CN210745020U - Envelope tracking power supply and electronic device - Google Patents
Envelope tracking power supply and electronic device Download PDFInfo
- Publication number
- CN210745020U CN210745020U CN201922052232.2U CN201922052232U CN210745020U CN 210745020 U CN210745020 U CN 210745020U CN 201922052232 U CN201922052232 U CN 201922052232U CN 210745020 U CN210745020 U CN 210745020U
- Authority
- CN
- China
- Prior art keywords
- circuit
- power supply
- output
- input
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The utility model relates to the technical field of communication, and provides an envelope tracking power supply and an electronic device, wherein in the envelope tracking power supply, a first input end of a linear amplification circuit is connected with a power supply input end, and a second input end of the linear amplification circuit is connected with a power supply output end; the first input end of the error amplifying circuit is connected with the output end of the linear amplifying circuit, and the second input end of the error amplifying circuit is connected with the output end of the power supply; the first input end of the control circuit is connected with the output end of the error amplifying circuit, and the second input end of the control circuit is connected with the output end of the delay circuit; the power supply switch circuit comprises a switch sub-circuit and a first inductor, the input end of the switch sub-circuit is connected with the output end of the control circuit, the output end of the switch sub-circuit is connected with the first end of the first inductor and connected with the input end of the delay circuit, and the second end of the first inductor is connected with the power supply output end. The embodiment of the utility model provides a can improve radio frequency PA's efficiency.
Description
Technical Field
The utility model relates to the field of communication technology, especially, relate to an envelope tracking power supply and electronic equipment.
Background
With the development of high-speed mobile communication, the peak-to-average ratio of radio frequency signals is higher. In the case of a high average peak ratio of the rf signal, a higher supply voltage and a higher instantaneous supply current are required for the rf PA (Power Amplifier) under the same average Power. But increasing the supply voltage only for the higher peak-to-average signal portion makes the rf PA less efficient.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides an envelope tracking power supply and electronic equipment to solve the lower problem of radio frequency PA's efficiency.
In order to solve the technical problem, the utility model discloses a realize like this:
in a first aspect, an embodiment of the present invention provides an envelope tracking power supply, including: the circuit comprises a power supply input end, a linear amplifying circuit, an error amplifying circuit, a control circuit, a delay circuit, a power supply switch circuit and a power supply output end;
the first input end of the linear amplification circuit is connected with the power supply input end, and the second input end of the linear amplification circuit is connected with the power supply output end;
the first input end of the error amplifying circuit is connected with the output end of the linear amplifying circuit, and the second input end of the error amplifying circuit is connected with the power supply output end;
the first input end of the control circuit is connected with the output end of the error amplification circuit, and the second input end of the control circuit is connected with the output end of the delay circuit;
the power supply switching circuit comprises a switch sub-circuit and a first inductor, the input end of the switch sub-circuit is connected with the output end of the control circuit, the output end of the switch sub-circuit is connected with the first end of the first inductor and the input end of the delay circuit, and the second end of the first inductor is connected with the power supply output end;
when the delay circuit outputs a closing signal, the control circuit is used for controlling the switch sub-circuit to close.
In a second aspect, an embodiment of the present invention provides an electronic device, which includes the envelope tracking power supply of the first aspect.
The embodiment of the utility model provides an in, envelope tracking power's power input end input transmitting signal, when transmitting signal's amplitude is different, common control through linear amplification circuit, error amplification circuit, control circuit, delay circuit, switch circuit makes envelope tracking power's the power output end voltage also different to make radio frequency PA's supply voltage follow transmitting signal's amplitude change, can improve radio frequency PA's efficiency.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of an envelope tracking power supply according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a delay circuit in an envelope tracking power supply according to an embodiment of the present invention;
fig. 3 is a second schematic structural diagram of a delay circuit in an envelope tracking power supply according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a control circuit in an envelope tracking power supply according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an envelope tracking power supply according to an embodiment of the present invention, and as shown in fig. 1, the envelope tracking power supply includes: the circuit comprises a power input end 1, a linear amplifying circuit 2, an error amplifying circuit 3, a control circuit 4, a delay circuit 5, a power switch circuit 6 and a power output end 7;
a first input end of the linear amplification circuit 2 is connected with the power supply input end 1, and a second input end of the linear amplification circuit 2 is connected with the power supply output end 7;
a first input end of the error amplifying circuit 3 is connected with an output end of the linear amplifying circuit 2, and a second input end of the error amplifying circuit 3 is connected with a power supply output end 7;
a first input end of the control circuit 4 is connected with an output end of the error amplifying circuit 3, and a second input end of the control circuit 4 is connected with an output end of the delay circuit 5;
the power switch circuit 6 comprises a switch sub-circuit 61 and a first inductor L1, the input end of the switch sub-circuit 61 is connected with the output end of the control circuit 4, the output end of the switch sub-circuit 61 is connected with the first end of the first inductor L1 and is connected with the input end of the delay circuit 5, and the second end of the first inductor L1 is connected with the power output end 7;
when the delay circuit 5 outputs a turn-off signal, the control circuit 4 is used for controlling the switch sub-circuit 61 to turn off.
The power input terminal 1 may be configured to input a transmission signal, and the transmission signal may be an envelope signal. The linear amplifying circuit 2 may include a linear envelope amplifier 21, and may compare a voltage difference value between a first input terminal and a second input terminal of the linear amplifying circuit 2, and when the voltage value of the first input terminal of the linear amplifying circuit 2 is higher than the voltage value of the second input terminal of the linear amplifying circuit 2, the output terminal of the linear amplifying circuit 2 may output an envelope signal to the first input terminal of the error amplifying circuit 3; when the voltage value of the first input terminal of the linear amplification circuit 2 is higher than the voltage value of the second input terminal of the linear amplification circuit 2, the linear amplification circuit 2 turns off the output. The error amplifying circuit 3 is used for starting the power switch circuit 6, when the output power of the output end of the linear amplifying circuit 2 is not enough to support the load operation, the output voltage of the power output end 7 is pulled low, thereby causing the voltage difference between the first input end of the error amplifying circuit 3 and the second input end of the error amplifying circuit 3 to be large, and starting the power switch circuit 6.
In addition, the power switch circuit 6 is used for increasing the output voltage of the power output end 7 and providing envelope tracking power main power output. When the power switch circuit 6 is in the on state, the output voltage of the power output terminal 7 is increased. The power switch circuit 6 includes a switch sub-circuit 61 and a first inductor L1, and the switch sub-circuit 61 may be a buck DC-DC circuit. When the switch sub-circuit 61 is in the on state, the switch sub-circuit 61 may output a high level to the first terminal of the first inductor L1, and when the switch sub-circuit 61 is in the off state, the switch sub-circuit 61 may output a low level to the first terminal of the first inductor L1.
It should be noted that the control circuit 4 may include an and logic gate and a not logic gate; or may also be a trigger; or it may be a circuit built from other logic gates. When the delay circuit 5 outputs a turn-off signal, the control circuit 4 is used for controlling the switch sub-circuit 61 to turn off, and when the delay circuit 5 outputs a turn-on signal, the control circuit 4 is used for controlling the input signal of the switch sub-circuit 61 to be the same as the output signal of the error amplifying circuit 3. For example, the off signal is at a high level, the on signal is at a low level, the switch sub-circuit 61 outputs a low level when it is off, and the output terminal of the control circuit 4 outputs a low level when the second input terminal of the control circuit 4 inputs a high level; in the case where the low level is input to the second input terminal of the control circuit 4, the control circuit 4 controls the input signal of the switch sub-circuit 61 to be the same as the output signal of the error amplifying circuit 3. After the output end of the switch sub-circuit 61 outputs the high level, the output end of the delay circuit 5 changes to the high level after the preset time period, so that the output end of the control circuit 4 outputs the low level, the switch sub-circuit 61 is controlled to be closed, and the output end of the switch sub-circuit 61 outputs the low level to reduce the output voltage. The preset duration is related to the structural parameters of the delay circuit 5. The delay circuit 5 can be a delay circuit built by a resistor, a capacitor and an inductor, and at the moment, the preset time length is related to the resistance value of the resistor, the capacitance of the capacitor and the inductance of the inductor; or the delay circuit 5 can be a delay circuit built by a metal-oxide-semiconductor field effect transistor (MOS). Different delay circuits 5 can be designed for debugging, and a proper delay circuit is selected according to a debugging result, so that the output ripple of the envelope tracking power supply is small.
It should be noted that, due to the time delay effect of the first inductor L1, when the switch sub-circuit 61 outputs a low level to the first end of the first inductor L1, the induced current of the first inductor L1 cannot suddenly change, so that the output voltage of the power output terminal 7 will continue to increase, and reach the peak value of the envelope tracking power supply. If the envelope tracking power supply is not provided with the delay circuit 5 and the control circuit 4, but the output end of the error amplifying circuit 3 is connected with the input end of the switch sub-circuit 61, it may happen that when the error amplifying circuit 3 detects that the output voltage of the power output end 7 is higher than the envelope signal voltage output by the output end of the linear amplifying circuit 2, the output end of the error amplifying circuit 3 controls the output end of the switch sub-circuit 61 to be at a low level, because of the delay effect of the first inductor L1, the output voltage of the power output end 7 will continue to be increased, thereby increasing the output ripple of the envelope tracking power supply, the output ripple is coupled to the radio frequency PA, and the performance of sending the radio frequency signal will be affected. The delay circuit 5 and the control circuit 4 increase the feedback of the control terminal of the switch sub-circuit 61 at the first terminal of the first inductor L1, thereby controlling the on and off of the power switch circuit 6. Before the output terminal of the error amplifying circuit 3 controls the output terminal of the switch sub-circuit 61 to be at the low level, the delay circuit 5 controls the output terminal of the control circuit 4 to output the low level, thereby controlling the output terminal of the switch sub-circuit 61 to be at the low level. The output ripple of the envelope tracking power supply can be reduced, the performance of sending radio frequency signals is optimized, and the power consumption of a system can be reduced.
The embodiment of the utility model provides an in, envelope tracking power supply's power input end 1 input transmission signal, when transmission signal's amplitude is different, the common control through linear amplification circuit 2, error amplification circuit 3, control circuit 4, delay circuit 5, switch circuit 6 makes the voltage of envelope tracking power supply output 7 output also different to make radio frequency PA's supply voltage follow transmission signal's amplitude change, can improve radio frequency PA's efficiency.
Optionally, as shown in fig. 2, the delay circuit 5 includes a second inductor L2, a first resistor R1, and a first capacitor C1;
the first end of the second inductor L2 is connected to the output end of the switch sub-circuit 61, the second end of the second inductor L2 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first resistor R1 is connected to the second input end of the control circuit 4, and the second end of the first capacitor C1 is grounded.
After the output terminal of the switch sub-circuit 61 outputs the high level, the second input terminal of the control circuit 4 can output the high level only after a certain delay time under the actions of the second inductor L2, the first resistor R1 and the first capacitor C1. The delay time of the delay circuit 5 can be calculated from the inductance of the second inductor L2, the resistance of the first resistor R1, and the capacitance of the first capacitor C1. When the close signal is at a high level, the open signal is at a low level, and the switch sub-circuit 61 outputs a low level when closed, the switch sub-circuit 61 outputs a high level, and before the output end of the error amplification circuit 3 controls the output end of the switch sub-circuit 61 to be at a low level, the delay circuit 5 controls the output end of the control circuit 4 to output a low level after a certain delay time, thereby controlling the output end of the switch sub-circuit 61 to be at a low level.
Optionally, as shown in fig. 3, the delay circuit 5 includes a second resistor R2, a second capacitor C2, and a first control switch Q1;
a first end of the second resistor R2 is connected to a first end of the first control switch Q1 and to an output end of the switch sub-circuit 61, a second end of the second resistor R2 is connected to a first end of the second capacitor C2, a second end of the second resistor R2 is connected to a second end of the first control switch Q1, a second end of the second capacitor C2 is grounded, and a third end of the first control switch Q1 is connected to a second input end of the control circuit 4.
After the output end of the switch sub-circuit 61 outputs the high level, the second input end of the control circuit 4 can output the high level after a certain delay time through the actions of the second resistor R2, the second capacitor C2 and the first control switch Q1. The delay time of the delay circuit 5 can be calculated from the resistance value of the second resistor R2 and the capacitance of the second capacitor C2.
Optionally, as shown in fig. 4, the control circuit 4 includes an and gate 41 and a not gate 42, a first input terminal of the and gate 41 is connected to the output terminal of the error amplifying circuit 3, a second input terminal of the and gate 41 is connected to the output terminal of the nand gate 42, an output terminal of the and gate 41 is connected to the input terminal of the switch sub-circuit 61, and an input terminal of the not gate 42 is connected to the output terminal of the delay circuit 5.
When the first input terminal and the second input terminal of the and gate 41 both input a high level, the output terminal of the and gate 41 outputs a high level. When the first input terminal or the second input terminal of the and gate 41 inputs the low level, the output terminal of the and gate 41 outputs the low level. When the input terminal of the not gate 42 inputs a high level, the output terminal of the not gate 42 outputs a low level, and when the input terminal of the not gate 42 inputs a low level, the output terminal of the not gate 42 outputs a high level. For example, when the off signal is at a high level, the on signal is at a low level, and the switch sub-circuit 61 outputs a low level when it is off, after the output terminal of the switch sub-circuit 61 outputs a high level, the output terminal of the delay circuit 5 changes to a high level after a preset time period, the output terminal of the not gate 42 outputs a low level, the output terminal of the and gate 41 outputs a low level, and the output terminal of the switch sub-circuit 61 outputs a low level to reduce the output voltage. After the output end of the switch sub-circuit 61 outputs the low level, the output end of the delay circuit 5 changes to the low level, the output end of the not gate 42 outputs the high level, the signal output by the output end of the and gate 41 is the same as the output signal of the error amplifying circuit 3, and when the error amplifying circuit 3 outputs the high level, the output end of the and gate 41 outputs the high level; when the error amplifying circuit 3 outputs a low level, the output terminal of the and gate 41 outputs a low level.
Optionally, as shown in fig. 1, the switch sub-circuit 61 includes a second control switch Q2, a third control switch Q3 and an inverter 611;
a first end of the second control switch Q2 is connected with the output end of the control circuit 4, a second end of the second control switch Q2 is used for inputting a supply voltage VCC, and a third end of the second control switch Q2 is connected with a first end of the first inductor L1;
an input end of the inverter 611 is connected to an output end of the control circuit 4, an output end of the inverter 611 is connected to a first end of the third control switch Q3, a second end of the third control switch Q3 is grounded, and a third end of the third control switch Q3 is connected to a first end of the first inductor L1.
When the output end of the control circuit 4 outputs a high level, the first terminal of the second control switch Q2 is at a high level, the second control switch Q2 is turned on, and the third terminal of the second control switch Q2 outputs a high level; meanwhile, the input end of the inverter 611 inputs a high level, the output end of the inverter 611 outputs a low level, and the first end of the third control switch Q3 is at a low level, so that the first end of the first inductor L1 is isolated from the ground, and thus the switch sub circuit 61 outputs a high level, which can increase the output voltage. When the output end of the control circuit 4 outputs a low level, the first terminal of the second control switch Q2 is at a low level, the second control switch Q2 is turned off, and the third terminal of the second control switch Q2 outputs a low level; meanwhile, the input end of the inverter 611 inputs a low level, the output end of the inverter 611 outputs a high level, and the first end of the third control switch Q3 is at a high level, so that the first end of the first inductor L1 is connected to ground, the switch sub circuit 61 outputs a low level, and after a certain time, the output voltage is reduced.
In this embodiment, the switch sub-circuit 61 is configured by the second control switch Q2, the inverter 611, and the third control switch Q3, so that the switch sub-circuit 61 can output a high level in the on state and a low level in the off state, and the circuit configuration is simple.
Optionally, the second control switch Q2 is a MOS transistor, and the third control switch Q3 is a MOS transistor.
The first terminal of the second control switch Q2 may be a gate of a MOS transistor, the second terminal of the second control switch Q2 may be a drain of the MOS transistor, and the third terminal of the second control switch Q2 may be a source of the MOS transistor. The first terminal of the third control switch Q3 may be a gate of a MOS transistor, the second terminal of the third control switch Q3 may be a drain of the MOS transistor, and the third terminal of the third control switch Q3 may be a source of the MOS transistor.
Optionally, as shown in fig. 1, the linear amplifying circuit 2 includes a linear envelope amplifier 21, a first input terminal of the linear envelope amplifier 21 is connected to the power supply input terminal 1, a second input terminal of the linear envelope amplifier 21 is connected to the power supply output terminal 7, and an output terminal of the linear envelope amplifier 21 is connected to a first input terminal of the error amplifying circuit 3.
Wherein, the voltage difference value of the first input terminal and the second input terminal of the linear envelope amplifier 21 can be compared, and when the voltage value of the first input terminal of the linear envelope amplifier 21 is higher than the voltage value of the second input terminal of the linear envelope amplifier 21, the output terminal of the linear envelope amplifier 21 can output the envelope signal to the first input terminal of the error amplifying circuit 3; when the voltage value of the first input terminal of the linear envelope amplifier 21 is higher than the voltage value of the second input terminal of the linear envelope amplifier 21, the linear envelope amplifier 21 turns off the output. The linear amplification circuit 2 is formed by the linear envelope amplifier 21, and has the advantages of high working bandwidth, high linearity of output voltage and simple structure.
Optionally, as shown in fig. 1, the error amplifying circuit 3 includes an error amplifier 31 and a third resistor R3;
a first end of the third resistor R3 is connected to the output end of the linear amplifying circuit 2, a first end of the third resistor R3 is connected to the first input end of the error amplifier 31, a second end of the third resistor R3 is connected to the power output end 7, and a second end of the third resistor R3 is connected to the second input end of the error amplifier 31;
an output of the error amplifier 31 is connected to a first input of the control circuit 4.
The linear amplifying circuit 2 needs to directly supply power to a load or a radio frequency PA, so that the resistance of the third resistor R3 disposed between the output terminal of the linear amplifying circuit 2 and the power output terminal 7 cannot be too large, so as to prevent the voltage division of the third resistor R3 from being too large, which results in too large output loss of the linear amplifying circuit 2, and the resistance of the third resistor R3 may be set to 0.2 Ω, or may be set to 0.5 Ω, and so on. The resistance of the third resistor R3 is small, the voltage across the third resistor R3 is small and is not enough to turn on the second control switch Q2, the voltage across the third resistor R3 is amplified by the error amplifier 31, and therefore the voltage output by the output end of the error amplifier 31 can reach the state of turning on the second control switch Q2.
The embodiment of the utility model provides an electronic equipment is still provided, electronic equipment includes the embodiment of the utility model provides an envelope tracking power.
The electronic equipment further comprises a radio frequency PA, and the envelope tracking power supply is connected with the radio frequency PA and used for supplying power to the radio frequency PA. Since other structures of the electronic device are the prior art, the envelope tracking power supply has been described in detail in the above embodiments, and therefore, details of the structure of the electronic device in this embodiment are not described again.
The above embodiments are only specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention, and all should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. An envelope tracking power supply, comprising: the circuit comprises a power supply input end, a linear amplifying circuit, an error amplifying circuit, a control circuit, a delay circuit, a power supply switch circuit and a power supply output end;
the first input end of the linear amplification circuit is connected with the power supply input end, and the second input end of the linear amplification circuit is connected with the power supply output end;
the first input end of the error amplifying circuit is connected with the output end of the linear amplifying circuit, and the second input end of the error amplifying circuit is connected with the power supply output end;
the first input end of the control circuit is connected with the output end of the error amplification circuit, and the second input end of the control circuit is connected with the output end of the delay circuit;
the power supply switching circuit comprises a switch sub-circuit and a first inductor, the input end of the switch sub-circuit is connected with the output end of the control circuit, the output end of the switch sub-circuit is connected with the first end of the first inductor and the input end of the delay circuit, and the second end of the first inductor is connected with the power supply output end;
when the delay circuit outputs a closing signal, the control circuit is used for controlling the switch sub-circuit to close.
2. The envelope tracking power supply of claim 1, wherein the delay circuit comprises a second inductor, a first resistor, and a first capacitor;
the first end of the second inductor is connected with the output end of the switch sub-circuit, the second end of the second inductor is connected with the first end of the first resistor, the second end of the first resistor is connected with the first end of the first capacitor, the second end of the first resistor is connected with the second input end of the control circuit, and the second end of the first capacitor is grounded.
3. The envelope tracking power supply of claim 1 wherein the delay circuit comprises a second resistor, a second capacitor, and a first control switch;
the first end of the second resistor is connected with the first end of the first control switch and connected with the output end of the switch sub-circuit, the second end of the second resistor is connected with the first end of the second capacitor, the second end of the second resistor is connected with the second end of the first control switch, the second end of the second capacitor is grounded, and the third end of the first control switch is connected with the second input end of the control circuit.
4. The envelope tracking power supply of claim 1, wherein the control circuit comprises an AND gate and a NOT gate, a first input terminal of the AND gate is connected to the output terminal of the error amplifying circuit, a second input terminal of the AND gate is connected to the output terminal of the NOT gate, an output terminal of the AND gate is connected to the input terminal of the switch sub-circuit, and an input terminal of the NOT gate is connected to the output terminal of the delay circuit.
5. The envelope tracking power supply of claim 1 wherein the switch subcircuit includes a second control switch, a third control switch, and an inverter;
a first end of the second control switch is connected with an output end of the control circuit, a second end of the second control switch is used for inputting a power supply voltage, and a third end of the second control switch is connected with a first end of the first inductor;
the input end of the inverter is connected with the output end of the control circuit, the output end of the inverter is connected with the first end of the third control switch, the second end of the third control switch is grounded, and the third end of the third control switch is connected with the first end of the first inductor.
6. The envelope tracking power supply of claim 5 wherein the second control switch is a MOS transistor and the third control switch is a MOS transistor.
7. The envelope tracking power supply of claim 1 wherein the linear amplification circuit comprises a linear envelope amplifier having a first input connected to the power supply input, a second input connected to the power supply output, and an output connected to the first input of the error amplification circuit.
8. The envelope tracking power supply of claim 1, wherein the error amplifying circuit comprises an error amplifier and a third resistor;
the first end of the third resistor is connected with the output end of the linear amplification circuit, the first end of the third resistor is connected with the first input end of the error amplifier, the second end of the third resistor is connected with the power supply output end, and the second end of the third resistor is connected with the second input end of the error amplifier;
the output end of the error amplifier is connected with the first input end of the control circuit.
9. An electronic device, characterized in that the electronic device comprises an envelope tracking power supply according to any of claims 1-8.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201922052232.2U CN210745020U (en) | 2019-11-25 | 2019-11-25 | Envelope tracking power supply and electronic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201922052232.2U CN210745020U (en) | 2019-11-25 | 2019-11-25 | Envelope tracking power supply and electronic device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN210745020U true CN210745020U (en) | 2020-06-12 |
Family
ID=71005831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201922052232.2U Active CN210745020U (en) | 2019-11-25 | 2019-11-25 | Envelope tracking power supply and electronic device |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN210745020U (en) |
-
2019
- 2019-11-25 CN CN201922052232.2U patent/CN210745020U/en active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7372333B2 (en) | Monolithic supply-modulated RF power amplifier and DC-DC power converter IC | |
US7492209B2 (en) | High-frequency switching device with reduced harmonics | |
CN101043181B (en) | Electric power supply circuit and electronic device having the same | |
KR101325158B1 (en) | Multy-Mode Dogerty Power Amplifier | |
CN104169826A (en) | Apparatus and methods for voltage converters | |
WO2023078063A1 (en) | Low-dropout linear regulator circuit and radio-frequency switch | |
JP2009201096A (en) | Switch circuit | |
JP2006025062A (en) | High frequency switch circuit | |
WO2004047351B1 (en) | Radio frequency power amplifier adaptive bias control circuit | |
CN214626968U (en) | Radio frequency device | |
CN104485907A (en) | High-efficiency multimode radio frequency power amplifier | |
US7439806B2 (en) | Bias control circuit and method of controlling bias of RF power amplifier | |
CN109194291A (en) | A kind of one chip low-noise amplifier of the high-gain High Linear with bypass functionality | |
CN107306118A (en) | Power amplifier module | |
US6498533B1 (en) | Bootstrapped dual-gate class E amplifier circuit | |
US7982444B2 (en) | Systems and methods for driving a transistor | |
CN210745020U (en) | Envelope tracking power supply and electronic device | |
US6255885B1 (en) | Low voltage transistor biasing | |
KR20090003182A (en) | Method and system for high power switching | |
CN209949056U (en) | Control circuit and signal receiving and transmitting device of GaN amplifier tube | |
CN218633923U (en) | Passive circuit under radio frequency receiving module bypass mode and radio frequency receiving module | |
CN218633922U (en) | Passive circuit under bypass mode of radio frequency receiving module and radio frequency receiving module | |
CN109327194A (en) | A kind of one chip low-noise amplifier of the broadband High Linear with bypass functionality | |
CN207283507U (en) | A kind of radio-frequency power amplifier output circuit with gain-adjusted | |
US20060006935A1 (en) | Amplifier |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |