CN210721196U - Electric sequential circuit of power driving device - Google Patents
Electric sequential circuit of power driving device Download PDFInfo
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- CN210721196U CN210721196U CN201922079456.2U CN201922079456U CN210721196U CN 210721196 U CN210721196 U CN 210721196U CN 201922079456 U CN201922079456 U CN 201922079456U CN 210721196 U CN210721196 U CN 210721196U
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Abstract
The utility model provides an electric sequential circuit of a power driving device, which comprises a processor power supply, a high-power device power supply, a diode, a first capacitor, a first resistor, a second capacitor, a second resistor, a third resistor and a high-power device; the first capacitor is respectively connected with a power supply and one end of the first resistor, one end of the second capacitor is connected with the power supply, and one end of the second resistor is connected with the power supply; one end of the diode is connected with a power supply of the processor, and the other end of the diode is connected with the high-power device; and two ends of the third resistor are respectively connected with a high-power device power supply and a high-power device. The utility model discloses utilize RC delay circuit, make the treater have sufficient initialization time when last electricity to through the enable pin of drawing high UC3705 logic device, make high-power device keep definite break-make state. The utility model discloses circuit structure is simple, and low cost can prevent effectively that high-power device from producing the spurious triggering phenomenon.
Description
Technical Field
The utility model particularly relates to an electric sequential circuit of power drive device.
Background
In order to reduce energy consumption and improve the running speed of a processor, multi-power supply is a common knowledge, a high-power device has high voltage and large current, and it is important to control the power-on time sequence to prevent the device from being triggered by mistake.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides an electric sequential circuit of power drive device, the utility model discloses a time delay circuit control goes up electric sequential to prevent that high-power device from producing the spurious triggering phenomenon during last electricity.
The technical scheme of the utility model is that:
an electric time sequence circuit of a power driving device is characterized by comprising a processor power supply, a high-power device power supply, a diode, a first capacitor, a first resistor, a second capacitor, a second resistor, a third resistor and a high-power device;
the first capacitor is connected with one end of the power supply and one end of the first resistor respectively, the first capacitor is connected with one end of the power supply and one end of the second resistor respectively, and an RC delay circuit can be formed through the arrangement.
One end of the second capacitor is connected with a power supply, and one end of the second resistor is connected with the power supply;
one end of the diode is connected with a power supply of the processor, and the other end of the diode is connected with the high-power device;
furthermore, two ends of the third resistor are respectively connected with a high-power device power supply and a high-power device.
Further, a processor output control signal is formed in the diode.
Further, a logic device is arranged in the diode.
Further, the logic device is a UC3705 logic device.
In the utility model, Power _ MCU is the Power supply of the processor; the MCU _ CONTROL is a CONTROL signal output by the processor and used for controlling the on-off of a Power supply (Power _ Drive) of the high-Power device; the RL is a high power device.
When the Power _ MCU is powered on, due to the existence of the RC delay circuit, the current firstly charges the capacitor C2 through the V1 branch, and when the capacitor C2 is fully charged (the delay is finished); the voltage of the positive electrode of the V1 to ground reaches the reverse breakdown voltage of V2 to turn on the V2, and then the V3 is turned on to make the (pin 7) of the D1 low; according to the characteristics (truth table) of a UC3705 device, after the power-on initialization of a processor is completed (delay is finished), keeping a low level; when the MCU _ CONTROL is at a low level, the Out signal is at a low level, and the RL does not work; when the MCU _ CONTROL is at a high level, the Out signal is at a high level, and the RL works. At this time, the processor can accurately control the on-off of the RL.
The utility model discloses the truth table of UC3705 is still provided, as shown in the following table.
The utility model discloses utilize RC delay circuit, make the treater have sufficient initialization time when last electricity to through the enable pin of drawing high UC3705 logic device, make high-power device keep definite break-make state. The utility model discloses circuit structure is simple, and low cost can prevent effectively that high-power device from producing the spurious triggering phenomenon.
Drawings
FIG. 1 is a schematic diagram of a timing circuit according to the present invention;
description of the symbols:
the Power _ MCU and the processor Power supply; power _ Drive, Power supply of high Power device; a diode, D1; a first capacitance, C1; a first resistance, R1; a second capacitance, C2; a second resistor, R2; a third resistor, R3; high power devices, RL; MCU _ CONTROL, processor output CONTROL signal.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Examples
An electric time sequence circuit of a power driving device comprises a processor power supply, a high-power device power supply, a diode, a first capacitor, a first resistor, a second capacitor, a second resistor, a third resistor and a high-power device;
the first capacitor is connected with one end of the power supply and one end of the first resistor respectively, the first capacitor is connected with one end of the power supply and one end of the second resistor respectively, and an RC delay circuit can be formed through the arrangement.
One end of the second capacitor is connected with a power supply, and one end of the second resistor is connected with the power supply;
one end of the diode is connected with a power supply of the processor, and the other end of the diode is connected with the high-power device;
furthermore, two ends of the third resistor are respectively connected with a high-power device power supply and a high-power device.
Further, a processor output control signal is formed in the diode.
Further, a logic device is arranged in the diode.
Further, the logic device is a UC3705 logic device.
In the utility model, when the Power _ MCU is powered on, the current will firstly charge the capacitor C2 through the V1 branch due to the existence of the RC delay circuit, and when the capacitor C2 is fully charged (the delay is finished); the voltage of the positive electrode of the V1 to ground reaches the reverse breakdown voltage of V2 to turn on the V2, and then the V3 is turned on to make the (pin 7) of the D1 low; according to the characteristics (truth table) of a UC3705 device, after the power-on initialization of a processor is completed (delay is finished), keeping a low level; when the MCU _ CONTROL is at a low level, the Out signal is at a low level, and the RL does not work; when the MCU _ CONTROL is at a high level, the Out signal is at a high level, and the RL works. At this time, the processor can accurately control the on-off of the RL.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art. It should be noted that the technical features not described in detail in the present invention can be implemented by any prior art.
Claims (4)
1. An electric time sequence circuit of a power driving device is characterized by comprising a processor power supply, a high-power device power supply, a diode, a first capacitor, a first resistor, a second capacitor, a second resistor, a third resistor and a high-power device;
the first capacitor is respectively connected with a power supply and one end of the first resistor, one end of the second capacitor is connected with the power supply, and one end of the second resistor is connected with the power supply;
one end of the diode is connected with a power supply of the processor, and the other end of the diode is connected with the high-power device;
and two ends of the third resistor are respectively connected with a high-power device power supply and a high-power device.
2. The electrical timing circuit of a power driver device of claim 1, wherein the diode forms a processor output control signal.
3. The electrical sequential circuit of the power driving device according to claim 1 or 2, wherein a logic device is provided in the diode.
4. The electrical sequential circuit of power driven devices of claim 3, wherein said logic device is a UC3705 logic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922079456.2U CN210721196U (en) | 2019-11-27 | 2019-11-27 | Electric sequential circuit of power driving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922079456.2U CN210721196U (en) | 2019-11-27 | 2019-11-27 | Electric sequential circuit of power driving device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210721196U true CN210721196U (en) | 2020-06-09 |
Family
ID=70932844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922079456.2U Active CN210721196U (en) | 2019-11-27 | 2019-11-27 | Electric sequential circuit of power driving device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210721196U (en) |
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2019
- 2019-11-27 CN CN201922079456.2U patent/CN210721196U/en active Active
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