CN210670383U - KU dual-output phase-locked loop high-efficiency low-noise frequency demultiplier - Google Patents
KU dual-output phase-locked loop high-efficiency low-noise frequency demultiplier Download PDFInfo
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- CN210670383U CN210670383U CN201921451021.XU CN201921451021U CN210670383U CN 210670383 U CN210670383 U CN 210670383U CN 201921451021 U CN201921451021 U CN 201921451021U CN 210670383 U CN210670383 U CN 210670383U
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Abstract
The utility model discloses a KU double-output phase-locked loop high-efficiency low-noise frequency demultiplier, which comprises a box body and a frequency demultiplier circuit arranged in the box body; the frequency-reducing circuit is provided with a receiving module, an amplifying module, a phase-locking module, a filtering module, an output module and a power supply module, wherein the receiving module, the amplifying module, the filtering module, the phase-locking module and the output module are electrically connected in sequence; the receiving module comprises a horizontal polarization receiving antenna and a vertical polarization receiving antenna; the phase-locking module comprises a double-output phase-locking integrated chip; the power supply module comprises a power supply integrated chip with functions of rectification, voltage stabilization and signal selection control. The power supply rectification and voltage stabilizing circuit of the frequency demultiplier are integrated in the chip, so that the application of peripheral devices and the application of a plurality of voltage stabilizing modules are effectively reduced, the stability is improved, and the cost is effectively reduced.
Description
Technical Field
The utility model relates to the field of electronics, especially a KU dual output high-efficient low noise frequency demultiplier of phase-locked loop.
Background
With the development of science and technology and life, communication transmission is more and more popular, and the proportion of satellite television watching in families is higher and higher. The frequency demultiplier is a necessary device for watching satellite television, but the products of the KU-band frequency demultiplier on the market have the noise-proof and anti-interference capability and the output function, which can not meet the requirements of customers. With the popularization of satellite televisions, an LNBF can only be provided for a single user side to watch full-band television programs, and the requirements of customers can not be met more and more; moreover, the manufacturing cost and the design cost of the industrial technology are increasingly under the condition of continuous progress and increasingly competitive market in recent years, and the enterprise is faced with more and more tests.
SUMMERY OF THE UTILITY MODEL
In order to solve the above problem, an object of the utility model is to provide a KU dual output high-efficient low noise frequency demultiplier of phase-locked loop integrates active device, the passive device of product, has reduced the application of peripheral device and a plurality of voltage stabilizing module, improves stability to effective reduce cost.
The utility model provides a technical scheme that its problem adopted is:
according to the utility model, the KU dual-output phase-locked loop high-efficiency low-noise frequency demultiplier comprises a box body and a frequency demultiplier circuit arranged in the box body;
the frequency-reducing circuit is provided with a receiving module, an amplifying module, a phase-locking module, a filtering module, an output module and a power supply module, wherein the receiving module, the amplifying module, the filtering module, the phase-locking module and the output module are electrically connected in sequence;
the receiving module comprises a horizontal polarization receiving antenna and a vertical polarization receiving antenna;
the phase-locking module comprises a double-output phase-locking integrated chip;
the power supply module comprises a power supply integrated chip with functions of rectification, voltage stabilization and signal selection control.
The KU dual-output phase-locked loop high-efficiency low-noise frequency demultiplier has the following beneficial effects: the power supply rectification and voltage stabilizing circuit of the frequency demultiplier are integrated in the chip, so that the application of peripheral devices and the application of a plurality of voltage stabilizing modules are effectively reduced, the stability is improved, and the cost is effectively reduced.
According to the utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, the amplification module includes primary amplification circuit and secondary amplification circuit.
According to the utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, primary amplification circuit and secondary amplification circuit connects gradually and sets up receiving module with between the filtering module.
According to the utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, including first coupling capacitance and second coupling capacitance, once amplifier circuit includes first amplifier circuit and second amplifier circuit, the second amplifier circuit includes third amplifier circuit and fourth amplifier circuit, first amplifier circuit passes through first coupling capacitance with third amplifier circuit connects, the second amplifier circuit passes through second coupling capacitance with fourth amplifier circuit connects.
According to the utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, including third coupling capacitance and fourth coupling capacitance, the filtering module includes first high pass filter and second high pass filter, the third amplifier circuit passes through third coupling capacitance with first high pass filter connects, the fourth amplifier circuit passes through fourth coupling capacitance with second high pass filter connects.
According to the utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, the phase-locked module includes the KTD1051 chip, the KTD1051 chip includes RFin1 pin, RFin2 pin, xd1 pin, xd2 pin, ifout1 pin, ifout2 pin, output module includes first delivery outlet and second delivery outlet.
According to the utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, first high pass filter with RFin1 pin is connected, the second high pass filter with RFin2 pin is connected, if out1 pin with first delivery outlet is connected, if out2 pin with the second delivery outlet is connected.
According to the utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, including the crystal oscillator chip, xd1 pin passes through the crystal oscillator chip with xd2 pin is connected.
According to the utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, power module includes TDK 1200.
The utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, TDK1200 includes Vch1 pin, Vch2 pin, Vpll pin, Tpc1 pin, Tpc2 pin, the KTD1051 chip still includes vddrf pin, vddrf2 pin, tpin1 pin, tpin2 pin, vddpll2 pin, Vch1 pin with vddrf pin connects, Vch2 pin with vddrf2 pin connects, Vpll pin with vddpll2 pin connects, TPc1 pin with tpin1 pin connects, TPc2 pin with tpin2 pin connects.
Drawings
The present invention will be further explained with reference to the drawings and examples.
Fig. 1 is a schematic circuit design diagram of an embodiment of a KU dual-output phase-locked loop high-efficiency low-noise block downconverter of the present invention;
fig. 2 is a circuit diagram of an embodiment of the KU dual-output phase-locked loop high-efficiency low-noise block downconverter of the present invention;
fig. 3 is a schematic diagram of an embodiment of the KU dual-output phase-locked loop high-efficiency low-noise block downconverter.
Detailed Description
This section will describe in detail the embodiments of the present invention, preferred embodiments of the present invention are shown in the attached drawings, which are used to supplement the description of the text part of the specification with figures, so that one can intuitively and vividly understand each technical feature and the whole technical solution of the present invention, but they cannot be understood as the limitation of the protection scope of the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship indicated with respect to the orientation description, such as up, down, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, a plurality of means are one or more, a plurality of means are two or more, and the terms greater than, less than, exceeding, etc. are understood as not including the number, and the terms greater than, less than, within, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless there is an explicit limitation, the words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in combination with the specific contents of the technical solution.
Referring to fig. 1-3, an embodiment of the present invention provides a KU dual-output phase-locked loop high-efficiency low-noise block downconverter, including a box body and a block down circuit disposed in the box body;
the frequency-reducing circuit comprises a receiving module 100, an amplifying module 200, a phase-locking module 400, a filtering module 300, an output module 500 and a power supply module, wherein the receiving module 100, the amplifying module 200, the filtering module 300, the phase-locking module 400 and the output module 500 are electrically connected in sequence;
the receiving module 100 includes a horizontally polarized receiving antenna and a vertically polarized receiving antenna;
the phase-locking module 400 includes a dual-output phase-locking integrated chip;
the power supply module comprises a power supply integrated chip with functions of rectification, voltage stabilization and signal selection control.
The power supply rectification and voltage stabilizing circuit of the frequency demultiplier are integrated in a chip, so that the application of peripheral devices and the application of a plurality of voltage stabilizing modules are effectively reduced, the stability is improved, and the cost is effectively reduced.
According to the utility model provides a pair of KU dual output high-efficient low noise block downconverter of phase-locked loop, amplification module 200 includes primary amplification circuit and secondary amplification circuit.
According to the utility model provides a pair of KU dual output high-efficient low noise block downconverter of phase-locked loop, primary amplification circuit and secondary amplification circuit connects gradually and sets up receiving module 100 with between the filter module 300.
The utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, including first coupling capacitance C8 and second coupling capacitance C23, once amplifier circuit includes first amplifier circuit and second amplifier circuit, the second amplifier circuit includes third amplifier circuit and fourth amplifier circuit, first amplifier circuit passes through first coupling capacitance C8 with the third amplifier circuit is connected, the second amplifier circuit passes through second coupling capacitance C23 with the fourth amplifier circuit is connected.
The utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, including third coupling capacitance C6 and fourth coupling capacitance C21, filtering module 300 includes first high pass filter and second high pass filter, the third amplifier circuit passes through third coupling capacitance C6 with first high pass filter connects, the fourth amplifier circuit passes through fourth coupling capacitance C21 with the second high pass filter connects.
According to the utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, phase-locked module 400 includes the KTD1051 chip, the KTD1051 chip includes RFin1 pin, RFin2 pin, xd1 pin, xd2 pin, ifout1 pin, ifout2 pin, output module 500 includes first delivery outlet and second delivery outlet.
According to the utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, first high pass filter with RFin1 pin is connected, the second high pass filter with RFin2 pin is connected, if out1 pin with first delivery outlet is connected, if out2 pin with the second delivery outlet is connected.
According to the utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, including the crystal oscillator chip, xd1 pin passes through the crystal oscillator chip with xd2 pin is connected.
According to the utility model provides a pair of KU dual output high-efficient low noise frequency demultiplier of phase-locked loop, power module includes TDK 1200.
The utility model provides a pair of KU dual output phase-locked loop high efficiency low noise frequency demultiplier, TDK1200 includes Vch1 pin, Vch2 pin, Vpll pin, Tpc1 pin, Tpc2 pin, the KTD1051 chip still includes vddrf pin, vddrf2 pin, tpin1 pin, tpin2 pin, vddpll2 pin, Vch1 pin with vddrf pin connects, Vch2 pin with vddrf2 pin connects, Vpll pin with vddpll2 pin connects, TPc1 pin with tpin1 pin connects, TPc2 pin with tpin2 pin connects.
According to the utility model provides a pair of the design principle of circuit in the high-efficient low noise frequency demultiplier of KU dual output phase-locked loop as follows:
1. the phase-locked chip KTD1051 is provided with a power supply circuit, a polarization switching circuit, a bias voltage generating circuit and other circuits which are not designed in the chip, so that radiation interference of various factors is effectively avoided, and a plurality of groups of bias voltage circuits, bias voltage generating circuits and the like are arranged in the phase-locked chip on the market; it will generate undesirable interference such as radiation to the rf circuit inside the chip.
2. The host power supply and the control system adopt KTD1200 combination to form a rectification, voltage stabilization and signal selection control integrated module to replace the traditional separated voltage stabilization and channel control circuit; in the current market, a power supply voltage stabilization chip, a group of 78LXX series chips are respectively used for each port to supply power to a phase locking chip and a voltage switching circuit, and a dual-output LNB (low noise amplifier) needs two groups of 78LXX chips, and the cost can be reduced by adopting a KTD1200 chip.
3. The filter module 300 (a first high-pass filter and a second high-pass filter) using the high-narrow-frequency comb-type microstrip line pilot frequency band pass is matched with a KTD1051 dual-output phase-locked integrated chip, and is connected with a KTD1200 to form an LNB with a power supply, channel control integration, two-input and two-output dual local oscillator 9.75GHz and 10.6 GHz. Because the oscillator is purely integrated with the phase lock, the interference between the local oscillators and the radiation of each circuit is reduced to the minimum, and the problems of mutual interference between the local oscillators and one or more times of frequency multiplication caused by signal resonance are effectively solved.
4. The power supply mode of a field effect tube and an independent negative feedback automatic regulating circuit are adopted; monitoring the instant start and normal working voltage of each field effect transistor; the field effect transistor is ensured to always keep the optimal state.
According to the utility model provides a pair of structure and functional description of circuit in KU dual output phase-locked loop high efficiency low noise frequency demultiplier:
satellite television signals are received by the LNB integrated body, and the satellite television signals with the communication protocol frequency band of 10.7 GHz-12.75 GHz are completely guided in by the waveguide tube; filtering by a metal structure to suppress and filter (frequencies before 10.7GHz and after 12.75 GHz), and receiving signals by a horizontal polarization mode or a vertical polarization mode; the signals are amplified by the primary amplifying circuit and the secondary amplifying circuit, then the external noise signals are filtered by the micro-strip high-pass filtering module 300, the signals are processed by the integrated phase-locked loop KTD1051, namely, the demodulated and amplified intermediate-frequency signals are divided into two groups, and finally the two groups of intermediate-frequency signals are output to the receiver set-top box through the coupling capacitors of the output modules 500. Wherein, the whole power system and the channel control circuit are provided by the KTD1200 integration module.
According to the utility model provides a pair of circuit theory of operation and explanation in KU dual output high-efficient low noise frequency demultiplier of phase-locked loop:
satellite signals are subjected to low-noise amplification through an H/horizontal polarization receiving antenna and an MOS-FET (CKRF7543) Q1 in a first amplifying circuit, and power supply voltage of the satellite signals is filtered by a third capacitor C3 and then is supplied to (-0.3-0.45V) through a current-limiting third resistor R3; the power supply voltage is filtered by a fourth capacitor C4 and then is provided by a current-limiting fourth resistor R4 (+ 2V-2.3V); meanwhile, a negative feedback automatic regulating circuit consisting of a sixth resistor R6, a third resistor R3 and a fourth resistor R4 ensures the optimal working linearity of the first capacitor Q1. The amplified signal is coupled to a MOS-FET (CK8513) Q2 of a third amplifying circuit by a first coupling capacitor C8, the power supply voltage of the amplified signal is filtered by a second capacitor C2 and is provided by a current-limiting second resistor R2, the power supply voltage is provided by the filtered first capacitor C1 and the current-limiting first resistor R1, and a negative feedback automatic regulating circuit which is composed of a sixth resistor R6, a third resistor R3 and a fourth resistor R4 amplifies the signal again. The signal after the secondary amplification is output to a first high-pass filter with high pass of the microstrip line through a third coupling capacitor C6 to filter out-of-band signals and noise; thus, a clean radio frequency signal is obtained and sent to an integrated phase-locked device IC1(KTD1501 chip) in the phase-locked module 400 to be subjected to phase discrimination, filtering and oscillation operation, and a local oscillation frequency of a 9.75/10.6GHz switchable type is obtained; the intermediate frequency signal of 950 MHz-2150 MHz is output through the first output port C5 and the second output port C28 after the internal mixing of the integrated phase-lock device IC1 and the amplification.
Satellite signals are subjected to low-noise amplification through a V/vertical polarization receiving antenna and an MOS-FET (CKRF7543) Q3 in a first amplifying circuit, and power supply voltage of the satellite signals is filtered by a twenty-ninth capacitor C29 and then is supplied to (-0.3-0.45V) through a seventeenth resistor R17 for current limitation; the power supply voltage is filtered by a twenty-sixth capacitor C26 and then is provided by a thirteenth current-limiting resistor R13 (+ 2V-2.3V); meanwhile, a negative feedback automatic regulating circuit consisting of a fifteenth resistor R15, a seventeenth resistor R17 and a thirteenth resistor R13 ensures the optimal working linearity of the third capacitor C3. The signal amplified by the second amplifying circuit is coupled to a MOS-FET (CK8513) Q4 in a fourth amplifying circuit by a second coupling capacitor C23, the power supply voltage of the signal is provided by a fourteenth current-limiting resistor R14 after being filtered by a twenty-seventh capacitor C27, the power supply voltage is provided by a twenty-fifth filtered capacitor C25 and a twelfth current-limiting resistor R12, and the signal is amplified again by a negative feedback automatic regulating circuit which consists of a sixteenth resistor R16, a fourteenth resistor R14 and a twelfth resistor R12. The signal after the secondary amplification is output to a second high-pass filter with high pass of the microstrip line through a fourth coupling capacitor C21 to filter out-of-band signals and noise; thus, a clean radio frequency signal is obtained and sent to an integrated phase-locked device IC1(KTD1501) in the phase-locked module 400 to be subjected to phase discrimination, filtering and oscillation operation, and a local oscillation frequency of a 9.75/10.6GHz switchable type is obtained; the intermediate frequency signal of 950 MHz-2150 MHz is output after internal mixing and amplification of the integrated phase-locked loop IC1, and is output to the first output port through the fifth capacitor C5 and the second output port through the twenty-eighth capacitor C28.
A Tp1 pin of the TDK1200 chip IC2 is connected with an ifout1 pin of a KTD1501 chip IC1 through a fifth capacitor C5, a Tpc1 pin of the TDK1200 chip IC2 is connected with a Tpin1 pin of the KTD1501 chip IC1, signals enter the TDK1200 chip IC2 through a Tp1 pin to be subjected to voltage stabilization processing, and control signals such as channel detection and voltage switching are output through a Tpc1 pin; and an ipin1 pin reaching the KTD1501 chip IC1 forms a signal channel for driving and controlling ports.
A Tp2 pin of the TDK1200 chip IC2 is connected with an ifout2 pin of a KTD1501 chip IC1 through a twenty-eighth capacitor C28, a Tpc2 pin of the TDK1200 chip IC2 is connected with a Tpin2 pin of a KTD1501 chip IC1, signals enter the TDK1200 chip IC2 through a Tp2 pin to be subjected to voltage stabilization processing, and control signals such as channel detection and voltage switching are output through a Tpc2 pin; the signal channel for driving and controlling the port is formed by a Tpin2 pin reaching the KTD1501 chip IC 1.
Above, only the preferred embodiment of the present invention has been described, the present invention is not limited to the above embodiment, and the technical effects of the present invention can be achieved by the same means, which all belong to the protection scope of the present invention.
Claims (10)
1. The utility model provides a KU dual output phase-locked loop high efficiency low noise frequency demultiplier which characterized in that: comprises a box body and a frequency reduction circuit arranged in the box body;
the frequency-reducing circuit is provided with a receiving module, an amplifying module, a phase-locking module, a filtering module, an output module and a power supply module, wherein the receiving module, the amplifying module, the filtering module, the phase-locking module and the output module are electrically connected in sequence;
the receiving module comprises a horizontal polarization receiving antenna and a vertical polarization receiving antenna;
the phase-locking module comprises a double-output phase-locking integrated chip;
the power supply module comprises a power supply integrated chip with functions of rectification, voltage stabilization and signal selection control.
2. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 1, wherein: the amplifying module comprises a primary amplifying circuit and a secondary amplifying circuit.
3. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 2, wherein: the primary amplifying circuit and the secondary amplifying circuit are sequentially connected and arranged between the receiving module and the filtering module.
4. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 3, wherein: the primary amplification circuit comprises a first amplification circuit and a second amplification circuit, the secondary amplification circuit comprises a third amplification circuit and a fourth amplification circuit, the first amplification circuit is connected with the third amplification circuit through the first coupling capacitor, and the second amplification circuit is connected with the fourth amplification circuit through the second coupling capacitor.
5. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 4, wherein: the filter module comprises a first high-pass filter and a second high-pass filter, the third amplification circuit is connected with the first high-pass filter through the third coupling capacitor, and the fourth amplification circuit is connected with the second high-pass filter through the fourth coupling capacitor.
6. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 5, wherein: the phase locking module comprises a KTD1051 chip, wherein the KTD1051 chip comprises an RFin1 pin, an RFin2 pin, an xd1 pin, an xd2 pin, an ifout1 pin and an ifout2 pin, and the output module comprises a first output port and a second output port.
7. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 6, wherein: the first high-pass filter is connected with the RFin1 pin, the second high-pass filter is connected with the RFin2 pin, the ifout1 pin is connected with the first output port, and the ifout2 pin is connected with the second output port.
8. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 6, wherein: the lead frame comprises a crystal oscillator chip, and the xd1 pin is connected with the xd2 pin through the crystal oscillator chip.
9. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 6, wherein: the power module includes a TDK 1200.
10. The KU dual-output phase-locked loop high-efficiency low-noise block downconverter of claim 9, wherein: the TDK1200 includes Vch1 pin, Vch2 pin, Vpll pin, Tpc1 pin, Tpc2 pin, the KTD1051 chip further includes vddrf pin, vddrf2 pin, tpin1 pin, tpin2 pin, vddpl 2 pin, Vch1 pin with vddrf pin is connected, Vch2 pin with vddrf2 pin is connected, Vpll pin with vddpl 2 pin is connected, Tpc1 pin with tpin1 pin is connected, Tpc2 pin with tpin2 pin is connected.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921451021.XU CN210670383U (en) | 2019-08-30 | 2019-08-30 | KU dual-output phase-locked loop high-efficiency low-noise frequency demultiplier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921451021.XU CN210670383U (en) | 2019-08-30 | 2019-08-30 | KU dual-output phase-locked loop high-efficiency low-noise frequency demultiplier |
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| CN210670383U true CN210670383U (en) | 2020-06-02 |
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| CN201921451021.XU Active CN210670383U (en) | 2019-08-30 | 2019-08-30 | KU dual-output phase-locked loop high-efficiency low-noise frequency demultiplier |
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