CN210668355U - Shared jumper wire structure suitable for MOS tube encapsulation - Google Patents
Shared jumper wire structure suitable for MOS tube encapsulation Download PDFInfo
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- CN210668355U CN210668355U CN201922204621.2U CN201922204621U CN210668355U CN 210668355 U CN210668355 U CN 210668355U CN 201922204621 U CN201922204621 U CN 201922204621U CN 210668355 U CN210668355 U CN 210668355U
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Abstract
The utility model relates to the technical field of MOS tube packaging, in particular to a common jumper structure suitable for MOS tube packaging, which comprises a source jumper body and a grid jumper body, wherein the source jumper body and the grid jumper body are in a left-right distribution structure, the source jumper body is provided with an outer frame, the upper part is a chip source electrode region welding boss matched with the weldable region area of a chip source electrode to be welded, the middle part is a first plane, the lower part is a chip source electrode pin welding boss with a fixed area, the grid jumper body is provided with an outer frame, the upper part is a chip grid electrode region welding boss matched with the weldable region area of a chip grid electrode to be welded, the middle part is a second plane, the lower part is a chip grid electrode pin welding boss with a fixed area, the appearance of the source jumper body and the grid jumper body and the area of the pin welding boss on the source jumper body are fixed, and the area of the chip welding boss, therefore, when the jumper structure die is developed for multiple chips, the die opening cost is reduced.
Description
Technical Field
The utility model relates to a MOS manages encapsulation technical field, especially relates to a sharing type wire jumper structure suitable for MOS manages encapsulation.
Background
In integrated circuit package technical field, when encapsulating the MOS tube device, the circuit connection between chip body and the chip pin is usually realized through using the wire jumper, but in the practical application process, because different MOS tube chips are different in size, if according to size classification, can have many kinds of MOS tube chips, if all design a wire jumper to each kind of MOS tube chip, then to chip package manufacturer, will produce high mould development expense, the design cost of wire jumper is too high, and then can lead to chip package cost high at rest, be unfavorable for chip package manufacturer to obtain higher market competition.
SUMMERY OF THE UTILITY MODEL
To the problem among the prior art, the utility model provides a sharing type wire jumper structure suitable for MOS manages encapsulation.
In order to realize the technical purpose, the technical proposal of the utility model is that:
a common jumper structure suitable for MOS tube packaging comprises a source jumper body and a gate jumper body, the source electrode jumper body and the grid electrode jumper body are in a left-right distribution structure, the source electrode jumper body is provided with an outer frame, the upper part of the source jumper body is a welding boss of a chip source electrode area, the middle part is a first plane, the lower part is a welding boss of a chip source electrode pin, the area of the welding lug boss of the chip source electrode area is matched with the area of the weldable area of the chip source electrode to be welded, the area of the welding lug boss of the chip source electrode pin is fixed, the grid jumper wire body is provided with an outer frame, the upper part of the grid jumper body is a welding boss of a chip grid region, the middle part of the grid jumper body is a second plane, the lower part of the grid jumper body is a welding boss of a chip grid pin, the area of the welding boss of the chip grid electrode area is matched with the area of the weldable area of the chip grid electrode to be welded, and the area of the welding boss of the chip grid electrode pin is fixed.
Preferably, the surface of the chip source region welding boss is circular, rectangular or regular polygon.
Preferably, the surface of the die gate region welding boss is circular, rectangular or regular polygonal.
Preferably, the die source region bonding pad and the die gate region bonding pad have the same height.
Preferably, the height of the chip source electrode pin welding boss is the same as that of the chip grid electrode pin welding boss.
Preferably, the upper width of the source jumper body is greater than the lower width.
Preferably, the upper width of the gate jumper body is smaller than the lower width.
Preferably, the connection positions of the first plane and the welding boss of the chip source electrode area and the welding boss of the chip source electrode pin are both slopes.
Preferably, the connection positions of the second plane and the welding boss of the chip grid region and the welding boss of the chip grid pin are both slopes.
As can be seen from the above description, the present invention has the following advantages:
the utility model fixes the shapes of the source jumper body and the grid jumper body, and the welding boss area of the chip grid pin and the welding boss area of the chip source pin on the two bodies, and sets the welding boss area of the chip source region and the welding boss area of the chip grid region on the two bodies to be adjustable, so when developing a jumper structure mould aiming at a plurality of types of chips, as the basic structure of the source jumper body and the basic structure of the grid jumper body are the same, a plurality of types of chips can share most of the structure of the mould, as long as partial mould parts corresponding to the chip source region welding boss on the source jumper body and the chip grid region welding boss on the grid jumper body are processed according to different chip sizes are developed, the mould opening cost of the jumper structure is greatly reduced, and simultaneously, when the jumper is filled, aiming at different chip welding boss jumper models, the welding equipment does not need to replace parts, can be directly started for operation, increases the convenience of operation and improves the production efficiency.
Drawings
Fig. 1 is a schematic structural diagram of the present invention;
fig. 2 is a schematic structural diagram of the source jumper body of the present invention;
fig. 3 is a schematic structural diagram of the gate jumper body of the present invention.
Detailed Description
With reference to fig. 1 to 2, a specific embodiment of the present invention is described in detail, but the present invention is not limited to the claims.
As shown in fig. 1 to 2, a common jumper structure suitable for MOS transistor packaging includes a source jumper body 1 and a gate jumper body 2, where the source jumper body 1 and the gate jumper body 2 are in a left-right distribution structure;
the source electrode jumper wire body 1 is provided with an outer frame 11, the upper part of the source electrode jumper wire body 1 is provided with a chip source electrode area welding boss 12, the middle part of the source electrode jumper wire body 1 is provided with a first plane 13, the lower part of the source electrode area welding boss is provided with a chip source electrode pin welding boss 14, the area of the chip source electrode area welding boss 12 is matched with the area of a chip source electrode area to be welded, the area of the chip source electrode pin welding boss 14 is fixed, the joint of the first plane 13 and the chip source electrode area welding boss 12 as well as the chip source electrode pin welding boss 14 is a slope 15;
the grid jumper body 2 is provided with an outer frame 21, the upper part of the grid jumper body 2 is a chip grid region welding boss 22, the middle part of the grid jumper body is a second plane 23, the lower part of the grid jumper body is a chip grid pin welding boss 24, the area of the chip grid region welding boss 22 is matched with that of a chip grid to be welded, the area of the chip grid pin welding boss 24 is fixed, the joint of the second plane 23 and the chip grid region welding boss 22 as well as the chip grid pin welding boss 24 is a slope 25, and the width of the upper part of the grid jumper body 2 is smaller than that of the lower part;
the chip source region bonding boss 12 and the chip gate region bonding boss 22 have the same height, and the chip source pin bonding boss 12 and the chip gate pin bonding boss 22 have the same height.
The utility model discloses total source electrode wire jumper body 1 is in the left side, and grid wire jumper body 2 is on the right side, with chip circuit design direction phase-match, and the structure is more reasonable.
In specific application, the surface of the welding boss of the source electrode area of the chip can be designed into a circular shape, a rectangular shape, a regular polygon shape or other irregular shapes according to the area of the welding area of the chip to be welded.
In specific application, the surface of the welding boss of the gate region of the chip can be designed into a circular shape, a rectangular shape, a regular polygon shape or other irregular shapes according to the area of the welding region of the chip to be welded.
The utility model discloses it is fixed with the appearance of source electrode wire jumper body and grid wire jumper body and the pin welding boss area on two bodies, and establish the chip welding boss area on two bodies to adjustable, thereby when developing wire jumper structure mould to many money chips, because the basic structure of grid wire jumper body and the basic structure of source electrode wire jumper body are the same, many money chips can share the most structure of mould, as long as according to the chip size development of difference corresponding to on the processing grid wire jumper body chip welding boss and the partial mould of source electrode wire jumper body can, greatly reduced wire jumper structure's die sinking expense.
To sum up, the utility model has the advantages of it is following:
the utility model fixes the shapes of the source jumper body and the grid jumper body, and the welding boss area of the chip grid pin and the welding boss area of the chip source pin on the two bodies, and sets the welding boss area of the chip source region and the welding boss area of the chip grid region on the two bodies to be adjustable, so when developing a jumper structure mould aiming at a plurality of types of chips, as the basic structure of the source jumper body and the basic structure of the grid jumper body are the same, a plurality of types of chips can share most of the structure of the mould, as long as partial mould parts corresponding to the chip source region welding boss on the source jumper body and the chip grid region welding boss on the grid jumper body are processed according to different chip sizes are developed, the mould opening cost of the jumper structure is greatly reduced, and simultaneously, when the jumper is filled, aiming at different chip welding boss jumper models, the welding equipment does not need to replace parts, can be directly started for operation, increases the convenience of operation and improves the production efficiency.
It should be understood that the above detailed description of the present invention is only for illustrative purposes and is not limited to the technical solutions described in the embodiments of the present invention. It will be understood by those skilled in the art that the present invention may be modified and equivalents may be substituted to achieve the same technical effects; as long as the use requirement is satisfied, the utility model is within the protection scope.
Claims (9)
1. The utility model provides a sharing type wire jumper structure suitable for MOS pipe encapsulation which characterized in that: including source electrode wire jumper body and grid wire jumper body, distribution structure about source electrode wire jumper body and grid wire jumper body are, source electrode wire jumper body has the outline, source electrode wire jumper body upper portion is the regional welding boss of chip source electrode, and the middle part is first plane, and the lower part is the regional welding boss of chip source electrode pin, the regional welding boss area of chip source electrode with by the regional area phase-match of welding chip source electrode, chip source electrode pin welding boss area is fixed, grid wire jumper body has the outline, grid wire jumper body upper portion is the regional welding boss of chip grid, and the middle part is the second plane, and the lower part is the regional welding boss of chip grid, the regional welding boss area of chip grid with by the regional area phase-match of welding chip grid, the regional welding boss area of chip grid is fixed.
2. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: the surface of the welding boss of the chip source electrode area is circular, rectangular or regular polygonal.
3. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: the surface of the welding boss of the chip grid electrode area is circular, rectangular or regular polygonal.
4. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: the welding boss of the chip source electrode area and the welding boss of the chip grid electrode area are the same in height.
5. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: the welding boss of the chip source electrode pin and the welding boss of the chip grid electrode pin are the same in height.
6. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: the width of the upper part of the source jumper body is larger than that of the lower part of the source jumper body.
7. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: the width of the upper part of the grid jumper body is smaller than that of the lower part of the grid jumper body.
8. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: the connection parts of the first plane and the welding boss of the chip source electrode area and the welding boss of the chip source electrode pin are both slope surfaces.
9. The common jumper structure suitable for MOS tube package as claimed in claim 1, wherein: and the joints of the second plane and the welding bosses of the chip grid region and the welding bosses of the chip grid pins are both slope surfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922204621.2U CN210668355U (en) | 2019-12-10 | 2019-12-10 | Shared jumper wire structure suitable for MOS tube encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922204621.2U CN210668355U (en) | 2019-12-10 | 2019-12-10 | Shared jumper wire structure suitable for MOS tube encapsulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210668355U true CN210668355U (en) | 2020-06-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922204621.2U Active CN210668355U (en) | 2019-12-10 | 2019-12-10 | Shared jumper wire structure suitable for MOS tube encapsulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210668355U (en) |
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2019
- 2019-12-10 CN CN201922204621.2U patent/CN210668355U/en active Active
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