CN210616556U

CN210616556U - Starting control device of manipulator

Info

Publication number: CN210616556U
Application number: CN201921398604.0U
Authority: CN
Inventors: 何定坤; 王光能; 张国平; 陈凯泽; 高云峰
Original assignee: Shenzhen Dazu Robot Co ltd; Han s Laser Technology Industry Group Co Ltd
Current assignee: Shenzhen Dazu robot Co.,Ltd.
Priority date: 2019-08-23
Filing date: 2019-08-23
Publication date: 2020-05-26
Anticipated expiration: 2029-08-23

Abstract

The application discloses a starting control device of a manipulator, which comprises a key input module for inputting a key trigger signal and a power input module for inputting a direct-current power supply, and further comprises a logic judgment module, a switch module, a power conversion module and a PFGA module, wherein the logic judgment module, the switch module, the power conversion module and the PFGA module are sequentially and electrically connected, the PFGA module is electrically connected with the logic judgment module, the key input module is electrically connected with the logic judgment module, and the power input module is electrically connected with the logic judgment module and the switch module; the logic judgment module is used for receiving the key trigger signal, and starting the switch module when the logic judgment is a starting signal based on circuit logic, the direct current power supply is transmitted to the power supply conversion module, and the power supply conversion module supplies power to the PFGA module after voltage reduction. By the device, the power consumption and the device cost of the starting circuit of the manipulator can be reduced.

Description

Starting control device of manipulator

Technical Field

The utility model relates to the field of electronic technology, especially, relate to a starting control device of manipulator.

Background

The mechanical arm is applied in various industries in a large scale, is an important part in the industries such as numerical control machine tools, packaging machinery, electronic special equipment, remote medical treatment and the like, and provides a huge market for the development of the mechanical arm industry along with the continuous promotion of the upgrading of the manufacturing industry.

When the mechanical arm is started, a starting circuit is usually needed to start, the traditional starting circuit detects whether a key is input through an MCU (micro controller Unit) module, when the MCU module detects that a key is pressed for two seconds, the MCU module controls a relay to be attracted, and a power supply supplies power to an FPGA (Field programmable gate Array) module to work after the relay is attracted. The traditional starting circuit design needs communication coordination among different devices, the complexity of the system is increased, meanwhile, the device cost is high, and the MCU module has certain power consumption when the power supply is switched on but the manipulator is not started.

Therefore, how to design a starting circuit of a manipulator, which can reduce cost and power consumption, is a technical problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a starting control device of manipulator can reduce the consumption and the device cost of the starting circuit of manipulator.

A starting control device of a manipulator comprises a key input module for inputting a key trigger signal, a power input module for inputting a direct-current power supply, a logic judgment module, a switch module, a power conversion module and a PFGA module, wherein the logic judgment module, the switch module, the power conversion module and the PFGA module are sequentially and electrically connected, the PFGA module is electrically connected with the logic judgment module, the key input module is electrically connected with the logic judgment module, and the power input module is electrically connected with the logic judgment module and the switch module;

the logic judgment module is used for receiving the key trigger signal, and starting the switch module when the logic judgment is a starting signal based on circuit logic, the direct current power supply is transmitted to the power supply conversion module, and the power supply conversion module supplies power to the PFGA module after voltage reduction.

Optionally, in one embodiment, the apparatus further includes a key detection module, the key detection module is electrically connected to the key input module and the PFGA module respectively, the key detection module is configured to detect the key trigger signal and send the detected key trigger signal to the PFGA module, and the PFGA module sends a corresponding control instruction to the logic determination module according to the key trigger signal to control the switch module to be turned off.

Optionally, in one embodiment, the apparatus further includes a teach pendant input module for inputting a control signal, the teach pendant input module is electrically connected to the PFGA module and is configured to send the control signal to the PFGA module, and the PFGA module sends a corresponding control command to the logic determination module according to the control signal to control the switch module to be turned off.

Optionally, in one embodiment, the logic determination module includes a voltage stabilizing unit, a filtering unit, a charging and discharging unit, a logic unit, and an FPGA control receiving unit, where the voltage stabilizing unit is electrically connected to the key input module, the voltage stabilizing unit, the filtering unit, the charging and discharging unit, and the logic unit are electrically connected in sequence, and one end of the FPGA control receiving unit is electrically connected to the PFGA module, and the other end of the FPGA control receiving unit is electrically connected to the logic unit;

the voltage stabilizing unit is used for stabilizing the voltage of the key trigger signal input by the key input module, the filtering unit is used for filtering, the charging and discharging unit is used for determining the delay time of the key trigger signal, the logic unit is used for logically judging the key trigger signal, and the FPGA control receiving unit is used for transmitting the control instruction sent by the PFGA module to the logic unit.

Optionally, in one embodiment, the voltage stabilizing unit includes a TVS diode, the filtering unit includes a first resistor and a first capacitor, the charging and discharging unit includes a second resistor, a second capacitor and a third capacitor, the logic unit includes a first nand gate chip, and the FPGA control receiving unit includes a third resistor, a fourth resistor, a fifth resistor and a first triode;

one end of the TVS diode is connected with the key input module, and the other end of the TVS diode is grounded; one end of the first resistor is connected with the key input module, the other end of the first resistor is connected with one end of the first capacitor, and the other end of the first capacitor is grounded; one end of the second resistor is connected between the first resistor and the first capacitor, the other end of the second resistor is connected with an input pin of the first NAND gate chip, one end of the second capacitor is connected with one end of the second resistor, the other end of the second capacitor is grounded, one end of the third capacitor is connected with one end of the second resistor, and the other end of the third capacitor is grounded; one end of the third resistor is connected with the PFGA module, the other end of the third resistor is grounded, one end of the fourth resistor is connected with the PFGA module, the other end of the fourth resistor is connected with the base electrode of the first triode, the emitting electrode of the first triode is grounded, the collecting electrode of the first triode is connected with one end of the fifth resistor, and the other end of the fifth resistor is connected with the input pin of the first NAND gate chip.

Optionally, in one embodiment, the switch module includes a voltage boosting unit and a switching tube unit, the voltage boosting unit is electrically connected to the logic determination module and the power input module, the switching tube unit is electrically connected to the power input module and the power conversion module, and the voltage boosting unit is configured to boost a circuit voltage to turn on the switching unit.

Optionally, in one embodiment, the voltage boosting unit includes an RC oscillator and a bootstrap circuit electrically connected;

the RC oscillator comprises a fourth capacitor, a second NAND gate chip and a fifth resistor, one end of the fourth capacitor is connected with the input end of the NOT gate chip, the other end of the fourth capacitor is grounded, one end of the fifth resistor is connected with the input end of the NOT gate chip, and the other end of the fifth resistor is connected with the output end of the second NAND gate chip;

the bootstrap circuit comprises a fifth capacitor, a sixth capacitor, a seventh capacitor, a second triode and a sixth resistor, wherein one end of the fifth capacitor is grounded, the other end of the fifth capacitor is connected with the power input module, one end of the sixth capacitor is grounded, the other end of the sixth capacitor is connected with the power input module, one end of the sixth resistor is connected with the power input module, the other end of the sixth resistor is connected with the switch tube unit, one end of the seventh capacitor is connected with the power input module, the other end of the seventh capacitor is connected with the switch tube unit, the base electrode of the second triode is connected to the output end of the second NAND gate chip, the emitter electrode of the second triode is connected with the power input module, and the collector electrode of the second triode is connected with the switch tube unit.

Optionally, in one embodiment, the switch tube unit includes an NMOS tube, a drain pin of the NMOS tube is connected to the power input module, a source pin of the NMOS tube is electrically connected to the power conversion module, and a gate of the NMOS tube is connected to the bootstrap circuit.

Optionally, in one embodiment, the key detection module includes a third nand gate chip and a third transistor, an input end of the third nand gate chip is connected to the key input module, an output end of the third nand gate chip is connected to a base of the third transistor, an emitter of the third transistor is grounded, and a collector of the third transistor is connected to the PFGA module.

Optionally, in one embodiment, the power conversion module includes a DC/DC voltage reduction circuit.

Implement the embodiment of the utility model provides a, will have following beneficial effect:

according to the starting control device of the manipulator, the key trigger signal is received through the logic judgment module, the switch module is started when the starting signal is judged based on the circuit logic, the direct-current power supply is transmitted to the power conversion module, the power conversion module supplies power to the PFGA module after voltage reduction, the circuit does not need to be started through an external MCU (micro control unit), the design complexity is simplified, the design cost and the manufacturing cost are reduced, the power supply only needs to supply power to a logic device with low power consumption before the manipulator is not started, and the power consumption of the starting circuit is greatly reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Wherein:

FIG. 1 is a block diagram showing an example of a starting control device of a robot;

FIG. 2 is a block diagram showing the construction of an activation control apparatus of a robot in another embodiment;

FIG. 3 is a schematic circuit diagram of an actuation control device for a robot in one embodiment;

FIG. 4 is a diagram illustrating the relationship between key input actions and respective dot levels according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. The first element and the second element are both components, but they are not the same component.

Fig. 1 is a block diagram showing a configuration of a start control device of a robot in one embodiment, which can reduce power consumption and device cost of a start circuit of the robot. As shown in fig. 1, the apparatus includes a key input module 110, a power input module 120, a logic determination module 130, a switch module 140, a power conversion module 150, and a PFGA module 160, wherein the logic determination module 130, the switch module 140, the power conversion module 150, and the PFGA module 160 are sequentially electrically connected, the PFGA module 160 is electrically connected to the logic determination module 130, the key input module 110 is electrically connected to the logic determination module 130, and the power input module 120 is electrically connected to the logic determination module 130 and the switch module 140.

The key input module 110 is configured to input a key trigger signal, the power input module 120 is configured to input a dc power, the logic determination module 130 is configured to receive the key trigger signal, and turn on the switch module 140 when it is determined that the logic determination module is a turn-on signal based on circuit logic, the dc power is transmitted to the power conversion module 150, and the power conversion module 150 supplies power to the PFGA module 160 after voltage reduction.

The starting control device of manipulator that this embodiment provided receives button trigger signal through logic judgement module to when judging for the start signal based on circuit logic, open switch module, DC power supply transmits to power conversion module, power conversion module gives after stepping down PFGA module power supply, through above-mentioned device, need not come the starting circuit through outside MCU, simplified design complexity, reduced design cost and manufacturing cost, and the power only need supply power for the logic device of low-power consumption before the manipulator does not start, greatly reduced starting circuit's consumption.

Fig. 2 is a structural block diagram of a start control device of a manipulator in another embodiment, the start control device of the manipulator further includes a key detection module 201d, the key detection module 201d is electrically connected to the key input module 202 and the PFGA module 201e, the key detection module 201d is configured to detect a key trigger signal and send the detected key trigger signal to the PFGA module 201e, the PFGA module 201e sends a corresponding control instruction to the logic determination module 201a according to the key trigger signal, and the logic determination module 201a controls the boosting unit 201b to be turned off to control the switching tube unit 201c to be turned off.

Further, please refer to fig. 2, the start control device of the manipulator further includes a teach pendant input module 204 for inputting a control signal, the teach pendant input module 204 is electrically connected to the PFGA module 201e and is configured to send the control signal to the PFGA module 201e, the PFGA module 201e sends a corresponding control command to the logic determination module 201a according to the control signal, and the logic determination module 201a controls the voltage boosting unit 201b to be turned off to control the switching tube unit 201c to be turned off.

Specifically, the key input module 202 generates a low level trigger signal and sends the low level trigger signal to the start-up motherboard 201, the power input module 203 supplies power to the whole system, the power input module 203 can specifically provide a 12Vdc power, the teach pendant input module 204 generates a control signal for software and sends the control signal to the start-up motherboard 201, and the start-up motherboard 201 is a control system and can receive the control signal and start or stop the power provided by the power input module 203.

The start-up motherboard 201 is composed of a logic judgment module 201a, a voltage boosting unit 201b, a switch tube unit 201c, a key detection module 201d, an FPGA module 201e, and a power conversion module 201 f. The logic determining module 201a detects a key trigger signal, which can distinguish a long key pressing action for more than 5S time or a short key pressing action for less than 2S time. For example, when the power input module 203 is powered on, if the logic determination module 201a detects a press-key operation for 2S, it will start the voltage boost unit 201b, after the voltage boost unit 201b is started, the MOS transistor of the switching transistor unit 301c is turned on, the power input module 203 supplies power to the power conversion module 201f, the power conversion module 201f may specifically include a DC/DC voltage-reducing circuit, and supplies power to the FPGA module 201e after voltage reduction by the DC/DC voltage-reducing circuit, and at this time, the manipulator system starts to operate. When the power input module 203 supplies power to the system and the manipulator is normally in a working state, if the logic judgment module 201a detects that the button action is performed for 2S, the logic judgment module starts the voltage boosting unit 201b, and the switching tube unit 201c is still in a turned-on state because the voltage boosting unit 201b is in a starting state; if the logic judgment module 201a detects a short 5S pressing, it turns off the voltage boosting unit 201b, and thus turns off the switching tube unit 201 c.

The button detection module 201d detects the state of the button input module 202 and transmits a signal to the FPGA module 201e, for example, when the manipulator system is not started, if the button detection module 201d detects a button input, it transmits a signal to the FPGA module 201e, and the FPGA module 201e does not work yet at this time, so the signal is ignored; when the manipulator system is in a normal working state, if the key detection module 201d detects a 2S key signal, the FPGA module 201e regards the button as a power-on action, and ignores the signal because the system is already working normally; when the manipulator system is in a normal working state, if the key detection module 201d detects a key signal greater than 5S, the FPGA module 201e regards as a shutdown key action, and after performing data storage and other actions, it sends a control command to the logic determination module 201a to turn off the voltage boosting unit 201b, thereby turning off the switching tube unit 201 c. The key input module 202 is a start key for turning on and off the manipulator. The power input module 203 supplies power for the starting mainboard, and the whole machine starts to work after being connected with commercial power.

Further, the teach pendant input module 204 is a manipulator operation interface, and when shutdown is controlled on the teach pendant interface, it sends a command to the FPGA module 201e, and after receiving the shutdown command, the FPGA module 201e stores data and performs other actions, and then sends a control command to the logic determination module 201a, and turns off the voltage boosting unit 201b, thereby turning off the switch tube unit 201 c.

The starting control device of the manipulator provided by the embodiment does not need to start a circuit through an external MCU (microprogrammed control Unit), simplifies the design complexity, reduces the design cost and the manufacturing cost, and greatly reduces the power consumption of the starting circuit because a power supply only needs to supply power to a logic device with low power consumption before the manipulator is not started.

Fig. 3 is a schematic circuit diagram of a start control device of a manipulator in an embodiment, in which a logic determination module includes a voltage stabilizing unit, a filtering unit, a charging and discharging unit, a logic unit, and an FPGA control receiving unit, the voltage stabilizing unit is electrically connected to the key input module, the voltage stabilizing unit, the filtering unit, the charging and discharging unit, and the logic unit are electrically connected in sequence, one end of the FPGA control receiving unit is electrically connected to the PFGA module, and the other end of the FPGA control receiving unit is electrically connected to the logic unit;

Specifically, referring to fig. 3, the logic circuit module includes a TVS transistor D1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R8, a resistor R9, a resistor R10, a resistor R12, a resistor R13, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a transistor Q2, a transistor Q4, a nand gate chip U1-B, and a nand gate chip U1-C. The voltage stabilizing unit comprises a TVS tube D1, the filtering unit comprises a resistor R1 and a capacitor C1, the charging and discharging unit comprises a resistor R2, a capacitor C2 and a capacitor C3, the logic unit comprises a NAND gate chip U1-B and a NAND gate chip U1-C, and the FPGA control receiving unit comprises a resistor R8, a resistor R9, a resistor R10 and a triode Q2.

Wherein, TVS tube D1 is connected to the input end of the key input module, resistor R1 and capacitor C1 form RC filter and are connected to the input end of the key input module, resistor R2, capacitor C2, capacitor C3 together form a secondary RC charge-discharge circuit and are connected to pin 9 of NAND gate chip U1-C, resistance-capacitance parameters of resistor R2, capacitor C2, and capacitor C3 determine the delay time of the key trigger signal, resistor R3 and resistor R4 are pulled up to +12V _ IN, two ends of capacitor C4 are connected to resistor R3, one end of resistor R4 is connected to pin 6 of NAND gate chip U1-B, one end of resistor R5 is connected to pin 4 of NAND gate chip U1-B, the other end is connected to capacitor C5 to form RC filter and is connected to pin 12 of NAND gate chip U1-D, one end of resistor R8 is pulled down to ground and is connected to receive control command 12V _ P from FPGA R9, the other end of the resistor R9 is connected to the base of a triode Q2, the emitter of the triode Q2 is grounded, the collector of the triode Q2 is connected to one end of a resistor R10, the other end of the resistor R10 is connected to the pin No. 9 of the NAND gate chip U1-C to form a loop of the FPGA control receiving unit, one end of the resistor R12 is connected to the pin No. 10 of the NAND gate chip U1-C, the other end of the resistor R12 is connected to the base of the triode Q4, the emitter of the triode Q4 is grounded, the collector of the triode Q4 is connected to one end of the resistor R13, and the other end of the resistor.

Furthermore, the switch module comprises a boosting unit and a switch tube unit which are electrically connected, the boosting unit is respectively electrically connected with the logic judgment module and the power input module, the switch tube unit is respectively electrically connected with the power input module and the power conversion module, and the boosting unit is used for boosting circuit voltage so as to start the switch unit.

Specifically, as shown in fig. 3, the boost unit includes a nand gate chip U1-D, a resistor R6, a resistor R7, a resistor R15, a capacitor C6, a capacitor C7, a capacitor C7, a capacitor C8, a diode Q5, a capacitor C9, and a capacitor C11. The boost unit comprises an RC oscillator and a bootstrap circuit which are electrically connected, the RC oscillator comprises a capacitor C6, a NAND gate chip U1-D and a resistor R6, and the bootstrap circuit comprises a capacitor C8, a capacitor C9, a capacitor C11, a diode Q5 and a resistor R15.

The No. 12 pin of the NAND gate chip U1-D is connected with a resistor R5 and a capacitor C5, one end of the capacitor C6 is grounded, the other end of the capacitor C6 is connected with the No. 13 pin of the NAND gate chip U1-D, one end of a resistor R6 is connected to the No. 13 pin of the NAND gate chip U1-D, the other end of the resistor R6 is connected to the No. 11 pin of the NAND gate chip U1-D, one end of the resistor R7 is connected to the No. 11 pin of the NAND gate chip U1-D, the capacitor C6, the NAND gate chip U1-D and the resistor R6 form an RC oscillator together. The other end of the resistor R7 is connected with a capacitor C7, one end of the capacitor C7 is connected with pin No. 3 of the diode Q5, pin No. 2 of the diode Q5 is connected with pin No. 4 of the MOS tube Q6, one end of the capacitor C8 is connected with the ground, the other end of the capacitor C8 is connected to +12V _ OUT, one end of the capacitor C9 is connected with the ground, the other end of the capacitor C9 is connected to +12V _ OUT, the resistor R15 is connected with the capacitor C11 in parallel, one end of the resistor R15 is connected to +12V _ OUT, and the other end of the resistor R15 is.

The switch tube unit comprises an NMOS tube, a drain electrode pin of the NMOS tube is connected with the power input module, a source electrode pin of the NMOS tube is electrically connected with the power conversion module, and a grid electrode of the NMOS tube is connected with the bootstrap circuit. Specifically, the pin No. 5, the pin No. 6, the pin No. 7 and the pin No. 8 representing the drain IN the NMOS transistor Q6 are all connected to +12V _ IN; the No. 1 pin, the No. 2 pin and the No. 3 pin representing the source electrode in the NMOS tube Q6 are all connected to +12V _ OUT; the NMOS transistor Q6 is used for realizing on-off switch for supplying power to the mainboard.

Further, the key detection module comprises a nand gate chip U1-a, a resistor R16, a resistor R17, a resistor R18, a capacitor C10 and a transistor Q3. The No. 1 pin and the No. 2 pin of the NAND gate chip U1-A are connected in parallel and then connected TO one end of a resistor R3, one end of the resistor R16 is connected TO the No. 3 pin of the NAND gate chip U1-A, the other end of the resistor R16 is connected TO one end of a capacitor C10, one end of a resistor R17 and the base of a triode Q3, the other end of the capacitor C10 is grounded, the other end of the resistor R17 is grounded, the emitter of the triode Q3 is grounded, the collector of the triode Q3 is pulled up TO a 3.3V power supply through the resistor R18, and meanwhile, a signal KEY _.

Further, the power conversion module comprises a DC/DC voltage reduction circuit, and the DC/DC voltage reduction circuit is used for reducing the voltage of the 12Vdc power supply and then supplying the reduced voltage to the FPGA module for use.

Furthermore, the FPGA module is a control core of the whole machine circuit and is used for receiving a signal of the key detection module, receiving a shutdown signal of the demonstrator and outputting a control instruction to the logic circuit module.

FIG. 4 is a diagram illustrating the relationship between key input actions and respective dot levels according to an embodiment. Wherein, the abscissa is the time axis, and the ordinate is signal level, and the ordinate signal includes: the KEY trigger signal KEY _ IN, a 6-pin signal U1_6 of the NAND gate chip U1-B, a 9-pin signal U1_9 of the NAND gate chip U1-C, a 4-pin signal U1_4 of the NAND gate chip U1-C, a 3-pin signal Q5_3 of the diode Q5, a 4-pin signal Q6_4 of the NMOS tube Q6 and a 1-pin signal Q6_1 of the NMOS tube Q6.

Specifically, after the power input module is powered on, the KEY _ IN is pressed for 2S at a point a, the level of the KEY _ IN is pulled low, and at this time, the level of the nand gate U1_6 also has a pull-down peak, which triggers the nand gate U1_4 to output a high level, and at the same time, the level of the nand gate U1_9 also has a certain drop, but because the resistor R2, the capacitor C2 and the capacitor C3 exist, the level of the pin is not enough to be pulled to a low level IN a short time, so the pin of the nand gate U1_9 cannot be triggered; meanwhile, the self-oscillation starts to work after the level of the NAND gate U1_4 is changed into high level, the control level of the diode Q5_3 comes from the level of the self-oscillation, the NMOS tube Q6_4 is changed into high level after the diode Q5_3 starts to work, the NMOS tube is conducted, the drain current of the NMOS tube flows to the source electrode through the NMOS, and the Q6_1 is changed into high level.

Further, if KEY _ IN is pressed for more than 5S at point B, the level of KEY _ IN will be pulled low, and at this time, the level of nand gate U1_6 will also have a pull-down peak, which triggers nand gate U1_4 to output a high level, because U1_4 originally outputs a high level, the level of U1_4 pin will not change; the level of the not gate U1_9 changes to low level at the point C simultaneously, because the energy existing in the resistor R2, the capacitor C2 and the capacitor C3 is discharged, the pin of the nand gate U1_9 will trigger to effective low level, the nand gate U1_9 changes to low level to trigger the nand gate U1_4 to low level, further leading to the self-oscillation stop, and finally the NMOS transistor Q6 turns off the output.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A starting control device of a manipulator comprises a key input module for inputting a key trigger signal and a power input module for inputting a direct-current power supply, and is characterized by further comprising a logic judgment module, a switch module, a power conversion module and a PFGA module, wherein the logic judgment module, the switch module, the power conversion module and the PFGA module are sequentially and electrically connected, the PFGA module is electrically connected with the logic judgment module, the key input module is electrically connected with the logic judgment module, and the power input module is electrically connected with the logic judgment module and the switch module;

2. The starting control device of the manipulator according to claim 1, further comprising a key detection module, wherein the key detection module is electrically connected to the key input module and the PFGA module, respectively, the key detection module is configured to detect the key trigger signal and send the detected key trigger signal to the PFGA module, and the PFGA module sends a corresponding control command to the logic determination module according to the key trigger signal to control the switch module to be turned off.

3. The manipulator start control device according to claim 1, further comprising a teach pendant input module for inputting a control signal, wherein the teach pendant input module is electrically connected to the PFGA module and configured to send the control signal to the PFGA module, and the PFGA module sends a corresponding control command to the logic determination module according to the control signal to control the switch module to turn off.

4. The starting control device of the manipulator according to any one of claims 1 to 3, wherein the logic judgment module comprises a voltage stabilization unit, a filter unit, a charging and discharging unit, a logic unit, and an FPGA control receiving unit, the voltage stabilization unit is electrically connected to the key input module, the voltage stabilization unit, the filter unit, the charging and discharging unit, and the logic unit are electrically connected in sequence, one end of the FPGA control receiving unit is electrically connected to the PFGA module, and the other end of the FPGA control receiving unit is electrically connected to the logic unit;

5. The starting control device of the manipulator according to claim 4, wherein the voltage stabilizing unit comprises a TVS diode, the filtering unit comprises a first resistor and a first capacitor, the charging and discharging unit comprises a second resistor, a second capacitor and a third capacitor, the logic unit comprises a first NAND gate chip, and the FPGA control receiving unit comprises a third resistor, a fourth resistor, a fifth resistor and a first triode;

6. The starting control device of the manipulator according to any one of claims 1 to 3, wherein the switch module includes a voltage boosting unit and a switching tube unit, the voltage boosting unit is electrically connected to the logic determination module and the power input module, the switching tube unit is electrically connected to the power input module and the power conversion module, and the voltage boosting unit is configured to boost a circuit voltage to turn on the switching tube unit.

7. The starting control device of the manipulator according to claim 6, wherein the booster unit includes an RC oscillator and a bootstrap circuit electrically connected;

8. The manipulator start-up control device according to claim 7, wherein the switching tube unit includes an NMOS tube, a drain terminal of the NMOS tube is connected to the power input module, a source terminal of the NMOS tube is electrically connected to the power conversion module, and a gate of the NMOS tube is connected to the bootstrap circuit.

9. The manipulator start control device according to claim 2, wherein the key detection module includes a third nand gate chip and a third transistor, an input terminal of the third nand gate chip is connected to the key input module, an output terminal of the third nand gate chip is connected to a base of the third transistor, an emitter of the third transistor is grounded, and a collector of the third transistor is connected to the PFGA module.

10. The start-up control device of a manipulator according to claim 1, wherein the power conversion module includes a DC/DC voltage step-down circuit.