CN210536530U - Voltage output stabilizing circuit based on NMOS (N-channel metal oxide semiconductor) tube - Google Patents
Voltage output stabilizing circuit based on NMOS (N-channel metal oxide semiconductor) tube Download PDFInfo
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- CN210536530U CN210536530U CN201921997520.9U CN201921997520U CN210536530U CN 210536530 U CN210536530 U CN 210536530U CN 201921997520 U CN201921997520 U CN 201921997520U CN 210536530 U CN210536530 U CN 210536530U
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Abstract
The utility model discloses a voltage output stabilizing circuit based on NMOS pipe, including transformer T1, NMOS pipe Q1, Q2, schottky diode D1-D4, resistance R1-R8, electric capacity C1, C2, wherein the grid of NMOS pipe Q1 is connected through resistance R1 to transformer T1 secondary coil's one end, simultaneously through diode D1, the drain electrode of NMOS pipe Q1 is connected to resistance R4, the grid of NMOS pipe Q1 is through resistance R2 ground connection, NMOS pipe Q1's source is through resistance R3 ground connection, electric capacity C1 is parallelly connected in resistance R3 both ends, NMOS pipe Q1's source is through diode D4 connection output Vout; the other end of the secondary coil of the transformer T1 adopts a circuit with the same structure. The utility model has the characteristics of circuit structure is simple, the low power dissipation, and the output is more stable.
Description
Technical Field
The utility model belongs to the technical field of the electronic circuit, concretely relates to voltage output stabilizing circuit based on NMOS pipe.
Background
The voltage stabilizing circuit is generally applied in circuit design and is commonly used for voltage conversion, how to achieve the voltage stabilizing circuit with stable output voltage based on the existing device is one of the design targets, and the NMOS tube is a voltage control device, has the characteristics of low impedance and low current when being conducted, and generates small power consumption. When the Schottky diode is conducted, the forward voltage is reduced, the reverse characteristic is good, and the generated power consumption is small. The voltage stabilizing circuit based on the two components has low self power consumption and more stable output voltage.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that needs to solve provides a voltage output stabilizing circuit based on NMOS pipe of circuit structure simple, low-power consumption, output stability.
In order to solve the above problems, the utility model adopts the following technical proposal:
a voltage output stabilizing circuit based on an NMOS tube comprises a transformer T1, NMOS tubes Q1 and Q2, Schottky diodes D1-D4, resistors R1-R8, capacitors C1 and C2, wherein one end of a secondary coil of the transformer T1 is connected with a grid electrode of the NMOS tube Q1 through a resistor R1, meanwhile, the secondary coil is connected with a drain electrode of the NMOS tube Q1 through a diode D1 and a resistor R4, the grid electrode of the NMOS tube Q1 is grounded through a resistor R2, a source electrode of the NMOS tube Q1 is grounded through a resistor R3, a capacitor C1 is connected with two ends of a resistor R3 in parallel, and a source electrode of the NMOS tube Q1 is connected with an output end Vout through a diode D4; the other end of the secondary coil of the transformer T1 is connected with the gate of an NMOS tube Q2 through a resistor R5, and is connected with the drain of an NMOS tube Q2 through a diode D2 and a resistor R8, the gate of the NMOS tube Q2 is grounded through a resistor R6, the source of the NMOS tube Q2 is grounded through a resistor R7, a capacitor C2 is connected in parallel with two ends of a resistor R7, and the source of the NMOS tube Q2 is connected with an output end Vout through a diode D3.
Adopt the produced beneficial effect of above-mentioned technical scheme to lie in:
the utility model discloses low current when utilizing the NMOS pipe to switch on, forward voltage reduces when low-impedance characteristic and schottky diode switch on, and low-power consumption voltage stabilizing circuit is constituteed jointly to the characteristic that reverse characteristic is good, has circuit simple structure, low power dissipation, exports more stable characteristics.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention;
Detailed Description
The utility model is described in further detail below with reference to the attached drawings:
as shown in fig. 1, the present invention includes a transformer T1, an NMOS transistor Q1, Q2, schottky diodes D1-D4, resistors R1-R8, capacitors C1, C2, wherein one end of the secondary coil of the transformer T1 is connected to the gate of the NMOS transistor Q1 through a resistor R1, and is connected to the drain of the NMOS transistor Q1 through a diode D1 and a resistor R4, the gate of the NMOS transistor Q1 is grounded through a resistor R2, the source of the NMOS transistor Q1 is grounded through a resistor R3, the capacitor C1 is connected to both ends of the resistor R3 in parallel, and the source of the NMOS transistor Q1 is connected to the output terminal Vout through a diode D4; the other end of the secondary coil of the transformer T1 is connected with the gate of an NMOS tube Q2 through a resistor R5, and is connected with the drain of an NMOS tube Q2 through a diode D2 and a resistor R8, the gate of the NMOS tube Q2 is grounded through a resistor R6, the source of the NMOS tube Q2 is grounded through a resistor R7, a capacitor C2 is connected in parallel with two ends of a resistor R7, and the source of the NMOS tube Q2 is connected with an output end Vout through a diode D3.
The working principle is as follows:
wherein: the resistor R1 and the resistor R2 form a voltage division circuit to control the conduction state of the NMOS tube Q1, and the resistor R5 and the resistor R6 form the voltage division circuit to control the conduction state of the NMOS tube Q2. The resistor R4 is used for current limiting protection of the Q1, and the resistor R8 is used for current limiting protection of the Q2.
When one end of the output end of the transformer T1 is positive voltage, D1, Q1 and D4 are turned on, D2, Q2 and D3 are turned off, the output voltage is rectified by a diode D1, and an NMOS tube Q1 is stabilized and then is output to Vout by a diode D4.
When the other end of the output end of the transformer T1 is positive voltage, D2, Q2 and D3 are turned on, D1, Q1 and D4 are turned off, the output voltage is rectified by a diode D2, and an NMOS tube Q2 is stabilized and then is output to Vout by a diode D3.
The capacitors C1 and C2 are filter capacitors.
Claims (1)
1. The utility model provides a voltage output stabilizing circuit based on NMOS pipe which characterized in that: the power supply comprises a transformer T1, NMOS tubes Q1 and Q2, Schottky diodes D1-D4, resistors R1-R8 and capacitors C1 and C2, wherein one end of a secondary coil of the transformer T1 is connected with the grid of the NMOS tube Q1 through the resistor R1, and is connected with the drain of the NMOS tube Q1 through the diode D1 and the resistor R4, the grid of the NMOS tube Q1 is grounded through the resistor R2, the source of the NMOS tube Q1 is grounded through the resistor R3, a capacitor C1 is connected with two ends of the resistor R3 in parallel, and the source of the NMOS tube Q1 is connected with an output end Vout through the diode D4; the other end of the secondary coil of the transformer T1 is connected with the gate of an NMOS tube Q2 through a resistor R5, and is connected with the drain of an NMOS tube Q2 through a diode D2 and a resistor R8, the gate of the NMOS tube Q2 is grounded through a resistor R6, the source of the NMOS tube Q2 is grounded through a resistor R7, a capacitor C2 is connected in parallel with two ends of a resistor R7, and the source of the NMOS tube Q2 is connected with an output end Vout through a diode D3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921997520.9U CN210536530U (en) | 2019-11-19 | 2019-11-19 | Voltage output stabilizing circuit based on NMOS (N-channel metal oxide semiconductor) tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921997520.9U CN210536530U (en) | 2019-11-19 | 2019-11-19 | Voltage output stabilizing circuit based on NMOS (N-channel metal oxide semiconductor) tube |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210536530U true CN210536530U (en) | 2020-05-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921997520.9U Active CN210536530U (en) | 2019-11-19 | 2019-11-19 | Voltage output stabilizing circuit based on NMOS (N-channel metal oxide semiconductor) tube |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210536530U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114675700A (en) * | 2022-04-02 | 2022-06-28 | 南通四建集团有限公司 | Scaffold safety inspection system |
| CN114688961A (en) * | 2022-04-02 | 2022-07-01 | 南通四建集团有限公司 | Scaffold frame warp detecting system device |
| CN114675700B (en) * | 2022-04-02 | 2024-06-07 | 南通四建集团有限公司 | Scaffold safety detection system |
-
2019
- 2019-11-19 CN CN201921997520.9U patent/CN210536530U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114675700A (en) * | 2022-04-02 | 2022-06-28 | 南通四建集团有限公司 | Scaffold safety inspection system |
| CN114688961A (en) * | 2022-04-02 | 2022-07-01 | 南通四建集团有限公司 | Scaffold frame warp detecting system device |
| CN114688961B (en) * | 2022-04-02 | 2024-01-26 | 南通四建集团有限公司 | Scaffold deformation detection system device |
| CN114675700B (en) * | 2022-04-02 | 2024-06-07 | 南通四建集团有限公司 | Scaffold safety detection system |
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