CN210488357U - Power supply path management circuit - Google Patents
Power supply path management circuit Download PDFInfo
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- CN210488357U CN210488357U CN201921724890.5U CN201921724890U CN210488357U CN 210488357 U CN210488357 U CN 210488357U CN 201921724890 U CN201921724890 U CN 201921724890U CN 210488357 U CN210488357 U CN 210488357U
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- 230000003068 static effect Effects 0.000 claims description 37
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000010248 power generation Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 description 9
- 239000003381 stabilizer Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000004134 energy conservation Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The utility model discloses a power path management circuit, include: the clock generating circuit comprises a clock generating circuit, a power supply control circuit, a power supply generating circuit and a load circuit, wherein a first output end of the clock generating circuit is electrically connected with an input end of the power supply control circuit, a second output end of the clock generating circuit is electrically connected with a first input end of the load circuit, an output end of the power supply control circuit is electrically connected with an input end of the power supply generating circuit, an output end of the power supply generating circuit is electrically connected with a second input end of the load circuit, and a low-power-consumption device is arranged in the power supply generating circuit. When the power supply path management circuit is applied to the chip, the power supply path can be switched timely when the chip is switched between a normal working mode and a dormant mode, and the power supply generation circuit is provided with a low-power-consumption device, so that the whole power consumption of the system is reduced while the normal work of the chip is ensured.
Description
Technical Field
The utility model relates to an electronic circuit technical field, concretely relates to power path management circuit.
Background
With the continuous progress of technology and the increasing functional demands of society on electronic products, the power consumption of the system is also continuously increased. With the goal of energy conservation globalization, power management of the system is necessary and essential.
The power management technology is also called as power control technology, most of current power management systems are realized by mode switching of loads, and the maximum energy conservation of the whole system is realized by controlling the system in a low power consumption mode.
However, due to different application scenarios, mode conversion in the prior art is monotonous and simple, so that power consumption of a power supply is not optimized. On the premise of realizing all requirements of products, how to effectively distribute power to different components of the system is the final goal of power management by reducing the energy consumption of the components when the components are idle and realizing the minimization of the power consumption of the whole system.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a solve above-mentioned technical problem, proposed following technical scheme:
in a first aspect, an embodiment of the present invention provides a power path management circuit, including: the clock generating circuit comprises a clock generating circuit, a power supply control circuit, a power supply generating circuit and a load circuit, wherein a first output end of the clock generating circuit is electrically connected with an input end of the power supply control circuit, a second output end of the clock generating circuit is electrically connected with a first input end of the load circuit, an output end of the power supply control circuit is electrically connected with an input end of the power supply generating circuit, an output end of the power supply generating circuit is electrically connected with a second input end of the load circuit, and a low-power-consumption device is arranged in the power supply generating circuit.
By adopting the implementation mode, when the power path management circuit is applied to the chip, the power path can be switched timely when the chip is switched between the normal working mode and the dormant mode, and the power path is switched due to the low-power-consumption device arranged in the power generation circuit, so that the whole power consumption of the system is reduced while the normal work of the chip is ensured.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the clock generation circuit includes a clock management unit, and the clock management unit is electrically connected to the power supply control circuit and the first input terminal of the load circuit, respectively.
With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the power control circuit includes a voltage regulator control unit, an action control unit, a first MOS switch and a second MOS switch, the voltage regulator control unit is electrically connected to the action control unit, the clock management unit, a gate of the first MOS switch and a gate of the second MOS switch, the action control unit is electrically connected to the clock management unit, drains of the first MOS switch and the second MOS switch are electrically connected to the power generation circuit, and sources of the first MOS switch and the second MOS switch are electrically connected to an external power supply.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the power generation circuit includes a switching regulator and an ultra-low static power consumption linear regulator, an input terminal of the switching regulator is electrically connected to a drain of the first MOS switch, an input terminal of the ultra-low static power consumption linear regulator is electrically connected to a drain of the second MOS switch, and output terminals of the switching regulator and the ultra-low static power consumption linear regulator are electrically connected to the load circuit.
With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the load circuit includes an uninterruptible working module and a turn-off module, a first end of the uninterruptible working module is electrically connected to output ends of the switching regulator and the ultra-low static power consumption linear regulator, respectively, and a second end of the uninterruptible working module is electrically connected to the clock management power supply; the first end of the turn-off module is electrically connected with the output ends of the switching regulator and the ultralow static power consumption linear regulator respectively, the second end of the turn-off module is electrically connected with the clock management power supply, and the third end of the turn-off module is electrically connected with the action control unit.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, a plurality of the turn-off modules are provided, and the plurality of turn-off modules are arranged in parallel.
With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, an external filter circuit is further disposed between the power generation circuit and the load circuit, a first end of the external filter circuit is electrically connected to the output ends of the switching regulator and the ultra-low static power consumption linear regulator, and a second end of the external filter circuit is electrically connected to the first end of the uninterruptible working module and the first end of the turn-off module.
With reference to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner of the first aspect, the external filter circuit includes an external inductor and an external capacitor, a first end of the external inductor is electrically connected to the output ends of the switching regulator and the ultra-low static power consumption linear regulator, a first end of the external capacitor is grounded, and a second end of the external inductor and a second end of the external capacitor are electrically connected to the first end of the uninterruptible working module and the first end of the turn-off module, respectively.
Drawings
Fig. 1 is a schematic diagram of a frame of a power path management circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power path management circuit according to an embodiment of the present invention;
in fig. 1-2, the symbols are represented as:
CMU-clock management unit, RCU-voltage stabilizer control unit, ACU-action control unit, M1-first MOS switch, M2-second MOS switch, eSR-switch voltage stabilizer, qLR-ultra low static power linear voltage stabilizer, AOL-uninterrupted operation module, EI-turn-off module, L1-external inductor, and C1-external capacitor.
Detailed Description
The present invention will be described with reference to the accompanying drawings and embodiments.
Fig. 1 is a schematic diagram of a frame of a power path management circuit provided in an embodiment of the present invention, referring to fig. 1, the power path management circuit in this embodiment includes: the clock generating circuit comprises a clock generating circuit, a power supply control circuit, a power supply generating circuit and a load circuit, wherein a first output end of the clock generating circuit is electrically connected with an input end of the power supply control circuit, a second output end of the clock generating circuit is electrically connected with a first input end of the load circuit, an output end of the power supply control circuit is electrically connected with an input end of the power supply generating circuit, and an output end of the power supply generating circuit is electrically connected with a second input end of the load circuit.
Further, the clock generation circuit described with reference to fig. 2 includes a clock management unit CMU electrically connected to the first input terminals of the power supply control circuit and the load circuit, respectively.
The power supply control circuit comprises a voltage stabilizer control unit RCU, an action control unit ACU, a first MOS switch M1 and a second MOS switch M2, wherein the voltage stabilizer control unit RCU is respectively electrically connected with the action control unit ACU, the clock management unit CMU, the grid electrode of the first MOS switch M1 and the grid electrode of the second MOS switch M2, the action control unit ACU is electrically connected with the clock management unit CMU, the drain electrodes of the first MOS switch M1 and the second MOS switch M2 are electrically connected with the power supply generation circuit, and the source electrodes of the first MOS switch M1 and the second MOS switch M2 are electrically connected with an external power supply.
The power generation circuit comprises a switching regulator eSR and an ultra-low static power consumption linear regulator qLR, wherein the input end of the switching regulator eSR is electrically connected with the drain electrode of the first MOS switch M1, the input end of the ultra-low static power consumption linear regulator qLR is electrically connected with the drain electrode of the second MOS switch M2, and the output end of the switching regulator eSR and the ultra-low static power consumption linear regulator qLR is electrically connected with the load circuit. The regulator control unit RCU controls the operating state of the switching regulator eSR and the operating state of the ultra-low static power consumption linear regulator qLR.
The load circuit comprises an uninterrupted operation module AOL and a turn-off module EI, wherein a first end of the uninterrupted operation module AOL is electrically connected with output ends of the switching regulator eSR and the ultra-low static power consumption linear regulator qLR respectively, and a second end of the uninterrupted operation module AOL is electrically connected with the clock management power supply; the first end of the turn-off module EI is electrically connected with the output ends of the switching regulator eSR and the ultra-low static power consumption linear regulator qLR, respectively, the second end of the turn-off module EI is electrically connected with the clock management power supply, and the third end of the turn-off module EI is electrically connected with the action control unit ACU. In this embodiment, the turn-off modules EI are provided in plurality, and a plurality of turn-off modules EI are arranged in parallel.
The power produce the circuit with still be provided with external filter circuit between the load circuit, external filter circuit's first end respectively with switching regulator eSR with the output electricity of ultralow static power consumption linear voltage regulator qLR is connected, external filter circuit's second end respectively with uninterrupted duty module AOL's first end and the first end electricity that can turn off module EI are connected. Further, the external filter circuit includes an external inductor L1 and an external capacitor C1, a first terminal of the external inductor L1 is electrically connected to the output terminals of the switching regulator eSR and the ultra-low static power linear regulator qLR, respectively, a first terminal of the external capacitor C1 is grounded, and a second terminal of the external inductor L1 and a second terminal of the external capacitor C1 are electrically connected to a first terminal of the uninterruptible operation module AOL and a first terminal of the turn-off module EI, respectively.
The output end of the switching regulator eSR and the output end of the ultra-low static power consumption linear regulator qLR are used as power output ports to connect an external inductor L1 and an external capacitor C1 filter circuit outside a chip, and the filter circuit supplies power to the uninterrupted operation module AOL and the turn-off module EI. The action control unit ACU is connected with the voltage regulator control unit RCU and the turn-off module EI, controls the working states of the switching voltage regulator eSR, the ultra-low static power consumption linear voltage regulator qLR and the turn-off module EIN, and returns a state signal; the clock management unit CMU supplies the clock signals required for the operation of the circuit to the action control unit ACU, the regulator control unit RCU and the turn-off module EI.
The embodiment of the utility model provides an in the power path management circuit is applicable to battery powered's system, through the operating condition realization low-power consumption of each module of control, power path management circuit has two kinds of mode: a normal operating mode and a sleep mode. Under the normal operating mode, stabiliser control unit RCU output low level control signal, control the gate of first MOS switch M1 makes first MOS switch M1 switches on, and the outside battery voltage of chip passes through first MOS switch M1's drain and source are received switching regulator eSR's input, switching regulator eSR is in the open mode, and its static power consumption is 60uA, can drive 100mA load, for uninterrupted duty module AOL and the module EI that can turn off provide operating voltage. The regulator control unit RCU outputs a high level control signal to control the gate of the second MOS switch M2, so that the second MOS switch M2 is turned off, and the ultra-low static power linear regulator qLR is in an off state. Under the sleep mode, regulator control unit RCU output low level control signal, control second MOS switch M2's grid makes second MOS switch M2 switches on, and outside battery voltage passes through second MOS switch M2's drain electrode and source are received ultra-low static power consumption linear voltage regulator qLR's input, ultra-low static power consumption linear voltage regulator qLR is in the on-state, and its static power consumption only 200nA can drive 300uA load, for uninterrupted duty module AOL provides operating voltage. The action control unit ACU outputs a high-level control signal to close the turn-off module EI, the voltage stabilizer control unit RCU outputs a high-level control signal to control the gate of the first MOS switch M1, so that the first MOS switch M1 is turned off, and the switching regulator eSR is in a turn-off state.
The embodiment of the utility model provides an in power path management circuit's work chronogenesis does: the power supply AVD is electrified, the enable signal EN is electrified, the high-resistance state of the signal VREG _ SEL is controlled, the switching regulator eSR and the ultra-low static power consumption linear regulator qLR work in the closed state, the external output voltage COUT starts the electrifying process, and the signals ROK _ SEL low level and ROK _ AVD high level are returned; after the power-on is finished, the switching regulator eSR is in an open state and supplies power to the load circuit, the ultra-low static power consumption linear regulator qLR is still in a closed state, the control signal VREG _ SEL is in a low level, and the return signals ROK _ SEL and ROK _ AVD are in a high level and a low level. When the next control signal VREG _ SEL low level comes and the signal becomes high level, the power supply path is switched, the switching regulator eSR is in a closed state, the ultra-low static power consumption linear regulator qLR is in an open state, and the signals ROK _ SEL low level and ROK _ AVD high level are returned; the control signal VREG _ SEL becomes low level, the power supply path is switched again, the switching regulator eSR is in an open state, the ultra-low static power consumption linear regulator qLR is in a closed state, and the return signals ROK _ SEL are high level and ROK _ AVD is low level; the enable signal EN is low level, the switching regulator eSR and the ultra-low static power consumption linear regulator qLR are turned off, there is no power output COUT to the outside, and the return signals ROK _ SEL are low level and ROK _ AVD high level.
It can be known from the foregoing embodiments that, this embodiment provides a power supply path management circuit, and the circuit is implemented by using a digital-analog hybrid process, and when a chip switches a working state between a normal working mode and a sleep mode, the power supply path management circuit applied to an ultra-low standby power supply can switch a power supply path in time, so that the overall power consumption of a system is reduced while the normal working of the chip is ensured. The power consumption of the ultra-low static power consumption linear voltage regulator qLR in the sleep mode is only 200nA, and the ultra-low static power consumption linear voltage regulator can be used in the form of a hard IP core, can also be transplanted according to different processes, and can be widely applied to the design of an MCU and an SOC.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Of course, the above description is not limited to the above examples, and technical features of the present invention that are not described in the present application may be implemented by or using the prior art, and are not described herein again; the above embodiments and drawings are only used for illustrating the technical solutions of the present invention and are not intended to limit the present invention, and if it is replaced, the present invention is only combined with and described in detail with reference to the preferred embodiments, and those skilled in the art should understand that changes, modifications, additions or substitutions made by those skilled in the art within the spirit of the present invention should also belong to the protection scope of the claims of the present invention.
Claims (8)
1. A power path management circuit, comprising: the clock generating circuit comprises a clock generating circuit, a power supply control circuit, a power supply generating circuit and a load circuit, wherein a first output end of the clock generating circuit is electrically connected with an input end of the power supply control circuit, a second output end of the clock generating circuit is electrically connected with a first input end of the load circuit, an output end of the power supply control circuit is electrically connected with an input end of the power supply generating circuit, an output end of the power supply generating circuit is electrically connected with a second input end of the load circuit, and a low-power-consumption device is arranged in the power supply generating circuit.
2. The power path management circuit of claim 1, wherein the clock generation circuit comprises a clock management unit electrically connected to the power control circuit and the first input of the load circuit, respectively.
3. The power path management circuit of claim 2, wherein the power control circuit comprises a voltage regulator control unit, an action control unit, a first MOS switch and a second MOS switch, the voltage regulator control unit is electrically connected to the action control unit, the clock management unit, a gate of the first MOS switch and a gate of the second MOS switch respectively, the action control unit is electrically connected to the clock management unit, drains of the first MOS switch and the second MOS switch are electrically connected to the power generation circuit, and sources of the first MOS switch and the second MOS switch are electrically connected to an external power supply.
4. The power path management circuit of claim 3, wherein the power generation circuit comprises a switching regulator and an ultra-low static power linear regulator, wherein an input of the switching regulator is electrically connected to a drain of the first MOS switch, an input of the ultra-low static power linear regulator is electrically connected to a drain of the second MOS switch, and outputs of the switching regulator and the ultra-low static power linear regulator are electrically connected to the load circuit.
5. The power path management circuit of claim 4, wherein the load circuit comprises an uninterruptible power module and a turn-off module, a first end of the uninterruptible power module is electrically connected to the output ends of the switching regulator and the ultra-low static power linear regulator, respectively, and a second end of the uninterruptible power module is electrically connected to the clock management power supply; the first end of the turn-off module is electrically connected with the output ends of the switching regulator and the ultralow static power consumption linear regulator respectively, the second end of the turn-off module is electrically connected with the clock management power supply, and the third end of the turn-off module is electrically connected with the action control unit.
6. The power path management circuit of claim 5, wherein the turn-off modules are provided in plurality, and wherein the turn-off modules are provided in parallel.
7. The power path management circuit according to claim 6, wherein an external filter circuit is further disposed between the power generating circuit and the load circuit, a first end of the external filter circuit is electrically connected to the output ends of the switching regulator and the ultra-low static power linear regulator, respectively, and a second end of the external filter circuit is electrically connected to the first end of the uninterruptible power module and the first end of the turn-off module, respectively.
8. The power path management circuit of claim 7, wherein the external filter circuit comprises an external inductor and an external capacitor, a first terminal of the external inductor is electrically connected to the output terminals of the switching regulator and the ultra-low static power linear regulator, respectively, a first terminal of the external capacitor is grounded, and a second terminal of the external inductor and a second terminal of the external capacitor are electrically connected to the first terminal of the uninterruptible operating module and the first terminal of the turn-off module, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921724890.5U CN210488357U (en) | 2019-10-15 | 2019-10-15 | Power supply path management circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921724890.5U CN210488357U (en) | 2019-10-15 | 2019-10-15 | Power supply path management circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210488357U true CN210488357U (en) | 2020-05-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921724890.5U Active CN210488357U (en) | 2019-10-15 | 2019-10-15 | Power supply path management circuit |
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|---|---|
| CN (1) | CN210488357U (en) |
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2019
- 2019-10-15 CN CN201921724890.5U patent/CN210488357U/en active Active
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