CN201690358U - Circuit structure for ensuring normal work state switching of submodules in multi-module system - Google Patents
Circuit structure for ensuring normal work state switching of submodules in multi-module system Download PDFInfo
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- CN201690358U CN201690358U CN 201020188499 CN201020188499U CN201690358U CN 201690358 U CN201690358 U CN 201690358U CN 201020188499 CN201020188499 CN 201020188499 CN 201020188499 U CN201020188499 U CN 201020188499U CN 201690358 U CN201690358 U CN 201690358U
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Abstract
A circuit structure for ensuring normal work state switching of submodules in a multi-module system solves the technical problem of ensuring normal work state switching of the submodules. The technical scheme adopted by the circuit structure includes that the circuit structure comprises a power supply module, a power supply module, a power supply management module and a group of the submodules, wherein the power supply module provides a work power supply for each loop, the power supply management module matches with the power supply module, and each submodule is composed of a field-effect tube switching circuit and a load. A residual voltage consumption circuit is additionally arranged inside a circuit structure of an arbitrary submodule; a control end of the power supply management module is connected with a controlled end of the residual voltage consumption circuit, and an output end of the field-effect tube switching circuit is connected with the residual voltage consumption circuit to be grounded. The circuit structure has the advantage of ensuring normal electrification of the submodules by switching in the matching residual voltage consumption circuit to an output end of the field-effect tube switching circuit and reducing voltage at input ends of the submodules to a permitted range.
Description
Technical field
The utility model relates to a kind of normal circuit structure that switches of submodule operating state that guarantees in multi-module system, belong to electronic technology field, and is particularly a kind of by residual voltage consumption circuit, realizes the circuit structure that submodule normally powers on.
Background technology
Fast development along with electronic technology, electronic equipment develops towards the direction of Highgrade integration, function modoularization, and along with the introducing of environmental protection, energy-saving and cost-reducing demand, and the demand of fault diagnosis functions etc., system often need close the working power of a module or several modules in certain occasion, to reach the purpose of energy-saving and cost-reducing and failure diagnosis, the power supply of restarting necessary submodule in due course is to realize the required function of user.As shown in Figure 1, in the prior art, power module is given other each module for power supply, and power management module also is responsible for the power management of each submodule except that finishing specific function.When the power supply of submodule is closed, we expect that the voltage that P is ordered is 0V, yet because each module also has a lot of signal circuits to be connected except working power in the multi-CPU system, the isolation that will all realize these signals need increase a large amount of devices, not only increase the complexity of system, and increased cost.Therefore these signal circuits can't be realized isolating one by one in actual design, the submodule of powered-down does not pour into weak current by these holding wires, cause the P point voltage greater than 0.7V, therefore when the submodule of closing re-powers, its working power is not to begin to power on from desirable 0V, can't operate as normal after causing submodule to power on.At this problem, prior art does not well solve, and has brought inconvenience for the work of this area.
Summary of the invention
The utility model will solve and guarantee the normal technical problem of switching of submodule operating state, designed and in multi-module system, guaranteed the normal circuit structure that switches of submodule operating state, insert supporting residual voltage by output and consume circuit at FET switch circuit, the input terminal voltage of submodule is reduced to allowed band, guarantee that submodule normally powers on.
The utility model for realizing the technical scheme that goal of the invention adopts is, in multi-module system, guarantee the normal circuit structure that switches of submodule operating state, being included as each loop in the above circuit structure provides the power module of working power, supporting power management module, and one group of submodule of forming by FET switch circuit and load, have additional residual voltage in the circuit structure of above-mentioned norator module and consume circuit, the control end of power management module connects the controlled end that residual voltage consumes circuit, and the output of FET switch circuit connects residual voltage consumption circuit and goes into ground.
The beneficial effects of the utility model are: insert supporting residual voltage by the output at FET switch circuit and consume circuit, the input terminal voltage of submodule is reduced to allowed band, guarantee that submodule normally powers on.
Below in conjunction with accompanying drawing the utility model is elaborated.
Description of drawings
Fig. 1 is the structure principle chart of multi-module system in the prior art.
Fig. 2 is a structure principle chart of the present utility model.
Fig. 3 is a specific embodiment of the present utility model.
In the accompanying drawing, 1 power module, 2 power management modules, 3 submodules, the 3-1 FET switch circuit, the 3-2 load, the 3-3 residual voltage consumes circuit, U1 current limliting chip.
Embodiment
Referring to Fig. 2, in multi-module system, guarantee the normal circuit structure that switches of submodule operating state, being included as each loop in the above circuit structure provides the power module 1 of working power, supporting power management module 2, and one group of submodule 3 of forming by FET switch circuit 3-1 and load 3-2, have additional residual voltage in the circuit structure of above-mentioned norator module 3 and consume circuit 3-3, the control end of power management module 2 connects the controlled end that residual voltage consumes circuit 3-3, and the output of FET switch circuit 3-1 connects residual voltage consumption circuit 3-3 and goes into ground.
Above-mentioned residual voltage consumes circuit 3-3 and is made up of current limliting chip U1, the controlled end of current limliting chip U1 connects the control end of power management module 2, the input of current limliting chip U1 connects the output of FET switch circuit 3-1, the ground pin ground connection of current limliting chip U1.
Above-mentioned current limliting chip U1 inside is provided with the logic sum gate circuit, the B input pin ground connection of logic sum gate circuit, the A input pin connects the control end of power management module 2 as the controlled end of current limliting chip U1, and the Y pin is connected the output of FET switch circuit 3-1 as the logic output terminal of the input of current limliting chip U1 and logic gates.
The model of above-mentioned current limliting chip U1 is NC7SZ32P5X.
A specific embodiment of the present utility model, referring to Fig. 3, residual voltage consumes circuit 3-3 and is made up of the current limliting chip U1 that inside is provided with the logic sum gate circuit, pin A, the B of current limliting chip U1 is two inputs of logic sum gate circuit, input B ground connection wherein, another input A is as the control end of the controlled end connection power management module 2 of current limliting chip U1, and the input of current limliting chip U1 connects the output of FET switch circuit 3-1.Power management module 2 controls FET switch circuit 3-1 simultaneously and residual voltage consumes circuit 3-3, power management module 2 output high level under the normal operating conditions, the fet switch conducting, the pin A of current limliting chip U1 is a high level, the logic sum gate circuit is output as high level, submodule 3 operate as normal; During power management module 2 output low levels, fet switch is closed, and supply voltage begins to descend, and the logic sum gate circuit is output as low level and begins absorption current (being no more than 90mA usually), final supply voltage drops near 0V, has guaranteed normally closing of submodule 3; When power management module 2 is exported high level once more, fet switch is opened, supply voltage begins to rise from 0V, the logic sum gate circuit is output as high level and pours into electric current (being no more than 90mA usually) to load 3-2 simultaneously, final supply voltage rises to normal working voltage, and submodule 3 is finished normal startup; So far finished the following electricity of submodule 3 and re-powered process, submodule is able to start smoothly and operate as normal.
Claims (4)
1. in multi-module system, guarantee the normal circuit structure that switches of submodule operating state, being included as each loop in the above circuit structure provides the power module of working power (1), supporting power management module (2), and one group of submodule (3) of forming by FET switch circuit (3-1) and load (3-2), it is characterized in that: have additional residual voltage in the circuit structure of described norator module (3) and consume circuit (3-3), the control end of power management module (2) connects the controlled end that residual voltage consumes circuit (3-3), and the output of FET switch circuit (3-1) connects residual voltage consumption circuit (3-3) and goes into ground.
2. the normal circuit structure that switches of submodule operating state that in multi-module system, guarantees according to claim 1, it is characterized in that: described residual voltage consumes circuit (3-3) and is made up of current limliting chip (U1), the controlled end of current limliting chip (U1) connects the control end of power management module (2), and the input of current limliting chip (U1) connects the output of FET switch circuit (3-1).
3. the normal circuit structure that switches of submodule operating state that in multi-module system, guarantees according to claim 2, it is characterized in that: described current limliting chip (U1) inside is provided with the logic sum gate circuit, the B input pin ground connection of logic sum gate circuit, the A input pin is connected the control end of power management module (2), and the Y pin is connected the output of FET switch circuit (3-1).
4. the normal circuit structure that switches of submodule operating state that guarantees in multi-module system according to claim 2, it is characterized in that: the model of described current limliting chip (U1) is NC7SZ32P5X.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020188499 CN201690358U (en) | 2010-05-07 | 2010-05-07 | Circuit structure for ensuring normal work state switching of submodules in multi-module system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020188499 CN201690358U (en) | 2010-05-07 | 2010-05-07 | Circuit structure for ensuring normal work state switching of submodules in multi-module system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201690358U true CN201690358U (en) | 2010-12-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201020188499 Expired - Lifetime CN201690358U (en) | 2010-05-07 | 2010-05-07 | Circuit structure for ensuring normal work state switching of submodules in multi-module system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201690358U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014100968A1 (en) * | 2012-12-25 | 2014-07-03 | 华为终端有限公司 | Power supply circuit and wireless network card |
| CN107530539A (en) * | 2015-02-26 | 2018-01-02 | 睿博专利有限公司 | It is used for equipment and the associated percutaneous electrode that functional electrostimulation and electromyogram measure including the device for making electrode pair short circuit and being grounded |
-
2010
- 2010-05-07 CN CN 201020188499 patent/CN201690358U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014100968A1 (en) * | 2012-12-25 | 2014-07-03 | 华为终端有限公司 | Power supply circuit and wireless network card |
| CN107530539A (en) * | 2015-02-26 | 2018-01-02 | 睿博专利有限公司 | It is used for equipment and the associated percutaneous electrode that functional electrostimulation and electromyogram measure including the device for making electrode pair short circuit and being grounded |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN GONGJIN ELECTRONIC CO., LTD. Free format text: FORMER NAME: SHENZHEN GONGJIN ELECTRONICS CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 518000, Shenzhen, Guangdong province Nanshan District Shekou Nanhai Road 1019, 100 surplus medical instrument Park, two floor Patentee after: Shenzhen Gongjin Electronics Co., Ltd. Address before: 518000, Shenzhen, Guangdong province Nanshan District Shekou Nanhai Road 1019, 100 surplus medical instrument Park, two floor Patentee before: Shenzhen Gongjin Electronics Co., Ltd. Address after: 518000, Shenzhen, Guangdong province Nanshan District Shekou Nanhai Road 1019, 100 surplus medical instrument Park, two floor Patentee after: Shenzhen Gongjin Electronics Co., Ltd. Address before: 518000, Shenzhen, Guangdong province Nanshan District Shekou Nanhai Road 1019, 100 surplus medical instrument Park, two floor Patentee before: Shenzhen Gongjin Electronics Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101229 |