CN210469265U - Level signal conversion circuit, PON chip and optical module - Google Patents
Level signal conversion circuit, PON chip and optical module Download PDFInfo
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- CN210469265U CN210469265U CN201921052233.0U CN201921052233U CN210469265U CN 210469265 U CN210469265 U CN 210469265U CN 201921052233 U CN201921052233 U CN 201921052233U CN 210469265 U CN210469265 U CN 210469265U
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Abstract
The utility model discloses a level signal conversion circuit, PON chip and optical module relates to the optical communication technology field, and the level signal conversion circuit includes phase inverter, AND gate, first transistor, second transistor, first resistance, second resistance and power; the input end of the phase inverter is connected with the first level signal, the output end of the phase inverter is connected with the first end of the second crystal, one input end of the AND gate is connected with the second level signal, the other input end of the AND gate is connected with the output end of the phase inverter, and the output end of the AND gate is connected with the first end of the first transistor; the first resistor and the second resistor are connected in series and then connected with the second end of the second transistor, and the other end of the first resistor is connected with a power supply; the second end of the first transistor is connected between the first resistor and the second resistor, and the connection point of the first resistor and the second resistor is taken as an output control signal.
Description
Technical Field
The utility model relates to an optical communication technical field, concretely relates to level signal converting circuit, PON chip and optical module.
Background
In the optical communication transmission process, an optical module is a relatively common optoelectronic device and is mainly used for performing photoelectric and electro-optical conversion, a transmitting end of the optical module converts an electric signal into an optical signal, and a receiving end of the optical module converts the optical signal into an electric signal.
Generally, an optical module generally adopts an SFP + package, the number of pins of the package is limited, and a control signal of the pins of the optical module is provided by a PON chip, and in general, the PON chip provides a one-to-one control signal for each pin of the optical module, where the control signal is a high-level or low-level signal.
However, as the technology of the optical module continuously evolves, in practical applications, the optical module needs to be compatible with multiple working modes, and therefore, in the prior art, the pin definition of the SFP + package is modified, and pins that need to be extended are directly added to make the optical module compatible with multiple working modes.
However, since the pins of the PON chip and the optical module are one-to-one, when the number of the pins of the optical module increases, the pins of the PON chip connected to the optical module also need to be changed, so that the PON chip becomes a non-standard component, and the components of the non-standard component inevitably increase the cost, and have low universality and limited application range, thereby causing resource waste.
SUMMERY OF THE UTILITY MODEL
To the defect that exists among the prior art, the utility model aims to provide a level signal conversion circuit can be exported two level signal conversion for a control signal, can obtain the control signal COM of three kinds of differences, when being applied to the optical module with this level signal conversion circuit, only need be connected to the control signal COM on a pin of optical module, can realize having the mode of operation of three kinds of differences.
In order to achieve the above purpose, the utility model adopts the technical proposal that:
a level signal conversion circuit comprises an inverter NOT, an AND gate AND, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2 AND a power supply VCC;
the input end of the inverter NOT is connected with a first level signal a, the output end of the inverter NOT is connected with a first end of a second transistor Q2, one input end of the AND gate AND is connected with a second level signal B, the other input end of the AND gate AND is connected with the output end of the inverter NOT, AND the output end of the AND gate AND is connected with a first end of the first transistor Q1;
the first resistor R1 and the second resistor R2 are connected in series and then connected with the second end of the second transistor Q2, and the other end of the first resistor R1 is connected with a power supply VCC;
the second end of the first transistor Q1 is connected between the first resistor R1 and the second resistor R2, and a connection point of the first resistor R1 and the second resistor R2 is taken as a control signal COM output.
On the basis of the technical scheme, the resistance values of the first resistor R1 and the second resistor R2 are the same.
On the basis of the above technical solution, the first transistor Q1 is an NMOS transistor.
On the basis of the above technical solution, the second transistor Q2 is an NMOS transistor.
On the basis of the above technical solution, an output end of the inverter NOT is connected to a gate of a second transistor Q2, an output end of the AND gate AND is connected to a gate of the first transistor Q1, the first resistor R1 AND the second resistor R2 are connected in series AND then connected to a drain of the second transistor Q2, AND a drain of the first transistor Q1 is connected between the first resistor R1 AND the second resistor R2.
On the basis of the technical scheme, the power supply VCC is 3.3V.
On the basis of the technical scheme, the resistance values of the first resistor R1 and the second resistor R2 are both 150 omega.
The utility model also provides a PON chip of installing above-mentioned level signal converting circuit:
the inverter NOT, the AND gate AND, the first transistor Q1 AND the second transistor Q2 are arranged inside the PON chip, AND the power supply VCC, the first resistor R1 AND the second resistor R2 are arranged outside the PON chip;
the drain of the first transistor Q1 is connected with one output pin J1 of the PON chip, and the drain of the second transistor Q2 is connected with the other output pin J2 of the PON chip;
the two ends of the second resistor R2 are respectively connected to the output pin J1 and the output pin J2, the output pin J1 is connected to a power supply VCC through the first resistor R1, and a signal of the output pin J1 is taken as an output control signal COM.
On the basis of the technical scheme, the resistance values of the first resistor R1 and the second resistor R2 are the same.
The utility model also provides an optical module of installing level signal conversion circuit, phase inverter NOT, AND gate AND, first transistor Q1, second transistor Q2, first resistance R1, second resistance R2 all locate inside the optical module;
the drain of the first transistor Q1 is connected to a pin J0 of the optical module, and the drain of the second transistor Q2 is connected to a pin J0 of the optical module after passing through a second resistor R2.
Compared with the prior art, the utility model has the advantages of:
(1) the utility model discloses a level signal conversion circuit can be exported two level signal conversion for a control signal, be about to first level signal A and second level signal B and convert into a control signal COM, thereby realize through the state that changes first level signal A and second level signal B, can obtain the control signal COM of three kinds of differences, when being applied to the optical module with this level signal conversion circuit, only need be connected to the control signal COM on the pin of optical module, can realize there being three kinds of different mode.
(2) The utility model discloses in install above-mentioned level signal converting circuit's PON chip, can be a control signal with two level signal conversion exports, be about to first level signal A and second level signal B convert into a control signal COM, thereby realize through the state that changes first level signal A and second level signal B, can obtain the control signal COM of three kinds of differences, when being applied to the optical module with this level signal converting circuit, only need be connected to control signal COM on a pin of optical module, can realize there being three kinds of different mode.
(3) The utility model discloses in install above-mentioned level signal conversion circuit's optical module, after a pin of optical module received a control signal COM, this control signal correspondence has 3 kinds of states, the optical module is according to the control signal of this pin, can have three kinds of different voltages, through this reverse level signal conversion circuit, then can convert the control signal of this pin into two height level signal, be first level signal A and second level signal B respectively, the realization obtains two height level signal according to the control signal of a pin, thereby make and need not to change the optical module pin, also can reach the purpose of expanding the pin, and the pin encapsulation of optical module and PON chip still is the standard component, therefore, the commonality is strong, and application scope is wide.
Drawings
Fig. 1 is a schematic diagram of a level signal conversion circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a PON chip with a level signal conversion circuit installed in an embodiment of the present invention;
fig. 3 is a schematic diagram of an optical module equipped with a level signal conversion circuit in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Referring to fig. 1, an embodiment of the present invention provides a level signal conversion circuit, which includes an inverter NOT, an AND gate AND, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, AND a power source VCC.
The input end of the inverter NOT is connected with a first level signal a, the output end of the inverter NOT is connected with a first end of a second transistor Q2, one input end of the AND gate AND is connected with a second level signal B, the other input end of the AND gate AND is connected with the output end of the inverter NOT, AND the output end of the AND gate AND is connected with a first end of the first transistor Q1;
the first resistor R1 and the second resistor R2 are connected in series and then connected with the second end of the second transistor Q2, and the other end of the first resistor R1 is connected with a power supply VCC;
the second end of the first transistor Q1 is connected between the first resistor R1 and the second resistor R2, and a connection point of the first resistor R1 and the second resistor R2 is taken as a control signal COM output.
Preferably, the first resistor R1 and the second resistor R2 have the same resistance. In the embodiment of the present invention, the resistance values of the first resistor R1 and the second resistor R2 are both 150 Ω. When the voltage of the control signal COM needs to be calculated, the voltage is obtained by dividing the voltage through the first resistor R1 and the second resistor R2, and when the resistances of the first resistor R1 and the second resistor R2 are the same, the voltage of the control signal COM is just half of the voltage of the power supply VCC, so that the calculation is more convenient.
In practical applications, the resistances of the first resistor R1 and the second resistor R2 may be different, and the voltage division may be performed according to a ratio of the two resistors.
Furthermore, the first transistor Q1 is an NMOS transistor. The second transistor Q2 is an NMOS transistor. Because field effect transistor performance is better, uses comparatively extensively, in the embodiment of the utility model provides an embodiment, choose for use first transistor Q1 and second transistor Q2 to be the design of NMOS pipe for circuit structure performance is better.
When the first transistor Q1 AND the second transistor Q2 are both NMOS transistors, the output terminal of the inverter NOT is connected to the gate of the second transistor Q2, the output terminal of the AND gate AND is connected to the gate of the first transistor Q1, the drain of the first transistor Q1 is connected between the first resistor R1 AND the second resistor R2, the first resistor R1 AND the second resistor R2 are connected in series AND then connected to the drain of the second transistor Q2, AND the sources of the first transistor Q1 AND the second transistor Q2 are both grounded.
In the embodiment of the present invention, the power VCC is the high level signal 3.3V.
The utility model discloses well level signal conversion circuit's theory of operation does:
when the first level signal a is at a low level 0 AND the second level signal B is at a low level 0, the first level signal a passes through an inverter NOT AND is sent to an AND gate AND together with the second level signal B, the output of the AND gate AND is at the low level 0, the first transistor Q1 is NOT conducted, the first level signal a passes through NOT AND is sent to the second transistor Q2, the second transistor Q2 is conducted, AND the level of the control signal COM is generated by dividing the voltage of R1 AND R2 AND is at a Middle level 1.65V;
when the first level signal a is at a Low level 0 AND the second level signal B is at a high level 1, the first level signal a passes through the inverter NOT AND is sent to the AND gate AND together with the second level signal B, the AND gate AND outputs a high level 1, the first transistor Q1 is turned on, the first level signal a passes through the inverter NOT AND is sent to the second transistor Q2, the second transistor Q2 is turned on, but the second transistor R2 AND the second transistor Q2 are bypassed due to the turn-on of the first transistor Q1, AND the level of the control signal COM is at a Low level 0V;
when the first level signal a is at the high level 1, the first level signal a passes through the inverter NOT AND is sent to the AND gate AND together with the second level signal B, AND the output of the AND gate AND is at the low level 0 no matter whether the second level signal B is at the high level 1 or the low level 0, the first transistor Q1 is NOT turned on, the first level signal a passes through the inverter NOT AND is sent to the second transistor Q2, the second transistor Q2 is NOT turned on, the second resistor R2 is opened, AND the level of the control signal COM is at the high level 3.3V.
The embodiment of the utility model provides an in level signal converting circuit can be exported two level signal conversion for a control signal, be about to first level signal A and second level signal B convert into a control signal COM, thereby realize through the state that changes first level signal A and second level signal B, can obtain the control signal COM of three kinds of differences, when being applied to the optical module with this level signal converting circuit, only need be connected to the control signal COM on a pin of optical module, can realize there being three kinds of different mode.
Referring to fig. 2, an embodiment of the present invention provides a PON chip having the above level signal conversion circuit installed therein, wherein the phase inverter NOT, the AND gate AND, the first transistor Q1 AND the second transistor Q2 are disposed inside the PON chip, AND the power VCC, the first resistor R1 AND the second resistor R2 are disposed outside the PON chip.
A second terminal of the first transistor Q1 is connected to one output pin J1 of the PON chip, and a second terminal of the second transistor Q2 is connected to the other output pin J2 of the PON chip;
the two ends of the second resistor R2 are respectively connected to the output pin J1 and the output pin J2, the output pin J1 is connected to a power supply VCC through the first resistor R1, and a signal of the output pin J1 is taken as an output control signal COM.
Preferably, the first resistor R1 and the second resistor R2 have the same resistance. In the embodiment of the present invention, the resistance values of the first resistor R1 and the second resistor R2 are both 150 Ω. When the voltage of the control signal COM needs to be calculated, the voltage is obtained by dividing the voltage through the first resistor R1 and the second resistor R2, and when the resistances of the first resistor R1 and the second resistor R2 are the same, the voltage of the control signal COM is just half of the voltage of the power supply VCC, so that the calculation is more convenient.
In the embodiment of the present invention, the first transistor Q1 and the second transistor Q2 are NMOS transistors. The drain of the first transistor Q1 is connected to one output pin J1 of the PON chip, and the drain of the second transistor Q2 is connected to the other output pin J2 of the PON chip.
Generally, pins of a PON chip and pins of an optical module are connected one to one, a pin J1 and a pin J2 of the PON chip are respectively and correspondingly connected to two pins of the optical module, a first level signal a is directly connected to the pin J2, a second level signal B is directly connected to the pin J1, signals input to the two pins of the optical module respectively correspond to the first level signal a and the second level signal B, and the first level signal a and the second level signal B are both high level 1 or low level 0, it can be seen that only two control signals output from each pin of the PON chip are respectively high level 1 or low level 0, and only two control signals input to the optical module are respectively high level 1 or low level 0.
The utility model discloses in install above-mentioned level signal converting circuit's PON chip, can be a control signal with two level signal conversion exports, be about to first level signal A and second level signal B convert into a control signal COM, thereby realize through the state that changes first level signal A and second level signal B, can obtain the control signal COM of three kinds of differences, when being applied to the optical module with this level signal converting circuit, only need be connected to control signal COM on a pin of optical module, can realize there being three kinds of different mode.
Referring to fig. 3, in the optical module of the present invention, in which the level signal conversion circuit is installed, the inverter NOT, the AND gate AND, the first transistor Q1, the second transistor Q2, the first resistor R1, AND the second resistor R2 are all disposed inside the optical module;
the drain of the first transistor Q1 is connected to a pin J0 of the optical module, and the drain of the second transistor Q2 is connected to a pin J0 of the optical module after passing through a second resistor R2.
The utility model discloses in install above-mentioned level signal conversion circuit's optical module, after a pin of optical module received a control signal COM, this control signal correspondence has 3 kinds of states, be the voltage 3.3V of power VCC respectively, 0V, 1.65V, the optical module is according to the control signal of this pin, can have the voltage of three kinds of differences, through this reverse level signal conversion circuit, then can convert the control signal of this pin into two height level signals, be first level signal A and second level signal B respectively, the realization obtains two height level signals according to the control signal of a pin, thereby make and need not to change the optical module pin, also can reach the purpose that expands the pin, and the pin encapsulation of optical module and PON chip still is the standard component, therefore, the commonality is strong, and wide application scope.
The present invention is not limited to the above embodiments, and for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered to be within the protection scope of the present invention. Those not described in detail in this specification are within the skill of the art.
Claims (9)
1. A level signal conversion circuit is characterized by comprising an inverter NOT, an AND gate AND, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2 AND a power supply VCC;
the input end of the inverter NOT is connected with a first level signal a, the output end of the inverter NOT is connected with a first end of a second transistor Q2, one input end of the AND gate AND is connected with a second level signal B, the other input end of the AND gate AND is connected with the output end of the inverter NOT, AND the output end of the AND gate AND is connected with a first end of the first transistor Q1;
the first resistor R1 and the second resistor R2 are connected in series and then connected with the second end of the second transistor Q2, and the other end of the first resistor R1 is connected with a power supply VCC;
the second end of the first transistor Q1 is connected between the first resistor R1 and the second resistor R2, and a connection point of the first resistor R1 and the second resistor R2 is taken as a control signal COM output.
2. The level signal conversion circuit of claim 1, wherein: the first resistor R1 and the second resistor R2 have the same resistance.
3. The level signal conversion circuit of claim 1, wherein: the first transistor Q1 is an NMOS transistor.
4. A level signal conversion circuit as claimed in claim 3, wherein: the second transistor Q2 is an NMOS transistor.
5. The level signal conversion circuit of claim 4, wherein: the output end of the inverter NOT is connected with the gate of a second transistor Q2, the output end of the AND gate AND is connected with the gate of the first transistor Q1, the first resistor R1 AND the second resistor R2 are connected in series AND then connected with the drain of the second transistor Q2, AND the drain of the first transistor Q1 is connected between the first resistor R1 AND the second resistor R2.
6. The level signal conversion circuit of claim 1, wherein: the power supply VCC is 3.3V.
7. The level signal conversion circuit of claim 2, wherein: the resistance values of the first resistor R1 and the second resistor R2 are both 150 omega.
8. A PON chip mounted with the level signal conversion circuit according to any one of claims 1 to 7, wherein:
the inverter NOT, the AND gate AND, the first transistor Q1 AND the second transistor Q2 are arranged inside the PON chip, AND the power supply VCC, the first resistor R1 AND the second resistor R2 are arranged outside the PON chip;
the drain of the first transistor Q1 is connected with one output pin J1 of the PON chip, and the drain of the second transistor Q2 is connected with the other output pin J2 of the PON chip;
the two ends of the second resistor R2 are respectively connected to the output pin J1 and the output pin J2, the output pin J1 is connected to a power supply VCC through the first resistor R1, and a signal of the output pin J1 is taken as an output control signal COM.
9. An optical module mounted with the level signal conversion circuit according to any one of claims 1 to 7, characterized in that:
the inverter NOT, the AND gate AND, the first transistor Q1, the second transistor Q2, the first resistor R1 AND the second resistor R2 are all arranged inside the optical module;
the drain of the first transistor Q1 is connected to a pin J0 of the optical module, and the drain of the second transistor Q2 is connected to a pin J0 of the optical module after passing through a second resistor R2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921052233.0U CN210469265U (en) | 2019-07-05 | 2019-07-05 | Level signal conversion circuit, PON chip and optical module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921052233.0U CN210469265U (en) | 2019-07-05 | 2019-07-05 | Level signal conversion circuit, PON chip and optical module |
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| CN210469265U true CN210469265U (en) | 2020-05-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111698582A (en) * | 2020-05-20 | 2020-09-22 | 烽火通信科技股份有限公司 | COMBO optical module and multimode PON system |
-
2019
- 2019-07-05 CN CN201921052233.0U patent/CN210469265U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111698582A (en) * | 2020-05-20 | 2020-09-22 | 烽火通信科技股份有限公司 | COMBO optical module and multimode PON system |
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