CN110149109B

CN110149109B - Isolated driving signal transmission circuit

Info

Publication number: CN110149109B
Application number: CN201910406932.9A
Authority: CN
Inventors: 秦海怡; 王燕晖
Original assignee: Xiamen Xindamao Microelectronics Co ltd
Current assignee: Xiamen Xindamao Microelectronics Co ltd
Priority date: 2019-05-16
Filing date: 2019-05-16
Publication date: 2024-08-20
Anticipated expiration: 2039-05-16
Also published as: CN110149109A

Abstract

The invention provides an isolated drive signal transmission circuit, which comprises: the input signal receiving module is coupled between a first power supply and a first ground end and is used for receiving an input signal, and outputting a differential signal after performing a dual-carrier modulation processing on the input signal; the high-voltage capacitor is used as an isolation medium and coupled with the input signal receiving module to receive the differential signal; and an output signal providing module coupled between a second power supply and a second ground terminal and coupled to the high-voltage capacitor, for receiving the differential signal through the high-voltage capacitor and providing an output signal after performing a dual-carrier demodulation process on the differential signal.

Description

Isolated driving signal transmission circuit

Technical Field

The present invention relates to an isolated driving circuit, and more particularly to an isolated driving signal transmission circuit applied in a gate driving device.

Background

An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is one type of semiconductor device, and is mainly used for driving control of electric motors such as electric vehicles, electric locomotives, and air conditioners. In a closed loop control system, the main control chip of the system generates an IGBT drive signal corresponding to the output voltage (current) signal, and the IGBT drive signal is transmitted to the IGBT device through the IGBT gate driver. Therefore, the IGBT gate driver is an electronic chip for transmitting driving signals to the IGBT device

The commercial IGBT gate driver chip contains isolation medium for isolating between a signal receiving circuit and an output circuit inside the IGBT gate driver chip. Currently, commonly used isolation media include: opto-electronic coupling components, NVE magnetic switches, GMR giant magneto resistance, etc., which may be in the form of individual signal Isolators (ICs). An optocoupler is a group of devices that transmit electrical signals using light as a medium, and functions to isolate between an input circuit and an output circuit at ordinary times, and to transmit electrical signals through the isolation layer when needed. Optocoupler devices are widely used in electrical isolation, level shifting, driving circuits, and industrial communications, but because of parasitic input-output capacitance problems, optocouplers have weak ability to resist Common mode transient suppression (CMTI) and are well suited for use in a wide variety of applications; in addition, speed limitation, high power consumption, and easy aging of components are major problems.

Optocouplers are also used in IGBT gate drivers for driving motors. However, the conventional IGBT gate driver including the optocoupler has a potential drawback in that the high voltage side thereof may be required to provide a timing adjustment circuit. Another problem is that during the switching process of the IGBT gate driver on the low voltage side, the drive circuit on the high voltage side may be damaged due to the burr voltage generated by the parasitic inductance of the circuit on the low voltage side.

On the other hand, chinese patent publication No. CN101640526a discloses an IGBT driving circuit with an internal isolation power supply, which does not use an optical coupler as an isolation medium; instead, a pulse transformer is used as an isolation medium of different types and is coupled between a pulse modulation circuit and a pulse demodulation circuit to provide signal isolation. However, it is still difficult to provide short delay and good CMTI performance using pulse transformers as isolation media.

Accordingly, there is a need in the art for a novel isolated drive signal transmission circuit.

Disclosure of Invention

An object of the present invention is to provide an isolated driving signal transmission circuit which has excellent common mode transient suppression (CMTI) capability and is capable of transmitting high frequency signals while isolating low frequency noise.

Another objective of the present invention is to provide an isolated driving signal transmission circuit, in which the current mirror, bandgap voltage, resistor, capacitor and other circuit components used have consistent process conditions, and the key circuit design parameters are determined by proportional values rather than absolute values, so that the chip comprising the isolated driving signal transmission circuit of the present invention can provide consistent performance.

In order to achieve the above object, the present invention provides an isolated driving signal transmission circuit, comprising:

The input signal receiving module is coupled between a first power supply and a first ground end and is used for receiving an input signal, and outputting a differential signal after performing a dual-carrier modulation processing on the input signal;

An isolation medium, which is a high-voltage capacitor and is coupled to the input signal receiving module to receive the differential signal; and

The output signal providing module is coupled between a second power supply and a second ground terminal, and is coupled with the isolation medium at the same time, and is used for receiving the differential signal through the isolation medium and providing an output signal after performing a dual carrier demodulation processing on the differential signal.

In one embodiment, the input signal receiving module includes:

a carrier signal generating unit for generating a first carrier signal and a second carrier signal based on a first threshold voltage and a second threshold voltage;

The multiplexer is coupled with the input signal and the carrier signal generating unit to perform the dual-carrier modulation processing on the input signal so as to output a first modulation signal or a second modulation signal, wherein the first modulation signal is generated in the following way: the multiplexer outputs the first carrier signal when the input signal is at a high level, and outputs the second carrier signal when the input signal is at a low level, and the second modulation signal is generated in the following manner: the multiplexer outputs the second carrier signal when the input signal is at a high level and outputs the first carrier signal when the input signal is at a low level; and

The differential signal output unit is coupled to the multiplexer and provided with an input end for receiving the first modulation signal or the second modulation signal and two output ends for outputting the differential signal.

In one embodiment, the carrier signal generating unit includes:

A first current source;

A first P-type MOS transistor having a source terminal coupled to the first current source;

A first N-type MOS transistor having a gate coupled to the gate of the first P-type MOS transistor to form a first common node and a drain coupled to the drain of the first P-type MOS transistor to form a second common node;

a second current source coupled to the source terminal of the first N-type MOS transistor;

a first delay capacitor, two ends of which are respectively coupled to the second common node and the first ground;

the positive input end and the negative input end of the first comparator are respectively coupled with the first threshold voltage and the second common joint;

a second comparator having a negative input terminal and a positive input terminal coupled to the second threshold voltage and the second common node, respectively;

A first inverse OR gate, an input end of which is coupled with the output end of the first comparator;

A second inverse OR gate, one input end of which is coupled with the output end of the second comparator, the other input end of which is coupled with the output end of the first inverse OR gate to form a third common joint, and the output end of which is coupled with the other input end of the first inverse OR gate; wherein the third common node is coupled to the first common node;

A D-type flip-flop having a clock signal receiving end, a data output end and an inverted data output end; the clock signal receiving end is coupled to the third common node, and the data receiving end is coupled to the inverted data output end; and

The frequency divider is provided with a signal receiving end and a signal output end, wherein the signal receiving end is coupled with the data output end;

the data output end of the D-type flip-flop is used for outputting the first carrier signal with a first frequency, and the signal output end of the frequency divider is used for outputting the second carrier signal with a second frequency.

In a possible embodiment, the carrier signal generating unit comprises:

A first current source;

An inverter having an input terminal, an output terminal and a bias terminal, wherein the bias terminal is coupled to the first current source;

The two ends of the first delay capacitor are respectively coupled to the output end and the first ground end of the inverter;

the positive input end and the negative input end of the first comparator are respectively coupled with the first threshold voltage and the output end of the inverter;

A second comparator having a negative input terminal and a positive input terminal coupled to the second threshold voltage and the output terminal of the inverter, respectively;

a first inverse OR gate, an input end of which is coupled with the output end of the first comparator, and an output end of which is coupled with the output end of the inverter;

A second inverse OR gate, one input end of which is coupled with the output end of the second comparator, the other input end of which is coupled with the output end of the first inverse OR gate, and the output end of which is coupled with the other input end of the first inverse OR gate and the output end of the inverter;

In one embodiment, the output signal providing module includes:

The filtering unit is used for receiving the differential signal through the isolation medium and performing high-pass filtering on the differential signal so as to output a high-frequency modulation signal;

The frequency-voltage conversion unit is coupled with the filtering unit and used for receiving the high-frequency modulation signal and converting the high-frequency modulation signal into a voltage signal; and

A comparator unit coupled to the frequency-voltage conversion unit and a reference voltage for outputting a demodulation signal; wherein the demodulated signal comprises: the comparator unit outputs a high-level signal when the voltage signal is larger than the reference voltage and outputs a low-level signal when the voltage signal is smaller than the reference voltage.

In one embodiment, the filtering unit includes:

a first resistor having one end coupled to the isolation medium and the other end coupled to the second ground;

a second resistor having one end coupled to the isolation medium and the other end coupled to the second ground; wherein the first resistor, the second resistor and the isolation medium form a first-stage high-pass filter with two input ends and two output ends;

a first capacitor having one end coupled to the first resistor;

A third resistor having one end coupled to the other end of the first capacitor and the other end coupled to the second ground;

A second capacitor having one end coupled to the second resistor;

A fourth resistor having one end coupled to the other end of the second capacitor and the other end coupled to the second ground; wherein the first capacitor, the third resistor, the second capacitor and the fourth resistor form a second-stage high-pass filter with two input ends and two output ends; and

And the two input ends of the third comparator are respectively coupled to the two output ends of the second-stage high-pass filter.

In one embodiment, the frequency-to-voltage conversion unit includes:

a third current source;

a second P-type MOS transistor having a source terminal coupled to the third current source;

A second N-type MOS transistor having a gate coupled to the gate of the second P-type MOS transistor to form a fourth common node and a drain coupled to the drain of the second P-type MOS transistor to form a fifth common node;

a second delay capacitor, two ends of which are respectively coupled to the fifth common node and the second ground;

the input end and the output end of the first inverter are respectively coupled with the output end of the third comparator and the fourth common contact;

A fourth comparator having a positive input terminal and a negative input terminal coupled to a base reference voltage and the second common node, respectively;

a first inverse AND logic gate, one input end of which is coupled with the output end of the fourth comparator, and the other input end of which is coupled with the output end of the third comparator;

a third P-type MOS transistor having a gate terminal coupled to the output terminal of the first inverse and logic gate, a source terminal coupled to a fourth current source, and a drain terminal coupled to a fifth resistor; and

And the two ends of the output capacitor are respectively coupled with the drain terminal of the third P-type MOS transistor and the second ground terminal.

In an embodiment, the comparator unit includes a comparator, wherein a positive input terminal and a negative input terminal of the comparator are respectively coupled to the output capacitor and the reference voltage, and an output terminal of the comparator is used for outputting the demodulation signal.

In a possible embodiment, the frequency-to-voltage conversion unit further comprises:

A fifth current source;

a fourth P-type MOS transistor having a source terminal coupled to the fifth current source;

a third N-type MOS transistor having a gate coupled to the gate of the fourth P-type MOS transistor to form a sixth common node and a drain coupled to the drain of the fourth P-type MOS transistor to form a seventh common node;

A third delay capacitor, two ends of which are respectively coupled to the seventh common node and the second ground terminal;

The input end and the output end of the second inverter are respectively coupled with the output end of the first inverter and the sixth common contact;

A fifth comparator having a positive input terminal and a negative input terminal coupled to the base reference voltage and the seventh common node, respectively;

A second inverse AND logic gate, one input end of which is coupled with the output end of the fifth comparator, and the other input end of which is coupled with the output end of the first inverter; and

A fourth P-type MOS transistor having a gate terminal coupled to the output terminal of the second NAND gate, a source terminal coupled to the fourth current source, and a drain terminal coupled to the output capacitor.

In addition, the invention further provides a gate driving device, which is provided with the isolated driving signal transmission circuit.

Drawings

For a further disclosure of the present invention, reference is first made to the accompanying drawings, in which:

FIG. 1 is a circuit block diagram of an isolated drive signal transmission circuit according to an embodiment of the present invention;

FIG. 2 is a circuit topology diagram of an embodiment of a carrier signal generation unit of the isolated drive signal transmission circuit of FIG. 1 according to the present invention;

FIG. 3 is a circuit topology diagram of another embodiment of a carrier signal generation unit of the isolated drive signal transmission circuit of FIG. 1 according to the present invention;

FIG. 4 is a waveform diagram illustrating operation of the isolated driving signal transmission circuit of FIG. 1 according to the present invention;

FIG. 5 is a circuit topology diagram of an embodiment of a filtering unit of the isolated driving signal transmission circuit of FIG.1 according to the present invention;

FIG. 6 is a circuit topology diagram of an embodiment of a frequency-to-voltage conversion unit of the isolated drive signal transmission circuit of FIG. 1 according to the present invention;

FIG. 7 is a diagram illustrating another waveform of the isolated driving signal transmission circuit of FIG. 1 according to the present invention;

And

FIG. 8 is a circuit topology diagram of another embodiment of a frequency-to-voltage conversion unit of the isolated drive signal transmission circuit of FIG. 1.

Detailed Description

The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.

As shown in fig. 1, a circuit block diagram of an embodiment of an isolated driving signal transmission circuit of the present invention is provided, wherein the isolated driving signal transmission circuit of the present invention can be applied to a gate driving device to receive an input signal, such as an IGBT driving signal, transmitted from a main control chip. As shown in fig. 1, an isolated driving signal transmission circuit 1 performs dual carrier modulation processing on an input signal by using an internal input signal receiving module 11 to generate a differential signal, and then transmits the differential signal to an output signal providing module 13 by using an internal isolating medium 12; finally, the output signal providing module 13 demodulates the differential signal and provides an output signal to at least one IGBT device for controlling a gate operation.

According to the present invention, the input signal receiving module 11 is coupled between a first power supply VDD1 and a first ground GND1, and is configured to receive an input signal, perform a dual carrier modulation on the input signal, and output a differential signal. As can be seen from fig. 1, the input signal receiving module 11 includes; a carrier signal generating unit 111, which is a group of oscillators whose frequency is determined by voltage; a Multiplexer (Multiplexer) 112; and a differential signal output unit 113. Referring to fig. 2, a circuit topology diagram of an embodiment of the carrier signal generation unit 111 is shown. As shown in fig. 2, the carrier signal generating unit 111 generates a first carrier signal (a) and a second carrier signal (B) based on a first threshold voltage VTH1 and a second threshold voltage VTH2, and includes: a first current source 1111, a first P-type MOS transistor 1112, a first N-type MOS transistor 1113, a second current source 1114, a first delay capacitor 1110, a first comparator 1115, a second comparator 1116, a first nor gate 1117, a second nor gate 1118, a D-type flip-flop 1119, and a divider 111A.

It should be appreciated by an electronic engineer familiar with the high frequency signal transmission circuit that the first current source 1111, the first P-type MOS Transistor 1112, the first N-type MOS Transistor 1113, and the second current source 1114 are combined to form a Transistor-Transistor logic buffer (TTL buffer) which forms a delay circuit together with the first delay capacitor 1110. More specifically, the source terminal of the first P-type MOS transistor 1112 is coupled to the first current source 1111. In addition, the gate terminal of the first N-type MOS transistor 1113 is coupled to the gate terminal of the first P-type MOS transistor 1112 to form a first common node 1CP, the drain terminal of the first N-type MOS transistor 1113 is coupled to the drain terminal of the first P-type MOS transistor 1112 to form a second common node 2CP, and the source terminal of the first N-type MOS transistor 1113 is coupled to the second current source 1114. On the other hand, two ends of the first delay capacitor 1110 are respectively coupled to the second common node 2CP and the first ground GND1, and the positive input terminal and the negative input terminal of the first comparator 1115 are respectively coupled to the first threshold voltage VTH1 and the second common node 2CP

As described above, the negative input terminal and the positive input terminal of the second comparator 1116 are respectively coupled to the second threshold voltage VTH2 and the second common node 2CP, and the first inverse or gate 1117 is coupled to the output terminal of the first comparator 1115 via an input terminal. It is noted that the second nor gate 1118 has an input coupled to the output of the second comparator 1116, another input coupled to the output of the first nor gate 1117 to form a third common node 3CP, and an output coupled to the other input of the first nor gate 1117. Furthermore, as can be seen from fig. 2, the third common node 3CP is coupled to the first common node 1CP. Furthermore, the D-type flip-flop 1119 has a clock signal receiving terminal, a data output terminal and an inverted data output terminal; the clock signal receiving terminal is coupled to the third common node 3CP, and the data receiving terminal is coupled to receive the inverted data output terminal. Further, the frequency divider 111A has a signal receiving end and a signal output end, wherein the signal receiving end is coupled to the data output end.

According to the present invention, the first threshold voltage VTH1 is set to be high, the second threshold voltage VTH2 is set to be low, and the first delay capacitor 1110 is a charging capacitor, and the charging time t1 and the discharging time t2 can be calculated by the following equations (1) and (2).

t1＝Cdelay1*(VTH2-VTH1)/Idealy1………(1)

t2＝Cdelay1*(VTH2-VTH1)/Idealy2………(2)

In the above formulas (1) and (2), idealy is a constant current provided by the first current source 1111, idealy2 is a constant current provided by the second current source 1114, and Cdelay1 is a capacitance value of the first delay capacitor 1110. It is additionally noted that the charging process is to charge a voltage from VTH2 to VTH1, and the discharging process is to discharge a voltage from VTH1 to VTH2. Further, when Idealy1 = Idealy2, the following expression (3) can be obtained.

Fcarrier＝Idelay1/(4*Cdelay1*(VTH2-VTH1))………(3)

In more detail, idelay is a constant current provided by the first current source 1111, and the first current source 1111 is a current mirror that generates Idelay1 based on the first bandgap reference voltage VBG1 and the load Resistor (RL) provided by a set of bandgap reference voltage generating circuits, while VTH1 and VTH2 are obtained by dividing the first bandgap reference voltage VBG 1; thus, the foregoing several conditions can be characterized as the following formulas (4), (5) and (6).

VTH1＝K1*VBG1………(4)

VTH2＝K2*VBG1………(5)

Idelay1＝Kx*VBG1/RL………(6)

Wherein, K1 and K2 are partial pressure coefficients, and Kx is the copy multiple of the current mirror. Then, the following formula (7) can be obtained by substituting the formulas (4), (5) and (6) into the above formula (3).

Fcarrier1＝Kx/(4*Cdelay1*(K1-K2)*RL)………(7)

Specifically, fcarrier is the frequency of a first carrier signal (a) outputted through the D-type flip-flop 1119, and the first carrier signal (a) is also transmitted to the divider 111A at the subsequent stage. As shown in fig. 2, the frequency divider 111A includes N D-type flip-flops, and the N D-type flip-flops are serially connected in a pre-stage and a post-stage. The first carrier signal (a) is converted into a second carrier signal (B) by the frequency divider 111A, and the frequency of the second carrier signal (B) can be obtained by the following equation (8).

Fcarrier2＝Kx/(4*Cdelay1*(K1-K2)*RL*2N)………(8)

Referring to fig. 1, and also referring to fig. 3, a circuit topology diagram of another embodiment of the carrier signal generation unit 111 is shown. As can be seen from comparing fig. 3 and fig. 2, IN a possible embodiment, an inverter 11IN may be used instead of the first P-type MOS transistor 1112 and the first N-type MOS transistor 1113 shown IN fig. 2. IN this case, the second current source 1114 may be omitted since only the first current source 1111 is required to provide a bias current to the inverter 11 IN.

As shown IN fig. 3, the inverter 11IN has an input terminal, an output terminal, and a bias terminal, and the bias terminal is coupled to the first current source 1111. And, two ends of the first delay capacitor 1110 are coupled to the output end of the inverter 11IN and the first ground GND1, respectively. On the other hand, the positive input terminal and the negative input terminal of the first comparator 1115 are respectively coupled to the first threshold voltage VTH1 and the output terminal of the inverter 11IN, and the negative input terminal and the positive input terminal of the second comparator 1116 are respectively coupled to the second threshold voltage VTH2 and the output terminal of the inverter 11 IN. Furthermore, an input terminal of the first nor gate 1117 is coupled to the output terminal of the first comparator 1115, and an output terminal thereof is coupled to the output terminal of the inverter 11 IN. It is noted that one input of the second nor gate 1118 is coupled to the output of the second comparator 1116, and the other input is coupled to the output of the first nor gate 1117. And, the output of the second nor gate 1118 is coupled to both the other input of the first nor gate 1117 and the output of the inverter 11 IN.

For the carrier signal generating unit 111 having the circuit topology as shown in fig. 3, the discharging time t2 of the first delay capacitor 1110 can be ignored, so that the frequencies of the first carrier signal (a) and the second carrier signal (B) outputted by the same can be obtained by the following equations (9) and (10).

Fcarrier1＝Kx/(2*Cdelay1*(K1-K2)*RL)………(9)

Fcarrier2＝Kx/(2*Cdelay1*(K1-K2)*RL*2N)………(10)

Please refer to fig. 1, and also refer to an operation waveform diagram shown in fig. 4. According to the present invention, the input signal receiving module 11 coupled between the first power supply VDD1 and the first ground GND1 is configured to receive an input signal, and make the carrier signal generating unit 111 therein generate a first carrier signal (a) and a second carrier signal (B) based on the first threshold voltage VTH1 and the second threshold voltage VTH 2; then, the multiplexer 112 coupled to the input signal and the carrier signal generating unit 111 outputs a first modulation signal (I) or a second modulation signal (II) to the differential signal output unit 113 correspondingly. In particular, as can be seen from the above formulas (7), (8) and fig. 4, the first modulation signal (I) comprises: the first carrier signal (a) selectively output by the multiplexer 112 when the input signal is at a high level and the second carrier signal (B) selectively output by the multiplexer 112 when the input signal is at a low level. On the other hand, the second modulation signal (II) comprises: the second carrier signal (B) selectively output by the multiplexer 112 when the input signal is at a high level and the first carrier signal (a) selectively output by the multiplexer 112 when the input signal is at a low level. Of course, after receiving the first modulation signal (I) or the second modulation signal (II) at one input terminal thereof, the differential signal output unit 113 outputs a differential signal to the isolation medium 12 of the subsequent stage at two output terminals thereof.

In particular, the present invention adopts a high-voltage capacitor as the isolation medium 12, and the output signal providing module 13 is composed of a filtering unit 131, a frequency-voltage converting unit 132, and a comparator unit 133. Referring to fig. 5, a circuit topology diagram of an embodiment of the filtering unit 131 is shown, wherein the filtering unit 131 receives the differential signal through the isolation medium 12 to perform a high-pass filtering process on the differential signal, and further outputs a high-frequency modulation signal. As shown in fig. 5, the filtering unit 131 includes: a first resistor 1311, a second resistor 1312, a first capacitor 1313, a third resistor 1315, a second capacitor 1314, a fourth resistor 1316, and a third comparator 1317. As shown in the dashed box in fig. 5, the first resistor 1311, the second resistor 1312 and the isolation medium 12 form a first-stage high-pass filter having two input ends and two output ends, wherein two ends of the first resistor 1311 are coupled to the isolation medium 12 and the second ground GND2, respectively, and two ends of the second resistor 1312 are coupled to the isolation medium 12 and the second ground GND2, respectively; as shown in another dashed box in fig. 5, the first capacitor 1313, the third resistor 1315, the second capacitor 1314 and the fourth resistor 1316 form a second-stage high-pass filter having two input ends and two output ends, wherein the first capacitor 1313 is coupled to the first resistor 1311 at one end, the third resistor 1315 is coupled to the other end of the first capacitor 1313 and the second ground GND2 at two ends, the second capacitor 1314 is coupled to the second resistor 1312 at one end, and the fourth resistor 1316 is coupled to the other end of the second capacitor 1314 and the second ground GND2 at two ends, respectively.

It should be noted that, the voltage of the differential signal input through the isolation medium 12 is generally lower after the high-pass filtering process of the first-stage high-pass filter and the second-stage high-pass filter, so that the two input terminals of the third comparator 1317 are respectively coupled to the two output terminals of the second-stage high-pass filter, so as to raise the voltage (level) of the differential signal to the voltage (level) of the second power supply VDD2 to provide the output signal.

With continued reference to fig. 1, and with reference to fig. 6, a circuit topology diagram of an embodiment of the frequency-to-voltage conversion unit 132 is shown, wherein the frequency-to-voltage conversion unit 132 is coupled to the filtering unit 131 to receive a high-frequency modulation signal outputted by the filtering unit 131 and convert the high-frequency modulation signal into a voltage signal. As shown in fig. 6, the frequency-voltage conversion unit 132 includes: a third current source 1321, a second P-type MOS transistor 1322, a second N-type MOS transistor 1323, a second delay capacitor 1324, a first inverter 1325, a fourth comparator 1326, a first inverting logic gate 1327, a third P-type MOS transistor 1328, a fourth current source 1329, a fifth resistor 132A, and an output capacitor 132B.

It should be appreciated by an electronic engineer familiar with the high frequency signal transmission circuit that the first inverter 1325, the third current source 1321, the second P-type MOS Transistor 1322 and the second N-type MOS Transistor 1323 form a Transistor-Transistor logic buffer (Transistor-Transistor logic buffer, TTL buffer), and the Transistor-Transistor logic buffer and the second delay capacitor 1324 together form a delay circuit. More specifically, the second P-type MOS transistor 1322 is coupled to the third current source 1321 at its source terminal. And, the gate of the second N-type MOS transistor 1323 is coupled to the gate of the second P-type MOS transistor 1322 to form a fourth common node 4CP, and the drain is coupled to the drain of the second P-type MOS transistor 1322 to form a fifth common node 5CP. Furthermore, two ends of the second delay capacitor 1324 are coupled to the fifth common node 5CP and the second ground GND2, respectively, and an input end and an output end of the first inverter 1325 are coupled to the output end of the third comparator 1317 and the fourth common node 4CP, respectively. On the other hand, the positive input terminal and the negative input terminal of the fourth comparator 1326 are respectively coupled to a base reference voltage VREF0 and the fifth common node 5CP, and one input terminal of the first nand gate 1327 is coupled to the output terminal of the fourth comparator 1326, while the other input terminal is coupled to the output terminal of the third comparator 1317. In addition, the gate of the third P-type MOS transistor 1328 is coupled to the output of the first NAND gate 1327, the source is coupled to a fourth current source 1329, and the drain is coupled to a fifth resistor 132A. And, two ends of the output capacitor 132B are respectively coupled to the drain terminal of the third P-type MOS transistor 1328 and the second ground GND2.

As shown in the circuit topology of fig. 6, the frequency-to-voltage conversion unit 132 receives the high frequency modulation signal transmitted from the third comparator 1317 through the first inverter 1325, and outputs the voltage signal to the comparator unit 133 at the subsequent stage through the third P-type MOS transistor 1328 and the output capacitor 132B. In particular, the present invention adopts a comparator 1331 as a demodulation signal generating unit, as shown in fig. 6, whose positive input terminal and negative input terminal are respectively coupled to the output capacitor 132B and a reference voltage VREF. It is easy to understand that, as long as the appropriate reference voltage VREF is selected, the voltage signal corresponding to Fcarrier a is larger than the reference voltage VREF, and the voltage signal corresponding to Fcarrier a is smaller than the reference voltage VREF. So designed, the comparator unit 133 receives the voltage signal transmitted from the frequency-to-voltage conversion unit 132 and then outputs a demodulation signal; wherein the demodulated signal comprises: the comparator unit 133 outputs a high level signal when the voltage signal is greater than the reference voltage VREF and a low level signal when the voltage signal is less than the reference voltage VREF.

Referring to fig. 7, another operational waveform diagram of the isolated driving signal transmission circuit of fig. 1 is shown. According to the design of the present invention, the delay circuit composed of the first inverter 1325, the third current source 1321, the second P-type MOS transistor 1322, the second N-type MOS transistor 1323 and the second delay capacitor 1324 further forms a so-called monostable trigger (one shot) circuit with the fourth comparator 1326. Furthermore, the output signal of the fourth comparator 1326 is a square wave signal, and the generation of the square wave signal is triggered by the rising edge of the input signal. The square wave signal is used to control the on/off state of the third P-type MOS transistor 1328 to determine the fourth current source 1329 to supply the current to the fifth resistor 132A. Therefore, the frequency of the input signal determines the average magnitude of the current flowing through the fifth resistor 132A, i.e. the magnitude of the output voltage of the demodulation signal.

The large dotted box in fig. 6 indicates a circuit unit that generates a one shot signal according to the rising edge of the high frequency modulation signal transmitted from the third comparator 1317 to generate a square wave signal for controlling the on/off of the third P-type MOS transistor 1328. The delay time (Tdelay) of the click signal is determined by Idelay, cdelay, and Vth. Idelay2 is the value of the constant current provided by the third current source 1321, and Cdelay is the capacitance value of the second delay capacitor 1324. On the other hand, vth is a threshold voltage, which is the base reference voltage VREF0 indicated in fig. 6. Therefore, the voltage signal (Vout) output by the frequency-voltage converting unit 132 can be obtained by the following equations (11), (12), (13), and (14).

Tdelay＝Cdelay2*Vth/Idelay2………(11)

Iout＝Ka*Idelay2………(12)

Vout＝Iout*Tdelay*Fcarrier*Rout………(13)

Vout＝Ka*Rout*Cdelay2*Vth*Fcarrier………(14)

Wherein Iout is a constant current value provided by the fourth current source 1329; ka is the current mirror multiple of Iout and Idelay; and Rout is the resistance of the fifth resistor 132A. It is easy to understand that the voltage signal (Vout) output by the frequency-to-voltage conversion unit 132 has a voltage value (level) proportional to the carrier frequency and also proportional to Rout (fifth resistor 132A), cdelay2 (second delay capacitor 1324) and the base reference voltage VREF0 (Vth).

Specifically, when the carrier signal generating unit 111 has the circuit topology shown in fig. 2, the following formula (15) can be obtained by further substituting the above formula (8) into the formula (14).

Vout＝Kx*Ka*Rout*Cdelay2*Vth*1/(4*Cdelay1*(K1-K2)*RL*2N)……… (15)

Since the process conditions of the first delay capacitor 1110 and the second delay capacitor 1324 are the same and the threshold voltage Vth (i.e., the base reference voltage VREF0 shown in fig. 6) can be obtained by dividing the second bandgap reference voltage VBG2 provided by another set of bandgap reference voltage generating circuits, the following equations (16) and (17) can be obtained. Then, the following formula (18) can be obtained by substituting the formula (16) and the formula (17) into the formula (15) at the same time.

Cdelay2/Cdelay1＝K3………(16)

Vth＝K4*VBG2………(17)

Vout＝Kx*Ka*K4**K3*Rout*VBG2*1/(4*(K1-K2)*R1*2N)(18)

Since Rout (i.e., the fifth resistor 132A) is the same as the process condition of the load Resistor (RL), the following expression (19) can be obtained. Then, the following formula (20) can be obtained by substituting formula (19) into formula (18).

Rout＝K5*R1………(19)

Vout＝Kx*Ka*K4**K3*K5*VBG2*/((4*(K1-K2)*2N)……(20)

On the other hand, when the carrier signal generating unit 111 has the circuit topology shown in fig. 3, the following expression (21) can be further derived.

Vout＝Kx*Ka*K4**K3*K5*VBG2*/((2*(K1-K2)*2N)……(21)

Referring to fig. 8, a circuit topology diagram of another embodiment of the frequency-to-voltage conversion unit 132 is shown. As can be easily seen by comparing fig. 6 and fig. 8, the frequency-voltage converting unit 132 shown in fig. 8 further includes: a fifth current source 1321', a fourth P-type MOS transistor 1322', a third N-type MOS transistor 1323', a third delay capacitor 1324', a second inverter 1325', a fifth comparator 1326', a second nand gate 1327', and a fourth P-type MOS transistor 1328'. The fourth P-type MOS transistor 1322 'is coupled to the fifth current source 1321' at its source terminal. And, the gate terminal of the third N-type MOS transistor 1323' is coupled to the gate terminal of the fourth P-type MOS transistor 1322' to form a sixth common node 6CP, and the drain terminal thereof is coupled to the drain terminal of the fourth P-type MOS transistor 1322' to form a seventh common node 7CP.

As described above, the two ends of the third delay capacitor 1324 'are coupled to the seventh common node 7CP and the second ground GND2, respectively, and the input end and the output end of the second inverter 1325' are coupled to the output end of the first inverter 1325 and the sixth common node 6CP, respectively. Furthermore, the positive input terminal and the negative input terminal of the fifth comparator 1326' are respectively coupled to the base reference voltage VREF0 and the seventh common node 7CP, and one input terminal of the second inverse AND logic gate 1327' is coupled to the output terminal of the fifth comparator 1326', and the other input terminal thereof is coupled to the output terminal of the first inverter 1325. On the other hand, the gate terminal of the fourth P-type MOS transistor 1328 'is coupled to the output terminal of the second inverse and logic gate 1327', the source terminal thereof is coupled to the fourth current source 1329, and the drain terminal thereof is coupled to the output capacitor 132B. In particular, the output voltage signal (Vout) of the frequency-to-voltage conversion unit having the circuit topology shown in fig. 8 can be obtained by the following equations (22) and (22').

Vout＝2*Ka*Rout*Cdelay2*Vth*Fcarrier………(22)

Therefore, the above formula (16), formula (17) and formula (19) can be substituted into formula (22) together. Thus, when the carrier signal generating unit 111 has the circuit topology shown in fig. 2 and the frequency-to-voltage converting unit 132 has the circuit topology shown in fig. 8, the following equation (23) can be further derived.

Vout＝Kx*Ka*K4**K3*K5*VBG2*/((2*(K1-K2)*2N)……(23)

On the other hand, when the carrier signal generating unit 111 has the circuit topology shown in fig. 3 and the frequency-voltage converting unit 132 has the circuit topology shown in fig. 8, the following expression (24) can be further derived.

Vout＝Kx*Ka*K4**K3*K5*VBG2*/((K1-K2)*2N)………(23)

As can be seen from the above description, the modulated carrier frequencies are related to Idelay, cdelay, and VBG1, and the voltage (Vout) of the demodulated output signal is related to Rout, cdelay2, VBG2, and carrier frequencies. Therefore, as long as the process conditions of the first delay capacitor 1110 and the second delay capacitor 1324 are the same and the process conditions of Rout (i.e., the fifth resistor 132A) and the load Resistor (RL) are the same when designing the circuit, the voltage (Vout) of the finally demodulated output signal is only related to Ka, K1, K2, K3, K4, K5, and VBG 2. Where Kx is the replica of the current mirror (first current source 1111), ka is the ratio of Iout to Idelay (constant current provided by second current source 1114), K1-K5 are the resistance, capacitance, and division factor, respectively, and VBG2 are the bandgap voltages. Briefly, the isolated drive signal transmission circuit of the present invention can employ consistent process conditions to provide consistent performance from chip to chip.

Thus, the foregoing has fully and clearly described the isolated drive signal transmission circuit of the present invention; moreover, it can be seen from the above that the present invention has the following advantages:

(1) The isolated drive signal transmission circuit has excellent common mode transient rejection (CMTI) resistance and can transmit high-frequency signals under the condition of isolating low-frequency noise.

(2) The circuit components such as the current mirror, the band gap voltage, the resistor, the capacitor and the like used by the isolated driving signal transmission circuit have consistent process conditions, and key circuit design parameters are determined by proportional values rather than absolute values, so that the chip comprising the isolated driving signal transmission circuit can provide consistent performance.

The present invention is disclosed as one of the preferred embodiments, but it is apparent to those skilled in the art that some changes or modifications may be made to the present invention without departing from the scope of the invention.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and the like falling within the spirit and principles of the invention are to be included within the scope of the invention.

Claims

1. An isolated drive signal transmission circuit, comprising:

The output signal providing module is coupled between a second power supply and a second ground end, is coupled with the isolation medium at the same time, and is used for receiving the differential signal through the isolation medium and providing an output signal after carrying out a double-carrier demodulation processing on the differential signal;

the input signal receiving module includes:

A differential signal output unit coupled to the multiplexer and having an input end for receiving the first modulation signal or the second modulation signal and two output ends for outputting the differential signal;

the carrier signal generation unit includes:

A first current source;

2. An isolated drive signal transmission circuit, comprising:

the input signal receiving module includes:

the carrier signal generation unit includes:

A first current source;

3. The isolated drive signal transmission circuit according to claim 1 or 2, wherein the output signal providing module comprises:

4. An isolated drive signal transmission circuit according to claim 3, wherein the filtering unit comprises:

a first capacitor having one end coupled to the first resistor;

A second capacitor having one end coupled to the second resistor;

5. The isolated drive signal transmission circuit of claim 4, wherein the frequency-to-voltage conversion unit comprises:

a third current source;

6. The isolated driving signal transmission circuit of claim 5, wherein the comparator unit comprises a comparator having a positive input terminal and a negative input terminal coupled to the output capacitor and the reference voltage, respectively, and an output terminal for outputting the demodulation signal.

7. The isolated drive signal transmission circuit of claim 5, wherein the frequency to voltage conversion unit further comprises:

A fifth current source;

8. A gate driving device having the isolated driving signal transmission circuit according to any one of claims 1 to 7.