CN210467287U - GOA circuit for narrow frame panel - Google Patents
GOA circuit for narrow frame panel Download PDFInfo
- Publication number
- CN210467287U CN210467287U CN201921766745.3U CN201921766745U CN210467287U CN 210467287 U CN210467287 U CN 210467287U CN 201921766745 U CN201921766745 U CN 201921766745U CN 210467287 U CN210467287 U CN 210467287U
- Authority
- CN
- China
- Prior art keywords
- output
- clock signal
- transistor
- signal
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses a GOA circuit for narrow frame panel, including cascaded a plurality of aversion register unit, characterized in that, the output of aversion register unit is connected with output control unit, every output control unit is used for timesharing output M GATE signal, wherein, M =2n, n > = 1; the output control unit comprises M time-sharing output units, and each time-sharing output unit is connected with a different clock signal CK control end; and each time-sharing output unit outputs a GATE driving signal according to the output signal of the shift register unit and different clock signals CK. The utility model discloses, can export the required GATE drive signal of multirow pixel drive, make an output signal that shifts and deposit the unit can provide the drive for many GATEs, be favorable to accomplishing the display panel of narrower frame.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a GOA circuit for narrow frame panel.
Background
GOA (Gate Driver on Array, Array substrate line drive) is a technology for manufacturing Gate line scan driving signal circuits on an Array substrate by using the existing tft Array process, so as to realize the driving method of Gate line scan line by line.
A GOA driver circuit (GOA circuit), typically comprises a plurality of driver cells in cascade. The GOA driving circuits are distributed in a frame area of a display product. With the rapid development of display technology, a GOA display with high integration and low cost has developed, and the reliability and output quality of the GOA are important standards for the GOA driving circuit.
Currently, as shown in fig. 1, each driving unit of a GOA driving circuit of an LCD product generally has only one output terminal, and the GATE driving signal OUT outputted by the driving unit can only provide driving for one GATE. The structure needs more layout space, and has little advantage for making narrow-frame products, for example, for a panel with a lattice of mRGB × n, if one-side driving is considered, one side needs n/2 GOA array units, and if one-side driving is considered, one side needs n GOA array units. The number of gate lines of the conventional LCD display panel is typically thousands, which requires a corresponding number of driving units. The design of the GOA driving circuit in the prior art seriously influences the reduction of the product frame.
SUMMERY OF THE UTILITY MODEL
In view of the defects of the prior art, the present application provides a GOA circuit for a narrow bezel panel, including a plurality of cascaded shift register units, an output end of each shift register unit is connected to an output control unit, and each output control unit is configured to output M GATE signals in a time-sharing manner, where M =2n, n > = 1; the output control unit comprises M time-sharing output units, and each time-sharing output unit is connected with a different clock signal CK control end; and each time-sharing output unit outputs a GATE driving signal according to the output signal of the shift register unit and different clock signals CK.
Furthermore, each shift register unit is connected with a control end of a main clock signal CLK;
the M clock signals CK corresponding to the M time-sharing output units sequentially have a difference of 1/M clock cycles of the main clock signal CLK;
the period of the M clock signals CK corresponding to the M time-sharing output units is respectively the clock period of 1/M main clock signals CLK.
Furthermore, the time-sharing output unit is a TFT transistor, and the TFT transistor outputs a GATE signal according to the output signal of the shift register unit and the clock signal CK; the TFT transistor is an NTFT transistor or a PTFT transistor.
Furthermore, the control end of the TFT transistor is connected to the output end of the shift register unit, the first end of the TFT transistor is connected to the clock signal CK, and the second end of the TFT transistor outputs a GATE driving signal.
Furthermore, each time-sharing output unit is a CMOS circuit structure formed by combining a PTFT transistor and an NTFT transistor;
each time-sharing output unit is provided with a clock signal CK input end and an inverted clock signal XCK input end, and the phases of the clock signal CK and the inverted clock signal XCK are opposite;
the CMOS circuit outputs a GATE driving signal according to the output signal of the shift register unit, the clock signal CK and the reverse clock signal XCK.
Furthermore, a first end of an NTFT transistor of the CMOS circuit is connected with an output end of the shift register unit, and a control end of the NTFT transistor is connected with a clock signal CK; the first end of a PTFT transistor of the CMOS circuit is connected with the output end of the shift register unit, and the control end of the PTFT transistor is connected with a reverse clock signal XCK; the second terminal of the NTFT transistor is connected to the second terminal of the PTFT transistor and outputs a GATE drive signal at the connection location.
Further, the output control unit has M clock signal CK control terminals and M inverted clock signal XCK control terminals;
the clock signal CK input end of the time-sharing output unit is connected with the clock signal CK control end, and the reverse clock signal XCK input end is connected with the reverse clock signal XCK control end.
Further, the output control unit has M clock signal CK control terminals;
each output control unit further comprises an inverter circuit structure formed by combining a PTFT transistor and an NTFT transistor, and the inverter outputs a reverse clock signal XCK according to a clock signal CK, a low level signal VGL and a high level signal line VGH;
the time-sharing output unit outputs a GATE signal according to the output signal of the shift register unit, the clock signal CK and the reverse clock signal XCK.
Furthermore, the control end of the PTFT transistor of the inverter and the control end of the NTFT transistor of the inverter are both connected with a clock signal CK, the first end of the PTFT transistor of the inverter is connected with a VGH high level, and the first end of the NTFT transistor of the inverter is connected with a VGL low level; and the second end of the PTFT transistor is connected with the second end of the NTFT transistor and outputs a reverse clock signal XCK.
Further, M > = 4.
Compared with the prior art, the utility model discloses following beneficial effect has:
the utility model discloses an increase output control unit, utilize clock signal CK's phase place to select, export a plurality of grid drive signals that accord with pixel required step by step, realized GOA drive circuit's many GATE output, make an output signal that shifts and deposit the unit can provide the drive for many GATE (grid), be favorable to accomplishing the display panel of narrower frame.
Drawings
Fig. 1 is a schematic structural diagram of a GOA driving circuit in the prior art;
fig. 2 is a schematic structural diagram of a GOA driving circuit according to a first embodiment;
fig. 3 is a schematic diagram illustrating a first structure of an output control unit of a GOA driving circuit according to a first embodiment of the disclosure;
fig. 4 is a schematic diagram illustrating a second structure of an output control unit of a GOA driving circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an output control unit of the GOA driving circuit according to the second embodiment;
fig. 6 is a schematic structural diagram of a GOA driving circuit according to a second embodiment;
fig. 7 is a schematic structural diagram of an output control unit of a GOA driving circuit according to a third embodiment;
fig. 8 is a schematic structural diagram of an output control unit of a GOA driving circuit according to a fourth embodiment;
fig. 9 is a schematic structural diagram of a GOA driving circuit according to a fourth embodiment;
fig. 10 is a schematic diagram of an output waveform corresponding to the clock signal according to the fourth embodiment.
The attached drawings are marked as follows:
10-shift register unit, 20-output control unit, 30-time sharing output unit and 40-inverter.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 2 to 10, for the present invention provides a GOA circuit for narrow bezel panels.
Example one
Fig. 2 shows one embodiment of a GOA circuit for a narrow-bezel panel according to this embodiment, where the GOA circuit includes a plurality of cascaded shift register units 10 (array units). Each shift register cell 10 has an output terminal and outputs a control signal. The output end of the shift register unit 10 is connected to an output control unit 20.
Only four cascaded shift register cells 10 are illustrated in fig. 2: g1, G2, G3, G4. It is understood that the number of the shift register units 10 of the GOA driving circuit is not limited thereto. The OUT1, OUT2, OUT3 and OUT4 are output control units 20 of shift register units G1, G2, G3 and G4, respectively.
The structure of one of the shift register cells G1 and its corresponding output control cell OUT1 is taken as an example for explanation. As shown in fig. 2, the control signal output from the shift register unit G1 passes through the output control unit OUT1, and through selection of 2 (M) clock signals CK1 and CK2, outputs two GATE driving signals SN1 and SN2 in a time-sharing manner, which are used as signals required for driving the pixels in 2 rows (M rows).
In the present embodiment, the output control unit 20 includes: an input end connected to the output end of the shift register unit 10, and M time-sharing output units 30, where the M time-sharing output units 30 are configured to output M gate driving signals SN at different times, and M is an integer multiple of 2.
In this embodiment, each time-sharing output unit 30 is connected to a clock signal, and each output control unit 20 includes M time-sharing output units 30, which are connected to control terminals of M clock signals CK. The control signal output by the shift register unit 10 passes through the output control unit 20-OUT, and generates the GATE driving signal SN required for driving the M rows of pixels by selecting M clock signals. As shown in fig. 3, M is specifically 2.
In the present embodiment, the time-sharing output unit 30 of the output control unit 20 may be NTFT as shown in fig. 3. Taking the output control unit 20-OUT1 as an example, the output control unit OUT1 specifically includes 2 time-sharing output units 30: NTFT (N-type TFT transistor) M1 and M2.
A control terminal (gate) of the transistor M1 is connected to the output terminal of the shift register unit G1, a first terminal of the transistor M1 is connected to the first clock signal CK1, and a second terminal of the transistor M1 outputs a gate driving signal SN1 of the first scan line. The transistor M1 is used for outputting a gate driving signal SN1 of the first scan line according to the output signal of the output terminal of the shift register unit G1 and the first clock signal CK 1.
A control terminal (gate) of the transistor M2 is connected to the output terminal of the shift register unit G1, a first terminal of the transistor M2 is connected to the first clock signal CK2, and a second terminal of the transistor M2 outputs a gate driving signal SN2 of the second scan line. The transistor M2 is used for outputting a gate driving signal SN2 of the second scan line according to the output signal of the output terminal of the shift register unit G1 and the second clock signal CK 2.
Alternatively, the time-sharing output unit 30 of the output control unit 20 may be a single PTFT as shown in fig. 4. The OUT1 output control unit 20 specifically includes 2 time-sharing output units 30: PTFT (P-type TFT transistors) M1 and M2.
The shift register units 10-G1 have one control terminal for the main clock signal CLK.
The periods of the 2 clock signals CK1, CK2 of the output control unit 20-OUT1 are the clock periods of 1/2 (1/M) of the body clock signal CLK, respectively. CK1 and CK2 differ by 1/2 (1/M) clock cycles of the body clock signal CLK.
In the present embodiment, an output control unit 20 is added, and the control signals output by the shift register unit 10 (array unit) of the GOA circuit pass through the output control unit 20, and the gate driving signals SN1 and SN2 required for driving a plurality of pixels are generated by selecting the clock signals CK1 and CK 2. The effect is that by improving the layout and increasing a plurality of TFT transistors, the GOA array unit with large area is effectively reduced, and the function of multi-row output is realized. An output signal of the shift register unit 10 can provide driving for a plurality of GATEs, which is beneficial for a display panel with a narrower frame.
Example two
Fig. 5 shows a specific structure of another output control unit 20 of the GOA circuit for narrow bezel panels according to this embodiment. Fig. 6 is a GOA circuit for a narrow bezel panel according to the present embodiment, which is a modification of the first embodiment.
As in the first embodiment, the output control unit 20 includes: an input end connected to the output end of the shift register unit 10, and M time-sharing output units 30, where the M time-sharing output units 30 are configured to output M gate driving signals SN in a time-sharing manner. M is an integer multiple of 2, M = 2.
Unlike the first embodiment, in the present embodiment, both the two time-sharing output units 30 adopt a CMOS circuit structure in which the PTFT and the NTFT shown in fig. 5 are combined.
As shown in fig. 5, each time-sharing output unit 30 of the CMOS circuit configuration is connected to two opposite clock signals, for example, the first CMOS circuit is connected to the first clock signal CK1 and the first inverted clock signal XCK1, CK1 and XCK1 with opposite levels. The second CMOS circuit connects the second clock signal CK2 and the second inverted clock signal XCK2, CK2 and XCK2 with opposite levels. In this embodiment, each time-sharing output unit 30 is connected to two opposite clock signals. Each output control unit 20 includes M time-sharing output units 30, which are connected to the control terminals of 2M clock signals CK in total.
As one specific example thereof, as shown in fig. 5, the first CMOS circuit includes an NTFT transistor M1 and a PTFT transistor M1'. A first end of the NTFT transistor M1 is connected to the output end of the shift register unit G1, and a control end (gate) of the NTFT transistor M1 is connected to the first clock signal CK 1;
a first terminal of the PTFT transistor M1 'is connected to the output terminal of the shift register cell G1, a control terminal (gate) of the PTFT transistor M1' is connected to the first inverted clock signal XCK1,
a second terminal of the NTFT transistor M1 is connected to a second terminal of the PTFT transistor M1' and outputs a gate driving signal SN1 of the first scan line at the connection position.
The second CMOS circuit includes NTFT transistor M2 and PTFT transistor M2'.
The first terminal of the transistor M2 and the first terminal of the transistor M2 ' are both connected to the output terminal of the shift register unit G1, the control terminal (gate) of the transistor M2 is connected to the second clock signal CK2, the control terminal (gate) of the transistor M2 ' is connected to the second inverted clock signal XCK2, and the second terminal of the transistor M2 and the second terminal of the transistor M2 ' are both connected to the gate driving signal SN2 of the second scan line.
The time-sharing output unit 30 of the present embodiment adopts a CMOS circuit structure, and can adopt a CMOS process, so that the output is more stable, and the multiple-output GOA circuit of the present application can be applied to LTPS low-temperature polysilicon panels. The time-sharing output unit 30 of the first embodiment only uses the general NTFT or PTFT, and the multiple-output GOA circuit is not suitable for LTPS low-temperature polysilicon panels. The resolution of the amorphous silicon panel is hardly over 720P basically, and the resolution of the low temperature polysilicon can reach 1080P or above, so the GOA circuit for the narrow frame panel of this embodiment has more obvious advantages compared with the first embodiment.
EXAMPLE III
This example is a modification of the second example. In the second embodiment, each time-sharing output unit 30 is connected with two opposite clock signals.
In order to reduce the number of clock signal lines of the output control unit 20, the present embodiment adds an inverter 40 to the circuit of the output control unit 20, and generates the level XCK with opposite phase by using the CK signal, i.e., generates the first inverted clock signal XCK1 by using the first clock signal CK1, and generates the second inverted clock signal XCK2 by using the second clock signal CK 2.
The specific circuit structure principle is as shown in fig. 7, and the inverter 40 is composed of a PTFT transistor M5 and an NTFT transistor M6. A control terminal (gate) of the PTFT transistor M5 and a control terminal (gate) of the NTFT transistor M6 are both connected to the first clock signal CK1, a first terminal of the PTFT transistor M5 is connected to VGH high level, a first terminal of the NTFT transistor M6 is connected to VGL low level, and a second terminal of the PTFT transistor M5 is connected to a second terminal of the NTFT transistor M6 and outputs the inverted clock signal of the first clock signal CK 1. The inverted clock signal is connected to the control terminal (gate) of the transistor M1' instead of the first inverted clock signal XCK1 in the second embodiment.
Similarly, the inverter 40 composed of the PTFT transistor M5 and the NTFT transistor M6 generates an inverted clock signal of the second clock signal CK2 by using the second clock signal CK2, and connects the inverted clock signal to the control terminal (gate) of the transistor M2', instead of the second inverted clock signal XCK2 in the second embodiment.
Example four
The embodiment is a modification of the first embodiment. In the first embodiment, the output control unit 20 has M time-sharing output units 30, where M = 2. The signals SN1, SN2 required for the driving of 2 rows (M rows) of pixels are thus generated.
In the present embodiment, M is an integer multiple of 2, and M may be an integer multiple of 2 such as 4, 6, 8 …, and the like. By adding the time-sharing output unit 30, M GATE drive signals SN1, SN2, SN3, SN4, … SNM can be time-shared and output as signals required for driving M rows of pixels. M =2n, n > =1, n is an integer.
Fig. 8 illustrates only the structure when M = 4. The output control unit 20-OUT1 specifically includes a time-sharing output unit 30 composed of 4 TFT transistors M1, M2, M3, and M4, wherein the 4 time-sharing output units 30 are respectively connected to clock signals CK1, CK2, CK3, and CK4, and the 4 time-sharing output units 30 respectively output signals SN1, SN2, SN3, and SN4 required for driving the pixels in 4 rows (M rows).
The two GATE signals SN1, SN2 are output in time division as signals required for driving the pixels of 2 rows (M rows).
The time-sharing output unit 30 may be an NTFT as illustrated, or may be a PTFT, which is not limited herein.
Fig. 9 is a schematic diagram of a GOA circuit for a narrow bezel panel according to this embodiment.
Fig. 10 is an output waveform corresponding to the clock signal of the present embodiment, and is used to illustrate the matching relationship between the main clock signal CLK and the clock signals CK1, CK2, CK3, and CK 4. As illustrated, the periods of the 4 clock signals CK1, CK2, CK3, CK4 of the output control unit OUT1 are respectively 1/4 (1/M) clock periods of the body clock signal CLK. CK1, CK2, CK3, CK4 differ by 1/4 (1/M) clock periods of the body clock signal CLK.
Compared with the prior art, the utility model discloses following beneficial effect has:
1. the utility model discloses, through increasing the output control unit who has a plurality of timesharing output unit, can export required GATE (grid) drive signal of multirow pixel drive, make an output end signal of aversion registering unit can provide the drive for many GATE (grid), be favorable to accomplishing the display panel of narrower frame.
2. The time-sharing output unit adopts a CMOS circuit structure, can adopt a CMOS process, can make output more stable, and can be applied to the LTPS low-temperature polycrystalline silicon panel.
It will be understood that modifications and variations can be made by those skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the appended claims.
Claims (10)
1. A GOA circuit for a narrow-bezel panel comprises a plurality of cascaded shift register units, and is characterized in that output control units are connected to output ends of the shift register units, each output control unit is used for outputting M GATE signals in a time-sharing mode, wherein M =2n, n > = 1;
the output control unit comprises M time-sharing output units, and each time-sharing output unit is connected with a different clock signal CK control end; and each time-sharing output unit outputs a GATE driving signal according to the output signal of the shift register unit and different clock signals CK.
2. The GOA driver circuit according to claim 1, wherein each shift register cell is coupled to a control terminal of a bulk clock signal CLK;
the M clock signals CK corresponding to the M time-sharing output units sequentially have a difference of 1/M clock cycles of the main clock signal CLK;
the period of the M clock signals CK corresponding to the M time-sharing output units is respectively the clock period of 1/M main clock signals CLK.
3. The GOA driver circuit according to claim 1, wherein the time-sharing output unit is a TFT transistor, and the TFT transistor outputs a GATE signal according to the output signal of the shift register unit and a clock signal CK; the TFT transistor is an NTFT transistor or a PTFT transistor.
4. The GOA driving circuit as claimed in claim 3, wherein the control terminal of the TFT transistor is connected to the output terminal of the shift register unit, the first terminal of the TFT transistor is connected to the clock signal CK, and the second terminal of the TFT transistor outputs the GATE driving signal.
5. The GOA driving circuit according to claim 1, wherein each time-sharing output unit is a CMOS circuit structure formed by combining a PTFT transistor and an NTFT transistor;
each time-sharing output unit is provided with a clock signal CK input end and an inverted clock signal XCK input end, and the phases of the clock signal CK and the inverted clock signal XCK are opposite;
the CMOS circuit outputs a GATE driving signal according to the output signal of the shift register unit, the clock signal CK and the reverse clock signal XCK.
6. The GOA driving circuit according to claim 5, wherein a first terminal of an NTFT transistor of the CMOS circuit is connected to an output terminal of the shift register unit, and a control terminal of the NTFT transistor is connected to a clock signal CK; the first end of a PTFT transistor of the CMOS circuit is connected with the output end of the shift register unit, and the control end of the PTFT transistor is connected with a reverse clock signal XCK; the second terminal of the NTFT transistor is connected to the second terminal of the PTFT transistor and outputs a GATE drive signal at the connection location.
7. The GOA driving circuit as claimed in claim 5, wherein the output control unit has M clock signal CK control terminals and M inverted clock signal XCK control terminals;
the clock signal CK input end of the time-sharing output unit is connected with the clock signal CK control end, and the reverse clock signal XCK input end is connected with the reverse clock signal XCK control end.
8. The GOA driving circuit according to claim 5, wherein the output control unit has M clock signal CK control terminals;
each output control unit further comprises an inverter circuit structure formed by combining a PTFT transistor and an NTFT transistor, and the inverter outputs a reverse clock signal XCK according to a clock signal CK, a low level signal VGL and a high level signal line VGH;
the time-sharing output unit outputs a GATE signal according to the output signal of the shift register unit, the clock signal CK and the reverse clock signal XCK.
9. The GOA driving circuit as claimed in claim 8, wherein the control terminal of the PTFT transistor of the inverter and the control terminal of the NTFT transistor are both connected to a clock signal CK, the first terminal of the PTFT transistor of the inverter is connected to VGH high level, and the first terminal of the NTFT transistor of the inverter is connected to VGL low level; and the second end of the PTFT transistor is connected with the second end of the NTFT transistor and outputs a reverse clock signal XCK.
10. The GOA driver circuit of claim 1, wherein M > = 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921766745.3U CN210467287U (en) | 2019-10-21 | 2019-10-21 | GOA circuit for narrow frame panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921766745.3U CN210467287U (en) | 2019-10-21 | 2019-10-21 | GOA circuit for narrow frame panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210467287U true CN210467287U (en) | 2020-05-05 |
Family
ID=70434524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921766745.3U Active CN210467287U (en) | 2019-10-21 | 2019-10-21 | GOA circuit for narrow frame panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210467287U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114141182A (en) * | 2020-09-03 | 2022-03-04 | 深圳市柔宇科技股份有限公司 | EOA circuit, array substrate and display device |
-
2019
- 2019-10-21 CN CN201921766745.3U patent/CN210467287U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114141182A (en) * | 2020-09-03 | 2022-03-04 | 深圳市柔宇科技股份有限公司 | EOA circuit, array substrate and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104575411B (en) | Liquid crystal display and its bi-directional shift apparatus for temporary storage | |
| CN102667909B (en) | Scan signal line driver circuit and display apparatus having same | |
| CN105118463B (en) | A kind of GOA circuits and liquid crystal display | |
| US10984738B2 (en) | Driving device and driving method of display panel | |
| WO2011092944A1 (en) | Multi-primary color display device | |
| US9928922B2 (en) | Shift register and method for driving the same, gate driving circuit and display device | |
| CN109410810B (en) | Shifting register unit and driving method thereof, grid driving circuit and display device | |
| CN106601175A (en) | Shifting register unit, driving method, grid drive circuit and display device | |
| US20160343338A1 (en) | Shift register and method for driving the same, gate driving circuit and display device | |
| CN104900211A (en) | Display device, gate driving circuit and driving method of gate driving circuit | |
| CN103985361B (en) | Gate driver circuit and control method thereof and liquid crystal display | |
| US11837147B2 (en) | Display substrate, display panel, display apparatus and display driving method | |
| CN102982777A (en) | Grid driving circuit of display device, switch control circuit and shifting register | |
| CN108320692B (en) | Shifting register unit, driving method, grid driving circuit and display panel | |
| CN108665845B (en) | Display panel and display device | |
| TW200426769A (en) | Display device and driving method thereof | |
| CN105139801A (en) | Array substrate line driving circuit, shift register, array substrate, and display | |
| CN205564251U (en) | Shift register , gate drive circuit, array substrate | |
| WO2022116371A1 (en) | Display panel and detection method thereof, and display device | |
| US11862216B2 (en) | Shift register and driving method therefor, gate driver circuit, and display apparatus | |
| CN101847374B (en) | Driving device, shift unit, buffer, shift register and driving method | |
| CN106486084A (en) | Shift register cell, gate driver circuit and its driving method, display device | |
| CN210467287U (en) | GOA circuit for narrow frame panel | |
| WO2021016942A1 (en) | Display panel, display apparatus, and driving method | |
| CN102368125B (en) | Liquid crystal display and driving method of liquid crystal display panel of same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |