CN210429860U - LED chip with high-stability current blocking layer - Google Patents

LED chip with high-stability current blocking layer Download PDF

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CN210429860U
CN210429860U CN201921316017.2U CN201921316017U CN210429860U CN 210429860 U CN210429860 U CN 210429860U CN 201921316017 U CN201921316017 U CN 201921316017U CN 210429860 U CN210429860 U CN 210429860U
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type semiconductor
semiconductor layer
annular groove
current blocking
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徐珊珊
吴疆
丁磊
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Coreach Electronic Technology Co ltd
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Abstract

The utility model discloses a LED chip with high stability current barrier layer, including DBR reflection stratum, N type semiconductor layer, luminescent layer, P type semiconductor layer, current barrier layer and P type electrode, P type semiconductor layer sets up in the luminescent layer top, just P type semiconductor layer is provided with first annular groove. The utility model has the advantages that: the utility model discloses a before growth silica, carry out the surface structure design to P type semiconductor layer, on P type semiconductor layer, and under P type electrode, etch out first annular groove, regrown silica, the current blocking layer of formation and the inseparable combination between the P type semiconductor layer, stable in structure, the current blocking layer is difficult for droing from P type semiconductor layer. The depth of the first annular groove on the P type semiconductor layer is 500A, the structural performance of the P type semiconductor layer cannot be damaged, and the depth of the second annular groove on the N type semiconductor layer is 500A, the structural performance of the N type semiconductor layer cannot be damaged.

Description

LED chip with high-stability current blocking layer
Technical Field
The utility model relates to a LED chip specifically is a LED chip with high stability electric current barrier layer, belongs to LED chip application technical field.
Background
An LED chip (namely a light emitting diode) mainly comprises a substrate layer, an epitaxial layer and a chip layer. Wherein the substrate layer is sapphire Al2O3, and the thickness is about 400 um; an epitaxial layer (i.e., a light emitting layer, with a thickness of about 6um) including a buffer layer, an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer; the chip layer comprises a current blocking layer, a transparent conductive layer, a passivation protective layer and an P, N type electrode layer, and also comprises a DBR reflective layer under the substrate.
The current blocking layer is a silicon dioxide film, is grown on the P-type semiconductor layer by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, is grown right below the P-type electrode, has the same shape as the P-type electrode, and is slightly wider than the P-type electrode. The current blocking layer has the function of increasing the uniformity of current circulation, so that the luminous efficiency of the LED is improved. Since the P-type electrode is opaque, the light emitted from this region is ineffective. In order to improve the light emitting efficiency, a current blocking layer is grown in the inactive area right below the P-type electrode to block the current, so that the current originally flowing through the inactive area can flow to other active areas.
The current blocking layer in the existing LED chip is directly grown on the P-type semiconductor layer, the current blocking layer and the P-type semiconductor layer are poor in adhesion and poor in adhesion, and the current blocking layer is prone to falling off, so that the problem that the chip falls off an electrode is caused.
SUMMERY OF THE UTILITY MODEL
The utility model discloses an aim at is directly growing on P type semiconductor layer in order to solve the current blocking layer among the current LED chip, and current blocking layer is relatively poor with P type semiconductor layer's adhesion, and it is bad to bond, the phenomenon that current blocking layer drops easily appears to lead to the chip to fall the problem of electrode, and provide a LED chip with high stability current blocking layer.
The purpose of the utility model can be realized by the following technical scheme: an LED chip with a high-stability current blocking layer comprises a DBR reflecting layer, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, a current blocking layer and a P-type electrode, wherein the P-type semiconductor layer is arranged above the light emitting layer and is provided with a first annular groove, the first annular groove is etched on the P-type semiconductor layer and right below the P-type electrode, silicon dioxide is regrown, a silicon dioxide film is grown on the surface of the first annular groove, the formed current blocking layer is tightly combined with the P-type semiconductor layer, the structure is stable, the current blocking layer is not easy to fall off from the P-type semiconductor layer, the current blocking layer is arranged above the first annular groove, a passivation protective layer is arranged above the P-type semiconductor layer, and one end of the passivation protective layer is provided with the current blocking layer;
the P-type electrode is arranged right above the first annular groove, the diameter of the first annular groove is smaller than that of the P-type electrode, and the depth of the first annular groove is 500A;
a second annular groove is formed above one end of the N-type semiconductor layer, and an N-type electrode is arranged above the second annular groove;
the diameter of the second annular groove is smaller than that of the N-type electrode, the depth of the second annular groove is 500A, the depth of the first annular groove on the P-type semiconductor layer is 500A, the structural performance of the P-type semiconductor layer cannot be damaged, the depth of the second annular groove on the N-type semiconductor layer is 500A, the structural performance of the N-type semiconductor layer cannot be damaged, and the thickness of the current blocking layer is 1600-2000A;
the preparation process of the LED chip specifically comprises the following steps:
the method comprises the following steps: using Metal Organic Chemical Vapor Deposition (MOCVD) equipment to grow a buffer layer, an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer in sequence on a sapphire substrate with the diameter of 4 inches by using an epitaxial growth method to obtain an epitaxial wafer;
carrying out photoetching pattern preparation on an epitaxial wafer, adopting positive photoresist as a mask, and etching the epitaxial wafer after photoetching by using an inductively coupled plasma device to remove a P-type semiconductor layer, a light-emitting layer and an N-type semiconductor layer with the depth of 4000A on one side and expose an N-type semiconductor mesa so as to obtain the P-type semiconductor layer and the N-type semiconductor layer;
step two: carrying out photoetching graph preparation on the product obtained in the step one, adopting a positive photoresist as a mask, and etching away a P-type semiconductor with the depth of 500A on the P-type semiconductor layer and an N-type semiconductor with the depth of 500A on the N-type semiconductor layer by using an inductively coupled plasma device, so as to obtain a first annular groove and a second annular groove on the P-type semiconductor layer and the N-type semiconductor layer;
step three: growing silicon dioxide on the first annular groove on the obtained P-type semiconductor layer by using Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment to obtain a current barrier layer;
the method for growing silicon dioxide by adopting plasma enhanced chemical vapor deposition is to use SiH4Gas and N2The O gas is subjected to chemical reaction to generate a product SiO2Deposited on the article, the chemical reaction formula is: SiH4+2N2O→ SiO2+2H2+2N2。
Step four: sputtering a transparent conducting layer;
sputtering and depositing an ITO film on the product obtained in the third step by using magnetron sputtering equipment to obtain a transparent conducting layer, wherein the ITO film is made of Sn in a molecular ratio2O3:In2O3Indium Tin Oxide (ITO) transparent conductive thin film, which is an n-type semiconductor material, has a body-centered cubic ferromanganese structure, and after Sn is doped In2O3, Sn element replaces In element In2O3 lattice and exists In SnO2 form;
step five: evaporating a metal film on the surface of the product obtained in the fourth step by using electron beam evaporation equipment, wherein the evaporated metal film is sequentially Cr, Al, Cr, Pt and Au, and removing the metal film in the areas outside the positions of the P-type electrode and the N-type electrode to obtain the P-type electrode and the N-type electrode;
step six: growing silicon dioxide as a passivation protective layer by using Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment, and removing the silicon dioxide above the P-type electrode and the N-type electrode to finish the preparation of the LED chip; the growth method of the passivation protective layer is the same as that of the current barrier layer, and silicon dioxide is grown. The silicon dioxide can be used as a current blocking layer of the LED chip and can also be used as a passivation layer of the LED chip to protect the chip from being corroded by water vapor in the external environment.
The preparation process of the first annular groove and the second annular groove specifically comprises the following steps:
s1: spin-coating a layer of positive photoresist on the product obtained in the first step by using a spin coater;
s2: a photoetching mask, using a photoetching machine, placing the product obtained in the step S1 under a photoetching plate with a ring-shaped pattern, aligning the position, and then carrying out exposure treatment, wherein the part of the photoresist covered by the pattern is not exposed, and the part of the photoresist uncovered by the pattern is exposed;
s3: developing, namely putting the product obtained in the step S2 into a developing solution by using a developing machine, reacting the photoresist of the exposed part with the developing solution, dissolving the photoresist, and not dissolving the photoresist of the unexposed part, so that the part of the pattern to be etched on the obtained product is not shielded by the photoresist, and the part which is not required to be etched is shielded by the photoresist;
s4: plasma etching, namely etching the developed product by using an inductively coupled plasma etching (ICP) device, wherein the part which is not shielded by the photoresist is etched, and the part which is shielded by the photoresist is not etched;
s5: removing the photoresist and cleaning, namely putting the etched product into a photoresist removing solution for cleaning, and completely dissolving the photoresist by the photoresist removing solution;
s6: and after degumming and cleaning, drying by using a dryer, and obtaining a first annular groove and a second annular groove from the obtained product.
The utility model discloses a further technological improvement lies in: the DBR reflection stratum top is provided with the sapphire substrate layer, just sapphire substrate layer top is provided with the buffer layer.
The utility model discloses a further technological improvement lies in: and a transparent conducting layer is arranged between the P-type semiconductor layer and the passivation protective layer.
Compared with the prior art, the beneficial effects of the utility model are that:
1. the utility model relates to a LED chip with high stability current barrier layer is before growing silicon dioxide, carries out the surface structure design to P type semiconductor layer, on P type semiconductor layer, and under P type electrode, etches out first annular groove, regrown silicon dioxide, and the silica film grows on the surface of first annular groove, combines closely between the current barrier layer of formation and the P type semiconductor layer, stable in structure, and the current barrier layer is difficult for droing from P type semiconductor layer.
2. The utility model relates to a LED chip with high stability current barrier layer, before growing N type electrode, carry out surface structure design to N type semiconductor layer, on N type semiconductor, and under N type electrode, the sculpture goes out second annular groove, regrown N type electrode, and N type electrode grows on the surface of second annular groove, closely combines between the N type electrode of formation and the N type semiconductor layer, and stable in structure can not appear the phenomenon that N type electrode falls the electrode.
3. The depth of the first annular groove on the P type semiconductor layer is 500A, the structural performance of the P type semiconductor layer cannot be damaged, and the depth of the second annular groove on the N type semiconductor layer is 500A, the structural performance of the N type semiconductor layer cannot be damaged.
Drawings
In order to facilitate understanding for those skilled in the art, the present invention will be further described with reference to the accompanying drawings.
Fig. 1 is a schematic view of the overall structure of the present invention.
Fig. 2 is a schematic diagram of the structure of the existing LED chip of the present invention.
In the figure: 1. a DBR reflective layer; 2. a sapphire substrate layer; 3. a buffer layer; 4. an N-type semiconductor layer; 5. A light emitting layer; 6. a P-type semiconductor layer; 7. a current blocking layer; 8. a transparent conductive layer; 9. passivating the protective layer; 10. a P-type electrode; 11. an N-type electrode; 12. a first annular groove; 13. a second annular groove.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1-2, an LED chip with a high-stability current blocking layer includes a DBR reflective layer 1, an N-type semiconductor layer 4, a light emitting layer 5, a P-type semiconductor layer 6, a current blocking layer 7, and a P-type electrode 10, wherein the P-type semiconductor layer 6 is disposed above the light emitting layer 5, the P-type semiconductor layer 6 is disposed with a first annular groove 12, the first annular groove 12 is etched on the P-type semiconductor layer 6 and right below the P-type electrode 10, silicon dioxide is grown, a silicon dioxide film is grown on the surface of the first annular groove 13, the formed current blocking layer 7 is tightly combined with the P-type semiconductor layer 6, the structure is stable, the current blocking layer 6 is not easily detached from the P-type semiconductor layer 6, the current blocking layer 7 is disposed above the first annular groove 12, and a passivation layer 9 is disposed above the P-type semiconductor layer 6, one end of the passivation protective layer 9 is provided with a current barrier layer 7;
the P-type electrode 10 is arranged right above the first annular groove 12, the diameter of the first annular groove 12 is smaller than that of the P-type electrode 10, and the depth of the first annular groove 12 is 500A;
a second annular groove 13 is formed above one end of the N-type semiconductor layer 4, and an N-type electrode 11 is arranged above the second annular groove 13;
wherein, the diameter of the second annular groove 13 is smaller than the N-type electrode 11, the depth of the second annular groove 13 is 500A, the depth of the first annular groove 12 on the P-type semiconductor layer 6 is 500A, the structural performance of the P-type semiconductor layer 6 cannot be damaged, the depth of the second annular groove 13 on the N-type semiconductor layer 4 is 500A, the structural performance of the N-type semiconductor layer 4 cannot be damaged, and the thickness of the current blocking layer 7 is 1600-2000A;
the preparation process of the LED chip specifically comprises the following steps:
the method comprises the following steps: using Metal Organic Chemical Vapor Deposition (MOCVD) equipment to grow a buffer layer 3, an N-type semiconductor layer 4, a light-emitting layer 5 and a P-type semiconductor layer 6 in sequence on a sapphire substrate with the diameter of 4 inches by using an epitaxial growth method to obtain an epitaxial wafer;
carrying out photoetching pattern preparation on the epitaxial wafer, adopting positive photoresist as a mask, and etching the epitaxial wafer after photoetching by using an inductively coupled plasma device to remove a P-type semiconductor layer (6), a light-emitting layer 5 and an N-type semiconductor layer 4 with the depth of about 4000A on one side and expose an N-type semiconductor mesa so as to obtain the P-type semiconductor layer 6 and the N-type semiconductor layer 4;
step two: carrying out photoetching pattern preparation on the product obtained in the step one, adopting a positive photoresist as a mask, and etching away a P-type semiconductor with the depth of 500A on the P-type semiconductor layer 6 and an N-type semiconductor with the depth of 500A on the N-type semiconductor layer 4 by using an inductively coupled plasma device, so as to obtain a first annular groove 12 and a second annular groove 13 on the P-type semiconductor layer 6 and the N-type semiconductor layer 4;
step three: growing silicon dioxide on the obtained first annular groove 12 on the P-type semiconductor layer 6 by using Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment to obtain a current barrier layer;
the method for growing silicon dioxide by adopting plasma enhanced chemical vapor deposition is to use SiH4Gas and N2The O gas is subjected to chemical reaction to generate a product SiO2Deposited on the article, the chemical reaction formula is: SiH4+2N2O→ SiO2+2H2+2N2。
Step four: sputtering the transparent conductive layer 8;
sputtering and depositing an ITO film on the product obtained in the third step by using magnetron sputtering equipment to obtain a transparent conducting layer 8, wherein the ITO film is made of Sn in a molecular ratio2O3:In2O3Indium Tin Oxide (ITO) transparent ═ 1:9The conductive film is an n-type semiconductor material and has a body-centered cubic ferromanganese structure, and after Sn is doped into In2O3, Sn replaces In elements In In2O3 crystal lattices and exists In a SnO2 form;
step five: evaporating a metal film on the surface of the product obtained in the fourth step by using electron beam evaporation equipment, wherein the evaporated metal film is sequentially Cr, Al, Cr, Pt and Au, and removing the metal film in the region except the positions of the P-type electrode 10 and the N-type electrode 11 to obtain the P-type electrode 10 and the N-type electrode 11;
step six: growing silicon dioxide as a passivation protective layer 9 by using Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment, and removing the silicon dioxide above the P-type electrode 10 and the N-type electrode 11 to finish the preparation of the LED chip; the growth method of the passivation protective layer is the same as that of the current barrier layer, and silicon dioxide is grown. The silicon dioxide can be used as a current blocking layer of the LED chip and can also be used as a passivation layer of the LED chip to protect the chip from being corroded by water vapor in the external environment.
The preparation process of the first annular groove 12 and the second annular groove 13 specifically comprises the following steps:
s1: spin-coating a layer of positive photoresist on the product obtained in the first step by using a spin coater;
s2: a photoetching mask, using a photoetching machine, placing the product obtained in the step S1 under a photoetching plate with a ring-shaped pattern, aligning the position, and then carrying out exposure treatment, wherein the part of the photoresist covered by the pattern is not exposed, and the part of the photoresist uncovered by the pattern is exposed;
s3: developing, namely putting the product obtained in the step S2 into a developing solution by using a developing machine, reacting the photoresist of the exposed part with the developing solution, dissolving the photoresist, and not dissolving the photoresist of the unexposed part, so that the part of the pattern to be etched on the obtained product is not shielded by the photoresist, and the part which is not required to be etched is shielded by the photoresist;
s4: plasma etching, namely etching the developed product by using an inductively coupled plasma etching (ICP) device, wherein the part which is not shielded by the photoresist is etched, and the part which is shielded by the photoresist is not etched;
s5: removing the photoresist and cleaning, namely putting the etched product into a photoresist removing solution for cleaning, and completely dissolving the photoresist by the photoresist removing solution;
s6: after degumming and cleaning, drying by a dryer, and obtaining a first annular groove 12 and a second annular groove 13.
The utility model discloses a further technological improvement lies in: a sapphire substrate layer is arranged above the DBR reflecting layer 1
2, and a buffer layer 3 is arranged above the sapphire substrate layer 2.
The utility model discloses a further technological improvement lies in: a transparent conductive layer 8 is arranged between the P-type semiconductor layer 6 and the passivation protective layer 9.
Compared with the prior art, the beneficial effects of the utility model are that:
1. the utility model relates to a LED chip with high stability current barrier layer is before growing silicon dioxide, carries out the surface structure design to P type semiconductor layer 6, on P type semiconductor layer 6, and under P type electrode 10, etch out first annular groove 12, regrown silicon dioxide, the silica film grows on the surface of first annular groove 13, and the current barrier layer 7 of formation and the inseparable combination between P type semiconductor layer 6, stable in structure, current barrier layer 6 is difficult for droing from P type semiconductor layer 6.
2. The utility model relates to a LED chip with high stability current barrier layer, before growing N type electrode 11, carry out the surface structure design to N type semiconductor layer 4, on N type semiconductor 4, and under N type electrode 11, the sculpture goes out second annular groove 13, regrown N type electrode 11, N type electrode 11 grows on the surface of second annular groove 13, closely combine between the N type electrode 11 of formation and N type semiconductor layer 4, stable in structure, the phenomenon that N type electrode 11 falls the electrode can not appear.
3. The depth of the first annular groove 12 on the P-type semiconductor layer 6 is 500A, which does not damage the structural performance of the P-type semiconductor layer 6, and the depth of the second annular groove 13 on the N-type semiconductor layer 4 is 500A, which does not damage the structural performance of the N-type semiconductor layer 4.
The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. The preferred embodiments are not exhaustive and do not limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims (3)

1. An LED chip with a high-stability current blocking layer comprises a DBR (distributed Bragg reflector) reflecting layer (1), an N-type semiconductor layer (4), a light emitting layer (5), a P-type semiconductor layer (6), a current blocking layer (7) and a P-type electrode (10), wherein the P-type semiconductor layer (6) is arranged above the light emitting layer (5), a first annular groove (12) is formed in the P-type semiconductor layer (6), the current blocking layer (7) is arranged above the first annular groove (12), a passivation protective layer (9) is arranged above the P-type semiconductor layer (6), and the current blocking layer (7) is arranged at one end of the passivation protective layer (9);
the P-type electrode (10) is arranged right above the first annular groove (12), the diameter of the first annular groove (12) is smaller than that of the P-type electrode (10), and the depth of the first annular groove (12) is 500A;
a second annular groove (13) is formed above one end of the N-type semiconductor layer (4), and an N-type electrode (11) is arranged above the second annular groove (13);
wherein the diameter of the second annular groove (13) is smaller than that of the N-type electrode (11), the depth of the second annular groove (13) is 500A, and the thickness of the current blocking layer (7) is 1600-2000A.
2. The LED chip with the high-stability current blocking layer according to claim 1, wherein a sapphire substrate layer (2) is arranged above the DBR reflecting layer (1), and a buffer layer (3) is arranged above the sapphire substrate layer (2).
3. The LED chip with the high-stability current blocking layer according to claim 1, wherein a transparent conducting layer (8) is arranged between the P-type semiconductor layer (6) and the passivation protective layer (9).
CN201921316017.2U 2019-08-14 2019-08-14 LED chip with high-stability current blocking layer Active CN210429860U (en)

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