CN210379041U

CN210379041U - Semiconductor structure

Info

Publication number: CN210379041U
Application number: CN201921696726.8U
Authority: CN
Inventors: 徐朋辉
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-10-11
Filing date: 2019-10-11
Publication date: 2020-04-21
Anticipated expiration: 2029-10-11

Abstract

The utility model relates to a semiconductor structure; the method comprises the following steps: providing a substrate; forming a first graph structure on the front surface of the base body; forming a first dielectric layer on the side wall of the first pattern structure, the surface far away from the substrate and the front surface of the substrate; forming a first low-k dielectric layer on the surface of the first dielectric layer, wherein the surface of the first low-k dielectric layer, which is far away from the substrate, is lower than the surface of the first pattern structure, which is far away from the substrate; a second dielectric layer formed on the surface of the first dielectric layer and the first low-k material; and planarizing the second dielectric layer and part of the first dielectric layer until the first patterned structure is exposed and the surface of the first low-k dielectric layer is covered with the second dielectric layer. The semiconductor structure takes the first low-k dielectric layer as a dielectric layer at the periphery of the first graph structure, so that RC signal delay can be reduced; the damage to the side wall of the first low-k dielectric layer is avoided, the appearance of the side wall of the first low-k dielectric layer is guaranteed, the electric leakage phenomenon caused by uneven appearance of the side wall of the interconnection structure is avoided, and the performance of the device is improved.

Description

Semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor device manufacturing technologies, and in particular, to a semiconductor structure.

Background

With the continuous development of semiconductor technology, the feature size of semiconductor integrated circuit devices is continuously reduced, and the RC (Resistor Capacitor) signal delay is more and more serious; to solve this problem, low dielectric constant (low-k) materials are generally used to reduce the RC signal delay.

However, since the low-k material (e.g., SiOCH, carbon-containing silicon oxide) is relatively loose, when the low-k material is etched, the loss of methyl groups in the microporous structure film is accelerated by the plasma, which increases the dielectric constant of the low-k material, causes etching damage, and causes uneven sidewall morphology of the etched pattern, such as Large Edge Roughness (LER) of the etched pattern, large bottom roughness of the trench, and the like; however, as the back-end copper interconnect critical dimensions and line-to-line pitch dimensions decrease, the impact of edge roughness and trench bottom roughness on electrical performance also increases, e.g., edge roughness may lead to higher device leakage and time-dependent dielectric breakdown; at the same time, the resistance of the copper interconnect structure also increases with increasing edge roughness under the effect of electron scattering.

SUMMERY OF THE UTILITY MODEL

Therefore, it is necessary to provide a semiconductor structure for solving the problems that the shape of the etched trench sidewall is poor, further leakage current is easily generated, a dielectric layer is broken down, the resistance of the conductive interconnection structure is increased, and the like due to the fact that the low-k material layer needs to be etched when the conductive interconnection structure is formed in the low-k material layer in the prior art of the semiconductor structure.

In order to achieve the above object, in one aspect, the present invention provides a semiconductor structure, including:

a substrate;

a first low-k dielectric layer located on the front surface of the substrate;

the first graphic structure is positioned in the first low-k dielectric layer and penetrates through the first low-k dielectric layer along the thickness direction; the surface of the first low-k dielectric layer, which is far away from the substrate, is lower than the surface of the first pattern structure, which is far away from the substrate;

the first dielectric layer is positioned between the first low-k dielectric layer and the first graph structure and between the first low-k dielectric layer and the substrate;

and the second dielectric layer is positioned on the surface of the first low-k dielectric layer.

The semiconductor structure takes the first low-k dielectric layer as a dielectric layer at the periphery of the pattern structure, so that RC signal delay can be reduced; in the preparation process, the damage to the side wall of the first low-k dielectric layer can be avoided, the appearance of the side wall of the first low-k dielectric layer is ensured, the electric leakage phenomenon caused by uneven appearance of the side wall of the interconnection structure is avoided, and the performance of the device is improved.

In one embodiment, the first pattern structure is an interconnect structure; the height difference between the surface of the first low-k dielectric layer far away from the substrate and the surface of the first pattern structure far away from the substrate is 0.5-2 times of the thickness of the first dielectric layer.

In one embodiment, the method further comprises the following steps:

a second low-k dielectric layer on a surface of the second dielectric layer;

the second graphic structure is positioned in the second low-k dielectric layer, penetrates through the second low-k dielectric layer along the thickness direction, and the bottom of the second graphic structure is contacted with the top of the first graphic structure; the surface of the second low-k dielectric layer far away from the first low-k dielectric layer is lower than the surface of the second pattern structure far away from the first low-k dielectric layer;

the third dielectric layer is positioned between the second low-k dielectric layer and the second graphic structure and between the second low-k dielectric layer and the second dielectric layer;

and the fourth dielectric layer is positioned on the surface of the second low-k dielectric layer.

In one embodiment, the first graphic structure and the second graphic structure together form an interconnection structure; the height difference between the surface of the first low-k dielectric layer, which is far away from the substrate, and the surface of the first pattern structure, which is far away from the substrate, is 0.5-2 times of the thickness of the first dielectric layer; the height difference between the surface of the second low-k dielectric layer far away from the first low-k dielectric layer and the surface of the second pattern structure far away from the first low-k dielectric layer is 0.5-2 times of the thickness of the third dielectric layer.

Drawings

Fig. 1 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structure diagram of the structure obtained in step S11 in the method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 3 to 4 are schematic cross-sectional views illustrating the structure obtained in step S12 in the method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 5 is a schematic cross-sectional structure diagram of the structure obtained in step S13 in the method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 6 is a schematic cross-sectional structure diagram of the structure obtained in step S14 in the method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 7 is a schematic cross-sectional view illustrating the structure obtained in step S15 in the method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 8 is a schematic cross-sectional view illustrating the structure obtained in step S16 in the method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 9 is a flow chart of a method of forming a semiconductor structure according to another embodiment of the present invention;

fig. 10 is a schematic cross-sectional view illustrating the structure obtained in step S27 in the method for forming a semiconductor structure according to another embodiment of the present invention;

fig. 11 is a schematic cross-sectional view illustrating the structure obtained in step S28 in the method for forming a semiconductor structure according to another embodiment of the present invention;

fig. 12 is a flow chart of a method of forming a semiconductor structure in yet another embodiment of the present invention;

fig. 13 to 14 are schematic cross-sectional views illustrating the structure obtained in step S307 in the method for forming a semiconductor structure according to still another embodiment of the present invention;

fig. 15 is a schematic cross-sectional view illustrating a structure obtained in step S308 of a method for forming a semiconductor structure according to still another embodiment of the present invention;

fig. 16 is a schematic cross-sectional view illustrating the structure obtained in step S309 in the method for forming a semiconductor structure according to still another embodiment of the present invention;

fig. 17 is a schematic cross-sectional view illustrating the structure obtained in step S310 of the method for forming a semiconductor structure according to still another embodiment of the present invention;

fig. 18 is a schematic cross-sectional view illustrating the structure obtained in step S311 in the method for forming a semiconductor structure according to still another embodiment of the present invention;

fig. 19 is a flow chart of a method of forming a semiconductor structure in accordance with yet another embodiment of the present invention;

fig. 20 is a schematic cross-sectional view illustrating a structure obtained in step S412 of a method for forming a semiconductor structure according to still another embodiment of the present invention;

fig. 21 is a schematic cross-sectional view illustrating the structure obtained in step S413 of the method for forming a semiconductor structure according to still another embodiment of the present invention.

Description of reference numerals:

10 base body

11 first graphic structure

111 first graphic material layer

12 first patterned mask layer

13 first dielectric layer

14 first low-k dielectric layer

15 second dielectric layer

16. 23 interconnect vias

17. 24 interconnect structure

18 second pattern structure

181 second pattern structure material layer

19 second patterned mask layer

20 third dielectric layer

21 second low-k dielectric layer

22 fourth dielectric layer

23 interconnect vias

241 first interconnection part

242 second interconnection

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In one embodiment, as shown in fig. 1, a method for forming a semiconductor structure of the present invention includes the steps of:

s11: providing a substrate;

s12: forming a first graph structure on the front surface of the base body;

s13: forming a first dielectric layer on the side wall of the first pattern structure, the surface far away from the substrate and the front surface of the substrate;

s14: forming a first low-k dielectric layer on the surface of the first dielectric layer, wherein the surface of the first low-k dielectric layer, which is far away from the substrate, is lower than the surface of the first pattern structure, which is far away from the substrate;

s15: a second dielectric layer formed on the surface of the first dielectric layer and the first low-k material;

s16: and planarizing the second dielectric layer and part of the first dielectric layer until the first patterned structure is exposed and the surface of the first low-k dielectric layer is covered with the second dielectric layer.

In one example, as shown in FIG. 2, the substrate 10 provided in step S11 may include, but is not limited to, a silicon substrate; the front side of the body 10 may be formed with device structures that require electrical extraction.

In one example, as shown in fig. 3 and 4, step S12 may include the following steps:

s121: forming a first pattern structure material layer 111 on the upper surface of the substrate 10, forming a first pattern structure material layer 111 on the upper surface of the first pattern structure material layer 111, and forming a first patterned mask layer 12 on the upper surface of the first pattern structure material layer 111, as shown in fig. 3; specifically, the first pattern structure material layer 111 may be formed on the upper surface of the substrate 10 by using, but not limited to, a Chemical Vapor Deposition (CVD) process, and the first pattern structure material layer 111 may be a conductive material layer, specifically, the first pattern structure material layer 111 may include, but not limited to, an aluminum layer, and in other examples, the first pattern structure material layer 111 may further include a doped polysilicon layer, etc.; the first patterned mask layer 12 may include, but is not limited to, a patterned photoresist layer, and a specific method for forming the patterned photoresist layer on the upper surface of the first pattern structure material layer 111 may include: first, a photoresist layer may be formed on the upper surface of the first pattern structure material layer 111 by, but not limited to, a spin coating process; then, exposing and developing the photoresist layer to form a patterned photoresist layer;

s122: etching the first pattern structure material layer 111 based on the first patterned mask layer 12 to form a first pattern structure 11, and removing the first patterned mask layer 12, as shown in fig. 4; specifically, the first pattern structure material layer 111 may be dry etched, but not limited to, to form the first pattern structure 11; the first patterned mask layer 12 may be removed using, but not limited to, an ashing process. In this embodiment, the first pattern structure 11 may be an interconnect structure.

In one example, as shown in fig. 5, the first dielectric layer 13 may be formed in step S13 by, but not limited to, an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process, a Low Pressure Chemical Vapor Deposition (LPCVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDP-CVD) process, a radical-enhanced CVD (laser-enhanced CVD, receiv) or an Atomic Layer Deposition (ALD) process; the first dielectric layer 13 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer.

In one example, the thicknesses of the first dielectric layer 13 and the second dielectric layer 15 may be set according to actual needs, and preferably, in this embodiment, the thicknesses of the first dielectric layer 13 and the second dielectric layer 15 may be both 1 nanometer (nm) to 10 nanometers.

In an example, as shown in fig. 6, the first low-k dielectric layer 14 may be formed in step S14 by, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process, or an atomic layer deposition process; the first low-k dielectric layer 14 may include, but is not limited to, a carbon-doped silicon oxide layer (e.g., SiOCH), a fluorine-doped silicon oxide layer, a fluorocarbon layer, a polyimide layer, or the like.

In one example, the surface of the first low-k dielectric layer 14 away from the substrate 10 (i.e., the upper surface of the first low-k dielectric layer 14 shown in fig. 6) initially formed in step S14 may be higher than the surface of the first pattern structure 11 away from the substrate 10 (i.e., the upper surface of the first pattern structure 11 shown in fig. 6), and at this time, removing a portion of the first low-k dielectric layer 14 by, but not limited to, dry etching is further included, so that the surface of the first low-k dielectric layer 14 away from the substrate 10 is lower than the surface of the first pattern structure 11 away from the substrate 10, as shown in fig. 6; preferably, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the surface of the first pattern structure 11 away from the substrate 10 is 0.5 to 2 times the thickness of the first dielectric layer 13, that is, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the upper surface of the first dielectric layer 13 located on the surface of the first pattern structure 11 away from the substrate 10 is 1.5 to 3 times the thickness of the first dielectric layer 13, and more preferably, in this embodiment, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the surface of the first pattern structure 11 away from the substrate 10 is 1 time the thickness of the first dielectric layer 13, that is, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the upper surface of the first dielectric layer 13 located on the surface of the first pattern structure 11 away from the substrate 10 is 2 times the thickness of the first dielectric layer 13.

In one example, as shown in fig. 7, in step S15, the second dielectric layer 15 may be formed by, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process, or an atomic layer deposition process; the second dielectric layer 15 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer.

In one example, the material of the first dielectric layer 13 and the material of the second dielectric layer 15 may be the same.

In one example, in step S16, the second dielectric layer 15 and a portion of the first dielectric layer 13 may be planarized using, but not limited to, a Chemical Mechanical Polishing (CMP) process. Since the surface of the first low-k dielectric layer 14 away from the substrate 10 is lower than the surface of the first pattern structure 11 away from the substrate 10, it is ensured that the surface of the first low-k dielectric layer 14 is still covered with the second dielectric layer 15 after planarization. After the planarization process, the upper surface of the first pattern structure 11 and the upper surface of the second dielectric layer 15 may be flush, as shown in fig. 8.

In the forming method of the semiconductor structure of the embodiment, the first low-k dielectric layer 14 is used as a dielectric layer at the periphery of the first pattern structure 11, so that the RC signal delay can be reduced; by adjusting the process steps, damage to the side wall of the first low-k dielectric layer 14 is avoided, the appearance of the side wall of the first low-k dielectric layer 14 is ensured, the phenomenon of electric leakage caused by uneven appearance of the side wall of the first pattern structure 11 is avoided, and the performance of the device is improved.

In another embodiment, as shown in fig. 9, the present invention further provides a method for forming a semiconductor structure, wherein steps S21 to S26 of the method for forming a semiconductor structure of this embodiment are substantially the same as steps S11 to S16 of the method for forming a semiconductor structure of the embodiment (here, the first method embodiment) illustrated in fig. 1 to 8, and the difference therebetween is that: the first pattern structure 11 formed in the first method embodiment is a conductive interconnect structure; the pattern structure 11 formed in the present embodiment is a sacrificial structure defining the shape and position of the interconnect structure, and the method for forming the semiconductor structure of the present embodiment further includes the following steps compared to the first method embodiment:

s27: removing the first pattern structure 11 to form an interconnection via 16, as shown in fig. 10;

s28: the interconnect via 16 is filled with a conductive material to form an interconnect structure 17, as shown in fig. 11.

The method for forming the semiconductor structure of the present embodiment includes steps S21 through S26, which are described with reference to the first method embodiment and fig. 1 through 8, and will not be described again here.

In an example, the material of the first pattern structure 11 in the present embodiment may include a dielectric material, such as: silicon oxide, silicon nitride, or silicon oxide and silicon nitride.

It should be noted that, in the present embodiment, the material of the first pattern structure 11 is different from the material of the first dielectric layer 13 and the material of the second dielectric layer 15, and specifically, the material of the first pattern structure 11 has a higher etching selectivity than the material of the first dielectric layer 13 and the material of the second dielectric layer 15, so as to ensure that the first dielectric layer 13 and the second dielectric layer 15 are hardly removed when the first pattern structure 11 is removed.

In one example, in step S27, all the first pattern structure 11 may be removed by a wet etching process or a dry etching process to form the interconnect via 16, and the interconnect via 16 penetrates through the first low-k dielectric layer 14 along the thickness direction to ensure that the interconnect via 16 exposes the front surface of the substrate 10, as shown in fig. 10.

In one example, the interconnect structure 17 may be formed by filling the interconnect via 16 with a conductive material in step S28 by, but not limited to, a chemical vapor deposition process or an electroplating process. The material of interconnect structure 17 may include, but is not limited to, copper; in other examples, the material of the interconnect structure 17 may also include aluminum or doped polysilicon, etc.

In the forming method of the semiconductor structure of the embodiment, the first low-k dielectric layer 14 is used as a dielectric layer at the periphery of the interconnection structure 17, so that the RC signal delay can be reduced; by adjusting the process steps, damage to the side wall of the first low-k dielectric layer 14 is avoided, the appearance of the side wall of the first low-k dielectric layer 14 is guaranteed, the phenomenon of electric leakage caused by uneven appearance of the side wall of the first pattern structure is avoided, and the performance of the device is improved.

In another embodiment, as shown in fig. 12, the present invention further provides a method for forming a semiconductor structure, wherein steps S301 to S306 in the method for forming a semiconductor structure of this embodiment are identical to steps S11 to S16 in the method for forming a semiconductor structure of the first embodiment, and the method further includes the following steps in comparison with the first embodiment:

s307: forming a second graphic structure on the surface of the first graphic structure and the surface of the second dielectric layer, wherein the bottom of the second graphic structure is contacted with the top of the first graphic structure;

s308: forming a third dielectric layer on the side wall of the second pattern structure, the surface far away from the first pattern structure and the surface of the second dielectric layer;

s309: forming a second low-k dielectric layer on the surface of the third dielectric layer, wherein the surface of the second low-k dielectric layer far away from the first low-k dielectric layer is lower than the surface of the second pattern structure far away from the first pattern structure;

s310: forming a fourth dielectric layer on the surfaces of the third dielectric layer and the second low-k dielectric layer;

s311: and planarizing the fourth dielectric layer and part of the third dielectric layer until the second graphic structure is exposed and the surface of the second low-k dielectric layer is covered with the fourth dielectric layer.

In the method for forming a semiconductor structure according to the present embodiment, please refer to the first method embodiment and fig. 1 to 8, which will not be described herein again.

In one example, as shown in fig. 13 and 14, step S307 may include the steps of:

s307 a: forming a second pattern structure material layer 181 on the surface of the first pattern structure 11 and the surface of the second dielectric layer 15, and forming a second patterned mask layer 19 on the surface of the second pattern structure material layer 1821 away from the second dielectric layer 15 (i.e., the upper surface of the second pattern structure material layer 181 in fig. 13), as shown in fig. 13; specifically, the second pattern structure material layer 181 may be formed by, but not limited to, a chemical vapor deposition process; the material of the second pattern structure material layer 181 may include a conductive material, specifically, the second pattern structure material layer 181 may include, but is not limited to, an aluminum layer, and in other examples, the second pattern structure material layer 181 may further include a doped polysilicon layer, etc.; the second patterned mask layer 19 may include, but is not limited to, a patterned photoresist layer, and a specific method of forming the patterned photoresist layer on the upper surface of the second patterned structure material layer 181 may include: first, a photoresist layer may be formed on the upper surface of the second pattern structure material layer 181 by using, but not limited to, a spin coating process; then, exposing and developing the photoresist layer to form a patterned photoresist layer;

s307 b: etching the second pattern structure material layer 181 based on the second patterned mask layer 19 to form a second pattern structure 18, and removing the second patterned mask layer 19, as shown in fig. 14; specifically, the second patterning structure material layer 181 may be dry etched to form the second patterning structure 18; the second patterned masking layer 19 can be removed using, but not limited to, an ashing process. In the present embodiment, the second pattern structure 18 and the first pattern structure 11 together constitute an interconnect structure.

In an example, the width of the second pattern structure 18 may be greater than the width of the first pattern structure 11.

In one example, as shown in fig. 15, the third dielectric layer 20 may be formed in step S308 by, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process, or an atomic layer deposition process; the third dielectric layer 20 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer.

In one example, the thicknesses of the third dielectric layer 20 and the fourth dielectric layer 22 can be set according to actual needs, and preferably, in this embodiment, the thicknesses of the third dielectric layer 20 and the fourth dielectric layer 22 can be both 1 nm to 10 nm.

In an example, as shown in fig. 16, the second low-k dielectric layer 21 may be formed in step S309 by using, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process, or an atomic layer deposition process; the second low-k dielectric layer 21 may include, but is not limited to, a carbon-doped silicon oxide layer (e.g., SiOCH), a fluorine-doped silicon oxide layer, a fluorocarbon layer, a polyimide layer, or the like.

In one example, the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 initially formed in step S309 (i.e., the upper surface of the second low-k dielectric layer 21 shown in fig. 16) may be higher than the surface of the second pattern structure 18 away from the first low-k dielectric layer 14 (i.e., the upper surface of the second pattern structure 18 shown in fig. 16), and at this time, removing a portion of the second low-k dielectric layer 21 by, but not limited to, dry etching is further included to make the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 lower than the surface of the second pattern structure 18 away from the first low-k dielectric layer 14, as shown in fig. 16; preferably, the height difference between the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 and the surface of the second pattern structure 18 away from the first low-k dielectric layer 14 is 0.5 to 2 times the thickness of the third dielectric layer 20, that is, the height difference between the surface of the second low-k dielectric layer 21 far away from the first low-k dielectric layer 14 and the upper surface of the third dielectric layer 20 on the surface of the second pattern structure 18 far away from the first low-k dielectric layer 14 is 1.5 to 3 times the thickness of the third dielectric layer 20, and more preferably, in the present embodiment, the difference between the height of the second low-k dielectric layer 21 away from the surface of the first low-k dielectric layer 14 and the height of the second pattern structure 18 away from the surface of the first low-k dielectric layer 14 is 1 times the thickness of the third dielectric layer 20, that is, the height difference between the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 and the upper surface of the third dielectric layer 20 on the surface of the second pattern structure 18 away from the first low-k dielectric layer 14 is 2 times the thickness of the third dielectric layer 20.

In one example, as shown in fig. 17, in step S310, the fourth dielectric layer 22 may be formed by, but not limited to, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, a radical enhanced chemical vapor deposition process, or an atomic layer deposition process; the fourth dielectric layer 22 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer.

In one example, the material of the first dielectric layer 13, the material of the second dielectric layer 15, the material of the third dielectric layer 20, and the material of the fourth dielectric layer 22 may be the same; the material of the first low-k dielectric layer 14 may be the same as the material of the second low-k dielectric layer 18, but the material of the first low-k dielectric layer 14 and the material of the second low-k dielectric layer 18 may be different from the material of the first dielectric layer 13, the material of the second dielectric layer 15, the material of the third dielectric layer 20, and the material of the fourth dielectric layer 22.

In one example, in step S311, the fourth dielectric layer 22 and a portion of the third dielectric layer 20 may be planarized using, but not limited to, a Chemical Mechanical Polishing (CMP) process. Since the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 is lower than the surface of the second pattern structure 18 away from the first low-k dielectric layer 14, the surface of the second low-k dielectric layer 14 is still covered with the fourth dielectric layer 22 after planarization. After the planarization process, the upper surface of the second pattern structure 18 and the upper surface of the fourth dielectric layer 22 may be flush, as shown in fig. 18.

In the method for forming the semiconductor structure of the embodiment, the first low-k dielectric layer 14 and the second low-k dielectric layer 21 are used as the dielectric layers of the periphery of the interconnection structure formed by the first pattern structure 11 and the second pattern structure 18, so that the RC signal delay can be reduced; by adjusting the process steps, damage to the side walls of the first low-k dielectric layer 14 and the second low-k dielectric layer 21 is avoided, the shapes of the side walls of the first low-k dielectric layer 14 and the second low-k dielectric layer 21 are ensured, the phenomenon of electric leakage caused by uneven shapes of the side walls of the first pattern structure 11 and the second pattern structure 18 is avoided, and the performance of the device is improved.

In another embodiment, as shown in fig. 19, the present invention further provides a method for forming a semiconductor structure, wherein steps S401 to S411 of the method for forming a semiconductor structure of this embodiment are substantially the same as steps S301 to S311 of the method for forming a semiconductor structure of the embodiment (here, the third embodiment) shown in fig. 12 to 18, and the difference therebetween is that: the first pattern structure 11 and the second pattern structure 18 formed in the third method embodiment are conductive interconnection structures; the first pattern structure 11 and the second pattern structure 18 formed in the present embodiment together form a sacrificial structure defining the shape and the position of the interconnect structure, and the method for forming the semiconductor structure of the present embodiment further includes the following steps compared with the third method embodiment:

s412: removing the first pattern structure 11 and the second pattern structure 18 to form an interconnection via 23, as shown in fig. 20;

s413: the interconnect via 23 is filled with a conductive material to form an interconnect structure 24, as shown in fig. 21.

For the specific method of steps S401 to S411 in the method for forming a semiconductor structure of this embodiment, please refer to the third embodiment and fig. 12 to 18, which will not be described herein again.

In an example, in the present embodiment, the material of the first pattern structure 11 and the material of the second pattern structure 18 may include dielectric materials, such as: silicon oxide, silicon nitride, or silicon oxide and silicon nitride. The material of the first graphic structure 11 may be the same as the material of the second graphic structure 18.

It should be noted that, in the present embodiment, the material of the first pattern structure 11 and the material of the second pattern structure 18 are different from the material of the first dielectric layer 13, the material of the second dielectric layer 15, the material of the third dielectric layer 20, and the material of the fourth dielectric layer 22, and specifically, the material of the first pattern structure 11 and the material of the second pattern structure 18 have a higher etching selectivity than the material of the first dielectric layer 13, the material of the second dielectric layer 15, the material of the third dielectric layer 20, and the material of the fourth dielectric layer 22, so as to ensure that the first dielectric layer 13, the second dielectric layer 15, the third dielectric layer 20, and the fourth dielectric layer 22 are hardly removed when the first pattern structure 11 and the second pattern structure 18 are removed.

In one example, in step S412, a wet etching process or a dry etching process may be used to remove all of the first pattern structure 11 and the second pattern structure 18 to form the interconnection via 23, and the interconnection via 23 penetrates through the first low-k dielectric layer 14 and the second low-k dielectric layer 21 in the thickness direction to ensure that the interconnection via 23 exposes the front surface of the substrate 10, as shown in fig. 20.

In one example, the interconnect structure 24 may be formed by filling the interconnect via 23 with a conductive material in step S413 by, but not limited to, a chemical vapor deposition process or an electroplating process. The material of interconnect structure 24 may include, but is not limited to, copper; in other examples, the material of interconnect structure 24 may also include aluminum or doped polysilicon, etc.

In one example, as shown in fig. 21, the interconnect structure 24 includes a first interconnect 241 and a second interconnect 242, the first interconnect 241 being located within the first low-k dielectric layer 14 and penetrating the first low-k dielectric layer 14 in a thickness direction; the second interconnect 242 is located in the second low-k dielectric layer 21 and penetrates through the second low-k dielectric layer 21 along the thickness direction, and the bottom of the second interconnect 242 contacts the top of the first interconnect 241; the width of the second interconnection 242 is greater than the width of the first interconnection 241.

In the forming method of the semiconductor structure of the embodiment, the first low-k dielectric layer 14 and the second low-k dielectric layer 21 are used as dielectric layers at the periphery of the interconnection structure 24, so that the RC signal delay can be reduced; in the preparation process, the damage to the side walls of the first low-k dielectric layer 14 and the second low-k dielectric layer 21 can be avoided, the appearance of the side walls of the first low-k dielectric layer 14 and the second low-k dielectric layer 21 is ensured, the electric leakage phenomenon caused by uneven appearance of the side walls of the interconnection structure 24 is avoided, and the performance of the device is improved.

In another embodiment, with continued reference to fig. 8, the present invention further provides a semiconductor structure, including: a base body 10; a first low-k dielectric layer 14, the first low-k dielectric layer 14 being located on the front surface of the substrate 10; the first pattern structure 11 is positioned in the first low-k dielectric layer 14, and the first pattern structure 11 penetrates through the first low-k dielectric layer 14 along the thickness direction; the surface of the first low-k dielectric layer 14 far away from the substrate 10 is lower than the surface of the first pattern structure 11 far away from the substrate 10; a first dielectric layer 13, the first dielectric layer 13 is positioned between the first low-k dielectric layer 14 and the first pattern structure 11 and between the first low-k dielectric layer 14 and the substrate 10; and a second dielectric layer 15, wherein the second dielectric layer 15 is positioned on the surface of the first low-k dielectric layer 14.

In one example, the substrate 10 may include, but is not limited to, a silicon substrate; device structures that need to be electrically extracted through the upper surface of the base 10 may be formed within the base 10.

In one example, the first low-k dielectric layer 14 may include, but is not limited to, a carbon-doped silicon oxide layer (e.g., SiOCH), a fluorine-doped silicon oxide layer, a fluorocarbon layer, a polyimide layer, or the like.

In one example, the first pattern structure 11 may be an interconnect structure or a sacrificial structure for defining the shape and position of the interconnect structure; when the first pattern structure 11 is an interconnect structure, the material of the first pattern structure 11 may include aluminum, copper, doped polysilicon, and the like; when the first pattern structure 11 is a sacrificial structure, the material of the first pattern structure 11 may include a dielectric material, such as: silicon oxide, silicon nitride, or silicon oxide and silicon nitride, and the like.

In one example, the surface of the first low-k dielectric layer 14 away from the substrate 10 is lower than the surface of the first pattern structure 11 away from the substrate 10, as shown in fig. 8; preferably, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the surface of the first pattern structure 11 away from the substrate 10 is 0.5 to 2 times the thickness of the first dielectric layer 13, that is, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the upper surface of the first dielectric layer 13 located on the surface of the first pattern structure 11 away from the substrate 10 is 1.5 to 3 times the thickness of the first dielectric layer 13, and more preferably, in this embodiment, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the surface of the first pattern structure 11 away from the substrate 10 is 1 time the thickness of the first dielectric layer 13, that is, the height difference between the surface of the first low-k dielectric layer 14 away from the substrate 10 and the upper surface of the first dielectric layer 13 located on the surface of the first pattern structure 11 away from the substrate 10 is 2 times the thickness of the first.

In one example, the first dielectric layer 13 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer; the second dielectric layer 15 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer; the material of the first dielectric layer 13 may be the same as that of the second dielectric layer 15.

In one example, the thickness of the first dielectric layer 13 and the thickness of the second dielectric layer 15 may be set according to actual needs, and preferably, in this embodiment, the thickness of the first dielectric layer 13 may be 1 nm to 10 nm, and the thickness of the second dielectric layer 15 may be 1 nm to 10 nm.

In the semiconductor structure of the embodiment, the first low-k dielectric layer 14 is used as a dielectric layer at the periphery of the first pattern structure 11, so that the RC signal delay can be reduced; the first dielectric layer 13 and the second dielectric layer 15 coat the first low-k dielectric layer 14, so that the side wall of the first low-k dielectric layer 14 can be prevented from being etched and damaged in the preparation process, meanwhile, the first low-k dielectric layer 14 can be prevented from being contacted with an interconnection structure, and the performance of the device is improved.

In another embodiment, referring to fig. 18, the present invention further provides a semiconductor structure, which is substantially the same as the semiconductor structure in the previous embodiment (i.e., the embodiment shown in fig. 8), and the difference between the semiconductor structure of this embodiment and the semiconductor structure of the previous embodiment is: the semiconductor structure of this embodiment further includes, in addition to the semiconductor structure of the previous embodiment: a second low-k dielectric layer 21, the second low-k dielectric layer 21 being located on a surface of the second dielectric layer 21; a second pattern structure 18, wherein the second pattern structure 18 is located in the second low-k dielectric layer 21, penetrates through the second low-k dielectric layer 21 along the thickness direction, and the bottom of the second pattern structure 18 is in contact with the top of the first pattern structure 11; the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 is lower than the surface of the second pattern structure 18 away from the first pattern structure 11; a third dielectric layer 20, the third dielectric layer 20 being located between the second low-k dielectric layer 21 and the second pattern structure 18 and between the second low-k dielectric layer 21 and the second dielectric layer 15; and a fourth dielectric layer 22, wherein the fourth dielectric layer 22 is positioned on the surface of the second low-k dielectric layer 21. In addition, the semiconductor structure of this embodiment is different from the semiconductor structure of the previous embodiment in that: the first pattern structure 11 of the previous embodiment alone constitutes a sacrificial structure or an interconnect structure; in the present embodiment, the first pattern structure 11 and the second pattern structure 18 together form a sacrificial structure or an interconnect structure.

In one example, the second low-k dielectric layer 21 may include, but is not limited to, a carbon-doped silicon oxide layer (e.g., SiOCH), a fluorine-doped silicon oxide layer, a fluorocarbon layer, a polyimide layer, or the like; the material of the second low-k dielectric layer 21 may be the same as the material of the first low-k dielectric layer 14.

In one example, the third dielectric layer 20 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer; the fourth dielectric layer 22 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon carbide layer, a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxide layer and a silicon nitride layer; the material of the first dielectric layer 13, the material of the second dielectric layer 15, the material of the third dielectric layer 20, and the material of the fourth dielectric layer 22 may all be the same. The material of the first dielectric layer 13, the material of the second dielectric layer 15, the material of the third dielectric layer 20, and the material of the fourth dielectric layer 22 may be different from the material of the first low-k dielectric layer 14 and the material of the second low-k dielectric layer 21.

In one example, the material of the first graphic structure 11 is the same as the material of the second graphic structure 18; when the first pattern structure 11 and the second pattern structure 18 together form an interconnect structure, the material of the first pattern structure 11 and the material of the second pattern structure 18 may include aluminum, copper, doped polysilicon, and the like; when the first pattern structure 11 and the second pattern structure 18 together form a sacrificial structure, the material of the first pattern structure 11 and the material of the second pattern structure 18 may both include dielectric materials, such as: silicon oxide, silicon nitride, or silicon oxide and silicon nitride, and the like.

In one example, the thickness of the third dielectric layer 20 may be 1 nm to 10 nm, and the thickness of the fourth dielectric layer 22 may be 1 nm to 10 nm.

In one example, the width of the second pattern structure 18 may be greater than the width of the first pattern structure 11.

In one example, the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 is lower than the surface of the second pattern structure 18 away from the first low-k dielectric layer 14, as shown in fig. 18; preferably, the height difference between the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 and the surface of the second pattern structure 18 away from the first low-k dielectric layer 14 is 0.5 to 2 times the thickness of the third dielectric layer 20, that is, the height difference between the surface of the second low-k dielectric layer 21 far away from the first low-k dielectric layer 14 and the upper surface of the third dielectric layer 20 on the surface of the second pattern structure 18 far away from the first low-k dielectric layer 14 is 1.5 to 3 times the thickness of the third dielectric layer 20, and more preferably, in the present embodiment, the difference between the height of the second low-k dielectric layer 21 away from the surface of the first low-k dielectric layer 14 and the height of the second pattern structure 18 away from the surface of the first low-k dielectric layer 14 is 1 times the thickness of the third dielectric layer 20, that is, the height difference between the surface of the second low-k dielectric layer 21 away from the first low-k dielectric layer 14 and the upper surface of the third dielectric layer 20 on the surface of the second pattern structure 18 away from the first low-k dielectric layer 14 is 2 times the thickness of the third dielectric layer 20.

In the semiconductor structure of the embodiment, the first low-k dielectric layer 141 and the second low-k dielectric layer are used as the dielectric layers at the periphery of the first pattern structure 11 and the second pattern structure 18, so that the RC signal delay can be reduced; the first dielectric layer 13, the second dielectric layer 15, the third dielectric layer 20 and the fourth dielectric layer 22 coat the first low-k dielectric layer 14 and the second low-k dielectric layer 21, so that the side wall of the first low-k dielectric layer 14 and the side wall of the second low-k dielectric layer 21 can be prevented from being damaged in the preparation process, meanwhile, the first low-k dielectric layer 14 and the second low-k dielectric layer 21 can be prevented from being contacted with an interconnection structure, and the performance of the device is improved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate;

a first low-k dielectric layer located on the front side of the substrate;

a first dielectric layer between the first low-k dielectric layer and the first pattern structure and between the first low-k dielectric layer and the substrate;

2. The semiconductor structure of claim 1, wherein the first pattern structure is an interconnect structure; the height difference between the surface of the first low-k dielectric layer far away from the base body and the surface of the first pattern structure far away from the base body is 0.5-2 times of the thickness of the first dielectric layer.

3. The semiconductor structure of claim 1, further comprising:

a second low-k dielectric layer on a surface of the second dielectric layer;

the second graphic structure is positioned in the second low-k dielectric layer, penetrates through the second low-k dielectric layer along the thickness direction, and the bottom of the second graphic structure is in contact with the top of the first graphic structure; the surface of the second low-k dielectric layer, which is far away from the first low-k dielectric layer, is lower than the surface of the second pattern structure, which is far away from the first pattern structure;

a third dielectric layer between the second low-k dielectric layer and the second pattern structure and between the second low-k dielectric layer and the second dielectric layer;

4. The semiconductor structure of claim 3, wherein the first pattern structure and the second pattern structure together form an interconnect structure; the height difference between the surface of the first low-k dielectric layer, which is far away from the substrate, and the surface of the first pattern structure, which is far away from the substrate, is 0.5-2 times of the thickness of the first dielectric layer; the height difference between the surface of the second low-k dielectric layer far away from the first low-k dielectric layer and the surface of the second pattern structure far away from the first low-k dielectric layer is 0.5-2 times of the thickness of the third dielectric layer.