CN210325805U

CN210325805U - Edge termination device with reinforcement structure

Info

Publication number: CN210325805U
Application number: CN201921125041.8U
Authority: CN
Inventors: 何乐平; 孙倩
Original assignee: Alpha Power Solutions Ltd
Current assignee: Feicheng Semiconductor Shanghai Co ltd
Priority date: 2019-07-17
Filing date: 2019-07-17
Publication date: 2020-04-14
Anticipated expiration: 2029-07-17

Abstract

The utility model discloses an edge termination device with additional strengthening. The edge termination device includes a device region and an edge region. The device region is provided with a semiconductor device, and the edge region is provided to surround the device region. The reinforcing structure is disposed at the edge region and includes a passivation layer and an organic layer disposed on the passivation layer. The organic layer includes an organic material, the passivation layer has a recess, at least a portion of the organic material fills the recess, and a top plan view of the recess is wavy and forms a closed loop around the device region. According to the utility model discloses an edge termination can strengthen the joint strength who has organic layer and passivation layer, avoids droing of organic layer, has better mechanical stability and reliability.

Description

Edge termination device with reinforcement structure

Technical Field

The utility model relates to a semiconductor field, more specifically relates to edge termination device with additional strengthening.

Background

Semiconductor devices such as schottky diodes and metal oxide field effect transistors (MOSFETs) can withstand voltages as high as several hundred to several thousand volts. In such high electric fields, the insulation between the device and the environment is very important. Passivation techniques are commonly employed to shield the surface of semiconductor devices from electrical stress, mechanical stress, water, and other chemical attacks. For example, the organic material and the passivation layer together form a passivation structure, thereby improving the electrical and mechanical characteristics of the semiconductor device. However, during chip processing, for example, during dicing, organic materials are easily peeled, peeled or peeled off due to the presence of deformation, thereby affecting the stability and reliability of the device.

Disclosure of Invention

The utility model provides an edge termination device with additional strengthening to above-mentioned one or more technical problem among the solution prior art.

According to an aspect of the present invention, there is provided an edge termination device having a reinforcement structure. The edge termination device includes a device region and an edge region. The device region is provided with a semiconductor device, and the edge region is provided to surround the device region. The reinforcing structure is disposed at the edge region and includes a passivation layer and an organic layer disposed on the passivation layer. The organic layer includes an organic material, the passivation layer has a recess, at least a portion of the organic material fills the recess, and a top plan view of the recess is wavy and forms a closed loop around the device region.

Alternatively or additionally, the organic material comprises polyimide.

Alternatively or additionally, the passivation layer comprises plasma-enhanced tetraethyl orthosilicate, or plasma-enhanced nitride, or a combination of both.

Alternatively or additionally, the semiconductor device is selected from one or more of the following group: schottky diodes, bipolar transistors, insulated gate bipolar transistors, metal oxide field effect transistors, junction field effect transistors, semiconductor memory devices, semiconductor photovoltaic devices.

Alternatively or additionally, the recess comprises two or more recesses, whereby a top plan view of the recesses forms two or more closed loops around the device region.

According to another aspect of the present invention, there is provided an edge termination device with a reinforcement structure. The edge termination device includes a semiconductor layer having a semiconductor material, a field oxide layer, a passivation layer, and an organic layer including an organic material. A field oxide layer is disposed on at least a portion of the semiconductor layer. At least a portion of the passivation layer is disposed on the field oxide layer, and at least a portion of the passivation layer has a recess, the recess having a wave shape in a top plan view and forming a closed loop. At least a portion of the organic material of the organic layer fills the recess, forming a reinforcing structure with the passivation layer.

Alternatively or additionally, the field oxide layer comprises a silane based oxide or tetraethyl orthosilicate based oxide.

Alternatively or additionally, the semiconductor material is selected from one of the following groups: silicon carbide, silicon, germanium, silicon germanium, gallium nitride, gallium arsenide, and indium phosphide.

The edge termination device according to the present invention has many advantages. For example, the organic layer can be firmly cured with the passivation layer due to the presence of the reinforcing structure, and thus peeling or falling-off does not easily occur during subsequent processing. In addition, because the top plane view or the plane pattern of the concave part included in the reinforcing structure is wave-shaped, and has no sharp corner, the concave part is not easy to peel off or fall off, and therefore, the mechanical stability, the reliability and the service life of the semiconductor device in the subsequent processing (such as slicing packaging) process can be greatly improved or improved.

Other embodiments and further technical effects of the invention will be described in detail below.

Drawings

One or more embodiments are illustrated in corresponding figures and are not meant to be limiting. For convenience, the same or similar elements are designated by the same or similar reference numerals in the drawings, which are not to scale unless otherwise specified, and wherein:

fig. 1a shows a schematic structural view of an edge termination device with a reinforcing structure according to some embodiments of the present invention;

FIG. 1b shows a top plan view of the edge termination device according to FIG. 1a with the organic layer removed;

fig. 2-4 illustrate methods of manufacturing edge termination devices with reinforcement structures according to further embodiments of the present invention.

Detailed Description

To facilitate an understanding of the present invention, a number of exemplary embodiments will be described below in conjunction with the associated drawings. It is to be understood by those skilled in the art that the present examples are for illustrative purposes only and are not intended to limit the present invention in any way.

In accordance with an aspect of the present invention, fig. 1a and 1b illustrate a schematic diagram of an edge termination device with a reinforced structure and a top plan view with an organic layer removed, respectively. Fig. 1a is, for example, a cross-sectional view along line a-a of fig. 1b (fig. 1a has organic layers compared to fig. 1 b). For the sake of simplicity, fig. 1a shows only a part of the cross-sectional view.

As shown in fig. 1a and 1b, the edge termination device includes a device region 100 and an edge region 10. The two are separated by a dashed line for clarity. The device region 100 is provided with a semiconductor device such as one or more of a schottky diode, a bipolar transistor, an insulated gate bipolar transistor, a metal oxide field effect transistor, a junction field effect transistor, a semiconductor memory device, and a semiconductor photovoltaic device. The edge region 10 is disposed to surround the device region 100. The edge region 10 can, for example, improve the distribution of the electric field at the edge or end of the device when reverse biased, increasing the breakdown voltage of the device, while providing protection to the device region 100.

The device region 100 and the edge region 10 are disposed on the semiconductor layer 110. The semiconductor layer 110 includes a semiconductor material such as silicon carbide, silicon, germanium, silicon germanium, gallium nitride, gallium arsenide, indium phosphide, or the like. The semiconductor layer 110 may include a semiconductor substrate, and one or more epitaxial layers, drift layers, etc., disposed on the substrate. Wherein each layer may have an appropriate thickness, doping concentration, doping type. For example, in some embodiments, the drift layer surface forms a schottky device with the metal thereon.

A metal layer 120 is formed on a portion of the surface of the semiconductor layer 110. The metal layer 120 may be in contact with the surface of the semiconductor layer 110 to form a schottky contact, a low resistance contact, or an ohmic contact, as required. The metal layer 120 may also be in contact with the gate insulating film to form a gate electrode. The metal layer 120 may be formed of a suitable metal, such as aluminum (Al), nickel (Ni), titanium (Ti), silver (Ag), platinum (Pt), gold (Au), molybdenum (Mo), or a combination of two or more thereof.

A field oxide layer 12 is disposed on at least a portion of the semiconductor layer 110. At least a portion of the field oxide layer 12 is interposed between the metal layer 120 and the semiconductor layer 110. The field oxide layer 12 includes, for example, a silane (SiH4) -based oxide or a Tetraethylorthosilicate (TEOS) -based oxide, such as plasma-enhanced tetraethylorthosilicate. A passivation layer 14 is disposed on the field oxide layer 12. The passivation layer 14 may be used to reduce electrical stress, mechanical stress, moisture or chemical corrosion of the metal surface of the semiconductor device, etc. The passivation layer 14 may comprise, for example, plasma-enhanced tetraethyl orthosilicate, or plasma-enhanced nitride, or a combination of both.

At least a portion of the passivation layer 14 has an opening or recess 18. An organic layer 16 is disposed on the passivation layer 14. The organic layer 16 includes an organic material, such as polyimide. At least a portion of the organic material fills the recess 18.

The organic layer 16 may, together with the passivation layer 14, achieve better electrical and mechanical properties. Taking polyimide as an example, polyimide is a typical passivation material because it has the characteristics of being lightweight, flexible, heat resistant, and chemical resistant, and is suitable for protecting semiconductor devices, such as silicon carbide power devices.

Due to the presence of the recesses 18, the organic layer 16 penetrates into the underlying passivation layer 14 and solidifies together with the passivation layer 14 to form a reinforcing structure, thereby alleviating or preventing peeling or detachment of the organic layer 16 during processing (e.g., dicing, packaging) of the semiconductor device.

Furthermore, the present inventors have recognized that peeling of the organic layer in a subsequent process, such as dicing a chip, may be attributed to sharp corners, and broken lines are generally linear. The utility model provides a design can solve this problem. As shown in fig. 1b, the top plan view or plan pattern of the depressions 18 is wavy and forms a closed loop or closed circuit. The wavy design does not include sharp corners and longer straight lines (in the shorter range, the curve can be approximately regarded as a straight line, i.e., a shorter straight line) as compared to a straight line shape, and the occurrence of cracking or chipping of the organic layer can be reduced or avoided. Furthermore, the wavy design also gives the organic layer additional elasticity or resilience and is therefore more difficult to break. Therefore, according to the utility model discloses an edge termination's organic layer is stronger more firm with the associativity of passivation layer, has higher mechanical stability in follow-up manufacturing process, can bear bigger stress or other external forces. Edge termination devices having such reinforced structural designs may also be applied in a wider variety of environments and have a longer useful life.

In fig. 1b, the wavy closed loop can be designed according to actual needs. For example, the wave shape can be arranged in a periodic regular wave shape, and can also be designed into a non-periodic wave shape. Other types of undulations may also be designed, for example, at least a portion having a periodic undulation.

In accordance with another aspect of the present invention, fig. 2-4 illustrate a method of manufacturing an edge termination device having a reinforcement structure. The method of fig. 2-4 may be used, for example, to manufacture the edge termination device of fig. 1a-1 b.

The edge termination device has a device region 200 and an edge region 20. To fabricate the edge termination device, a semiconductor layer 210, such as a silicon carbide semiconductor layer, is provided, as illustrated in fig. 2. The semiconductor layer 210 includes, for example, a silicon carbide substrate, an epitaxial layer, and a drift layer on the epitaxial layer. The semiconductor layer 210 may be used to fabricate a semiconductor device. Examples of semiconductor devices are schottky diodes, bipolar transistors, insulated gate bipolar transistors, metal oxide field effect transistors, junction field effect transistors, semiconductor memory devices, semiconductor photovoltaic devices, and integrated circuits incorporating one or more of these devices. Semiconductor devices may be fabricated by suitable semiconductor processes including, for example and without limitation, one or more of epitaxial growth, ion implantation, photolithography, etching, metal deposition, interconnection, passivation, and the like.

A field oxide layer 22 is formed on a portion of the semiconductor layer 210. The field oxide layer 22 is disposed at the edge region 20. The field oxide layer 22 may be formed of a suitable oxide, such as a silane based oxide or tetraethyl orthosilicate based oxide. The oxide as the field oxide layer 22 may be formed by a suitable process including, but not limited to, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, and the like. The field oxide layer 22 may be formed, for example, by depositing plasma enhanced tetraethyl orthosilicate. In some embodiments, the thickness of the field oxide layer 22 is in the range of 1 micrometer (um) to 2 um.

A metal layer 220 is formed. The metal layer 220 is in contact with the field oxide layer 22 such that at least a portion of the field oxide layer 22 is interposed between the semiconductor layer 210 and the metal layer 220 in a direction perpendicular to the surface of the semiconductor layer 210. The metal layer 220 may be made of, for example, a metal material including, for example, aluminum (Al), nickel (Ni), titanium (Ti), silver (Ag), platinum (Pt), gold (Au), molybdenum (Mo), or a multi-layered metal layer formed of two or more of the above metals. In some embodiments, metal layer 220 is aluminum with a thickness in the range of 1um to 4 um.

A passivation layer 24 is provided. A passivation layer 24 is disposed on the field oxide layer 22 and a portion of the metal layer 220. For example, in some embodiments, the passivation layer 24 is formed by depositing plasma enhanced tetraethyl orthosilicate, the thickness of the passivation layer 24 being in the range of 1um to 2 um.

As shown in fig. 3, the passivation layer 24 is patterned, and the recess 28 is etched and formed. Illustratively, the passivation layer 24 is dry etched, and during the etching process, the reactive ions 29 react with the plasma-enhanced tetraethyl orthosilicate of the passivation layer 24 for a fixed time according to the process recipe, thereby removing the plasma-enhanced tetraethyl orthosilicate of a specific thickness in the passivation layer 24. In some embodiments, the recess 28 is formed by wet etching.

As shown in fig. 4, an organic layer 26 using polyimide is coated on the surface of the passivation layer 300, and the polyimide fills the recess 28. As an example, the thickness of the organic layer 26 is 4um to 8 um. The organic layer 28 may be subsequently patterned, etc.

The above embodiments are only for illustrating the idea of the present invention, and not for limiting the present invention. It will be further appreciated by those of ordinary skill in the art that for purposes of clarity of illustration, elements (e.g., elements, regions, layers, etc.) in the figures have not necessarily been drawn to scale. In addition, each element in the drawings is not necessarily the exact shape thereof.

In the above embodiments, the passivation layers 14, 24 are shown as a single layer or layer only, as will be appreciated by those skilled in the art, for illustrative purposes only. In some embodiments, the passivation layer may include two or more layers. For example, in some embodiments, the passivation layer includes a first passivation layer and a second passivation layer disposed thereon. In one embodiment, the first passivation layer is formed from plasma enhanced tetraethyl orthosilicate to a thickness in a range of 1um to 2 um. The second passivation layer is formed of plasma enhanced nitride and has a thickness in the range of 0.5um to 2 um.

The first passivation layer has a first recess and the second passivation layer has a second recess. The first and second recesses may be formed by a suitable method. For example, the second recess portion may be formed by dry etching, and the first recess portion may be formed by wet etching. The connection between the first depressed part and the second depressed part can be step transition or curved surface transition. In some embodiments, the maximum width of the first recess may be greater than the maximum width of the second recess along a direction parallel to the plane of the semiconductor layer, so that the organic material (e.g., polyimide) can be more firmly cured together with the passivation layer to form a desired reinforcing structure after filling the first and second recesses.

In the above embodiments, for example, in fig. 1b, only one closed wavy closed loop is shown, which is only an illustration, and it will be understood by those skilled in the art that, in some embodiments, the number of the wavy closed loops may be two or more, and the distance between two adjacent closed loops may be set according to actual situations. In this case, each passivation layer has, for example in the sectional view shown in fig. 1a, two or more recesses in the edge region.

Furthermore, it will be understood by those skilled in the art that the above embodiments are intended to illustrate the invention in different respects, not in isolation; rather, those skilled in the art can combine the different embodiments appropriately according to the above examples to obtain other technical solution examples.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Embodiments of the present invention are illustrated in non-limiting examples. Variations that may occur to those skilled in the art upon consideration of the above-disclosed embodiments are intended to fall within the scope of the present invention.

Claims

1. An edge termination device having a reinforcement structure, the edge termination device comprising:

a device region provided with a semiconductor device; and

an edge region disposed to surround the device region,

wherein the reinforcement structure is disposed at the edge region, the reinforcement structure comprising a passivation layer and an organic layer disposed on the passivation layer, the organic layer comprising an organic material, the passivation layer having a recess, at least a portion of the organic material filling the recess, the recess having a wave shape in a top plan view and forming a closed loop around the device region.

2. The edge termination device of claim 1, wherein the organic material comprises polyimide.

3. The edge termination of claim 1 or 2, wherein the passivation layer comprises plasma-enhanced tetraethyl orthosilicate, or plasma-enhanced nitride, or a combination of both.

4. The edge termination apparatus of claim 1 or 2, wherein the semiconductor device is selected from one or more of the group consisting of: schottky diodes, bipolar transistors, insulated gate bipolar transistors, metal oxide field effect transistors, junction field effect transistors, semiconductor memory devices, semiconductor photovoltaic devices.

5. The edge termination device of claim 1 or 2, wherein the recess comprises two or more recesses such that a top plan view of a recess forms two or more closed loops around the device region.

6. An edge termination device having a reinforcement structure, the edge termination device comprising:

a semiconductor layer comprising a semiconductor material;

a field oxide layer disposed on at least a portion of the semiconductor layer;

a passivation layer, at least a portion of which is disposed on the field oxide layer, the at least a portion of which has a recess, a top plan view of which is wavy and forms a closed loop; and

an organic layer comprising an organic material, at least a portion of the organic material of the organic layer filling the recess to form a reinforcing structure with the passivation layer.

7. The edge termination device of claim 6, wherein the field oxide layer comprises a silane based oxide or a tetraethyl orthosilicate based oxide.

8. The edge termination device of claim 6 or 7, wherein the semiconductor material is selected from one of the group consisting of: silicon carbide, silicon, germanium, silicon germanium, gallium nitride, gallium arsenide, and indium phosphide.