CN110838471A - Chip edge structure and manufacturing method - Google Patents
Chip edge structure and manufacturing method Download PDFInfo
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- CN110838471A CN110838471A CN201810935804.9A CN201810935804A CN110838471A CN 110838471 A CN110838471 A CN 110838471A CN 201810935804 A CN201810935804 A CN 201810935804A CN 110838471 A CN110838471 A CN 110838471A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to the technical field of semiconductor devices, in particular to a chip edge structure and a manufacturing method thereof. The chip edge structure comprises an edge main body structure layer, a passivation layer and an organic film layer, wherein the passivation layer is arranged on the surface of the edge main body structure layer along a preset direction and is provided with at least one recessed area; the organic film layer is arranged on the surface of the passivation layer along a preset direction and fills each concave area. Because the organic film layer fills the depressed area of the passivation layer, the organic film layer can be firmly solidified with the passivation layer, and therefore, the passivation layer is not easy to peel or fall off during the process.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a chip edge structure and a manufacturing method thereof.
Background
Power devices such as schottky diodes can operate at voltages of hundreds of volts or even thousands of volts, and the degree of insulation from the environment is an important design factor when the power devices operate at such high electric fields.
In order to have excellent insulating property, one or more passivation layers are deposited on the power device in the conventional process, and the passivation layers can be used for reducing the electrical stress, the mechanical stress, the water vapor or the chemical corrosion of the metal surface of the power device.
In the process of implementing the invention, the inventor finds that the traditional technology has at least the following problems: although the power device has good electrical characteristics, the passivation layer of the power device may generate additional stress with the underlying material in other process steps, such as back grinding or dicing, which may cause the passivation layer to be easily peeled and even fall off. And these peeling phenomena of the passivation layer often occur at the corners of the power device chip.
Disclosure of Invention
An object of an embodiment of the present invention is to provide a chip edge structure and a manufacturing method thereof, in which the passivation layer has good firmness.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
in a first aspect, an embodiment of the present invention provides a chip edge structure, including:
an edge body structure layer;
the passivation layer is arranged on the surface of the edge main body structure layer along a preset direction and is provided with at least one recessed area;
and the organic film layer is arranged on the surface of the passivation layer along the preset direction and fills each concave area.
In a second aspect, embodiments of the present invention provide a junction termination extension structure, including any one of the chip edge structures.
In a third aspect, an embodiment of the present invention provides a power device, including any one of the chip edge structures.
In a fourth aspect, an embodiment of the present invention provides an electronic device, including the power device.
In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a chip edge structure, where the method includes:
providing an edge body structure layer;
depositing a passivation layer on the surface of the edge main body structure layer;
patterning the passivation layer to form at least one recess region;
and forming an organic film layer on the surface of the passivation layer, wherein the organic film layer fills each depression region.
In the chip edge structure and the manufacturing method provided by the embodiments of the present invention, the passivation layer is stacked on the surface of the edge main body structure layer along the predetermined direction, and the surface of the passivation layer is provided with at least one recessed region, and the organic film layer is stacked on the surface of the passivation layer along the predetermined direction and fills each of the recessed regions. Because the organic film layer fills the depressed area of the passivation layer, the organic film layer can be firmly solidified with the passivation layer, and therefore, the passivation layer is not easy to peel or fall off during the process.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of an edge structure of a chip according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of an edge body structure layer after forming a passivation layer according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a first embodiment of the present invention for forming a recess region by dry etching a passivation layer;
FIG. 4 is a cross-sectional view of an organic film filling a recessed area according to a first embodiment of the present invention;
FIG. 5 is a cross-sectional view of an edge body structure layer after formation of a passivation layer according to a second embodiment of the present invention;
fig. 6 is a schematic view of a first recess portion for forming a recess region by dry-etching a passivation layer according to a second embodiment of the present invention;
FIG. 7 is a schematic view of a second recess portion formed by wet etching an interlayer dielectric to form a recess region according to a second embodiment of the present invention;
FIG. 8 is a cross-sectional view of an organic film filling a recessed area according to a second embodiment of the present invention;
FIG. 9 is a cross-sectional view of an edge body structure layer after formation of a passivation layer according to a third embodiment of the present invention;
fig. 10 is a schematic view of an initial shape of a recess region formed by dry-etching a passivation layer and an interlayer dielectric provided by the third embodiment of the present invention;
FIG. 11 is a schematic illustration of the final shape of a recess formed by wet etching an interlayer dielectric as provided by the third embodiment of the present invention;
FIG. 12 is a cross-sectional view of a third embodiment of the present invention providing an organic film filling a recessed area;
FIG. 13 is a cross-sectional view of an edge body structure layer after forming a first passivation layer and a second passivation layer according to a fourth embodiment of the invention;
fig. 14 is a schematic view of a first recess portion provided in the fourth embodiment of the present invention for forming a recess region by dry-etching a second passivation layer;
fig. 15 is a diagram illustrating a second recess portion formed by wet etching the first passivation layer to form a recess region according to a fourth embodiment of the present invention;
FIG. 16 is a cross-sectional view of a fourth embodiment of the present invention providing an organic film filling a recessed area;
fig. 17 is a schematic view of an initial shape of a recess region formed by dry etching the second passivation layer and the first passivation layer according to the fifth embodiment of the present invention;
fig. 18 is a schematic view illustrating a final shape of a recess region formed by wet etching the first passivation layer and the interlayer dielectric according to a fifth embodiment of the present invention;
FIG. 19 is a cross-sectional view of an organic film filling a recessed area according to a fifth embodiment of the present invention;
FIG. 20 is a schematic view of a planar pattern of recessed areas in the form of stripes according to an embodiment of the present invention;
FIG. 21 is a schematic diagram of a plan view of a recessed area in phantom according to an embodiment of the present invention;
FIG. 22 is a schematic diagram of a planar pattern of recessed areas in a lattice shape according to an embodiment of the present invention;
FIG. 23 is a flow chart illustrating a method for fabricating a chip edge structure according to an embodiment of the invention;
FIG. 24 is a schematic flow chart of the second embodiment of S53 of FIG. 23;
FIG. 25 is a schematic flow chart of the third embodiment of S53 of FIG. 23;
fig. 26 is a schematic flow chart of S52 in fig. 23;
FIG. 27 is a schematic flow chart of a fourth embodiment of S53 of FIG. 23;
fig. 28 is a schematic flow chart of the fifth embodiment of S53 in fig. 23.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Although embodiments of the present invention may use terms such as first, second, etc. to refer to various elements, it should be understood that these elements should not be limited by the above terms. The above terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. Also, the use of first, second, etc. to refer to the number of elements includes both the singular and the plural, unless the context clearly dictates otherwise.
The terms "comprises," "comprising," "including," and/or "comprising," when used in connection with embodiments of the present invention, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments of the present invention use the term "substrate" to include any semiconductor structure having a semiconductor surface, and in some embodiments, the substrate comprises a Silicon carbide (SiC) substrate or a Silicon (Si) substrate or a gallium nitride (GaN) substrate, and in other embodiments, the substrate may further comprise Silicon germanium (SiGe), germanium (Ge), or gallium arsenide (GaAs).
Embodiments of the present invention are directed to the term "horizontal" in an effort to describe a surface substantially parallel to a semiconductor substrate, e.g., a silicon carbide substrate.
The term "vertical" with respect to embodiments of the present invention is intended to describe an orientation substantially parallel to a normal direction of a surface of a semiconductor substrate.
As will be appreciated by those skilled in the art, embodiments of the present invention described below relate to one or more interlayer materials, the positional relationship between layers being expressed using terms such as "laminating" or "forming" or "applying" or "disposing," for example: any terms such as "stacked" or "formed" or "applied" may cover all manner, kinds and techniques of "stacked". For example, sputtering, plating, molding, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, Hybrid Physical-Chemical Vapor Deposition (HPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and the like.
The chip edge structure provided by the embodiment of the invention can be formed in a Junction Termination Extension (JTE) structure, and the junction termination extension structure can be a single-region JTE or a multi-region JTE. It is understood that the chip edge structure can also be fabricated into power devices of various types and specifications by combining various types of active regions and metal electrodes, for example, the power devices include Schottky Barrier Diode (SBD), JBS Diode, bipolar insulated gate field effect transistor (IGBT), metal oxide insulated gate field effect transistor (MOS), thyristor (SCR), and the like.
It will also be appreciated that: the Power device may be combined with other discrete components (such as a Power device, a capacitor, an inductor, a processor, etc.) to form a functional circuit having a specific electrical function, for example, an Intelligent Power Module (IPM) formed by an IGBT transistor and other discrete components, a half-wave rectifier bridge or a full-wave rectifier bridge formed by a plurality of diodes, a half-bridge driver circuit or a full-bridge driver circuit formed by a plurality of MOS transistors, etc.
However, it can be further understood that: the functional circuit based on power device constitutes can also combine other functional circuit or power structure or physical structure to constitute the electronic equipment that can realize specific function, for example, intelligent power module combines the engine, in order to realize unmanned aerial vehicle's power take off.
The chip edge structure provided by the embodiment of the present invention may be applied to any suitable industry field, and the examples provided by the embodiment of the present invention are not intended to limit the scope of the present invention.
Various embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. As will be appreciated by those skilled in the art: the accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present invention and, together with the description, further serve to explain the principles of the invention: variations from the shapes of the illustrations as a result of, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a recessed region shown as dry etched or wet etched will have different binary variations depending on the different degrees of reduction formed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention. Embodiments of the present invention are described with reference to specific polarity conductivity types for various layers and regions. However, as will be appreciated by those skilled in the art, the polarity of the layers and regions may be reversed to provide devices of opposite polarity.
Referring to fig. 1, a chip edge structure 100 includes: an edge body structure layer 200, a passivation layer 300 and an organic film layer 400.
The edge body structure layer 200 is a basic structure layer for implementing a semiconductor function of the power device.
The passivation layer 300 is disposed on the surface 20 of the edge body structure layer 200 along a predetermined direction, and the passivation layer 300 has a plurality of recessed regions 31, wherein the number of the recessed regions 31 may be one or more. In the present embodiment, it can be understood by those skilled in the art that: for the purpose of the invention of the embodiment of the present invention, the predetermined direction is a reasonable direction for disposing the passivation layer 300 on the surface 20 of the edge body structure layer 200 to realize the electrical function of the power device, for example, a direction substantially parallel to the surface 20 of the edge body structure layer 200 is a horizontal direction, and the predetermined direction is a direction of a normal line substantially perpendicular to the horizontal direction, and the passivation layer 300 is disposed on the surface 20 of the edge body structure layer 200 in a vertical direction by selecting a corresponding disposing method.
In some embodiments, the number of passivation layers 300 may be a single layer or multiple layers. The passivation layer 300 is made of a passivation material, for example, the passivation layer 300 is made of Plasma enhanced tetraethyl orthosilicate (PETEOS) or Plasma enhanced nitride (PENit).
The organic film layer 400 is disposed on the surface 32 of the passivation layer 300 in a predetermined direction, and the organic film layer 400 fills each of the recess regions 31. For example, in connection with the above example, the organic film 400 is disposed on the surface 32 of the passivation layer 300 in a vertical direction, and when the organic film 400 is disposed, the organic film 400 flows into each of the recess regions 31, and thus, the organic film 400 fills each of the recess regions 31.
After the organic film 400 is filled in each recess 31, the organic film 400 can be firmly cured with the passivation layer 300, and thus, the passivation layer 300 is not easily peeled or peeled off during the process.
In some embodiments, the organic film 400 may be a Polyimide (Polyimide) layer, or other suitable organic layers. In general, polyimide has characteristics of light weight, flexibility, heat resistance, chemical resistance, and the like, and is suitable for protecting silicon carbide power devices. Polyimides are typically used with plasma enhanced chemical vapor deposition materials to form multiple passivation layers, for example, polyimides are used with plasma enhanced tetraethyl orthosilicate or plasma enhanced nitride to obtain more desirable electrical and mechanical properties.
In some embodiments, referring to fig. 2, the edge body structure layer 200 includes: substrate 21(Substrate), epitaxial layer 22 (epitoxy), Doped junction region 23(Doped junction region), interlayer dielectric 24 (ILD), and Top metal layer 25(Top metal layer).
The substrate 21 may be fabricated from various types of semiconductor materials, such as a silicon carbide substrate. As an example, the substrate 21 may be formed of silicon carbide of a first conductivity type (e.g., N-type or P-type). The substrate 21 is highly doped silicon carbide with a thickness of 350um and a resistivity in the range of 0.02 Ω · cm to 0.03 Ω · cm. The semiconductor type of the substrate is determined by majority carriers in the semiconductor, if the majority carriers of the first conduction type are holes, the first conduction type is P type, the heavily doped first conduction type is P + type, and the lightly doped first conduction type is P-type; if the majority carriers of the first conductivity type are electrons, the first conductivity type is N-type, the heavily doped first conductivity type is N + type, and the lightly doped first conductivity type is N-type. If the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.
The epitaxial layer 22 is disposed on the surface of the substrate 21 in a predetermined direction. As an example, epitaxial layer 22 is silicon carbide of a first conductivity type (e.g., N-type or P-type) grown on substrate 21. Epitaxial layer 22 is lightly doped silicon carbide with a thickness in the range of 5um to 30um and a doping concentration of 1e15cm-3To 2e16cm-3Within the range of (1).
The doping junction region 23 is disposed in a surface region of the epitaxial layer 22 and extends from a surface of the epitaxial layer 22 toward the substrate 21, for example, the doping junction region 23 is doped on a portion of the surface of the epitaxial layer 22 by ion implantation and diffusion in a predetermined direction. As an example, the doped junction region 23 is of a second conductivity type (e.g., P-type or N-type) having a higher doping concentration than the epitaxial layer 22. The junction depth of the doped junction region 23 is 0.3um to 1.2um, and the doping concentration is 1e18cm-3To 1e20cm-3Within the range of (1).
An interlayer dielectric 24 is disposed on a portion of the surface of the epitaxial layer 22 in a predetermined direction, and the interlayer dielectric 24 is in contact with the doped junction region 23. An interlayer dielectric 24 is deposited in the surface of epitaxial layer 22 and patterned to expose contact regions 241. The interlayer dielectric 24 may be formed of a suitable oxide, such as a silane (SiH4) -based oxide or a Tetraethylorthosilicate (TEOS) -based oxide. The oxide as the interlayer dielectric 24 may be formed by a suitable process including, but not limited to, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, and the like.
In some embodiments, the interlayer dielectric 24 is formed by depositing plasma enhanced tetraethylorthosilicate, the thickness of the interlayer dielectric 24 being in the range of 1um to 2 um.
The top metal layer 25 is disposed on a surface of the doped junction region 23 in a preset direction, and the top metal layer 25 is in contact with the interlayer dielectric 24 such that at least a portion of the interlayer dielectric 24 is interposed between the doped junction region 23 and the top metal layer 25 in the preset direction. The top metal layer 25 is a metal layer, and for example, the metal material used for the top metal layer 25 includes aluminum (Al), titanium (Ti), nickel (Ni), or may be a multi-layer metal layer formed of two or more of the above metals. In some embodiments, the top metal layer 25 is aluminum with a thickness in the range of 1um to 4 um.
Fig. 2 also shows a cutting lane 26(Scribe line).
The passivation layer 300 is disposed on the surfaces of the interlayer dielectric 24 and the top metal layer 25 in a predetermined direction. For example, in some embodiments, a single layer of the passivation layer 300 is formed by depositing plasma enhanced tetraethyl orthosilicate, the thickness of the passivation layer 300 being in the range of 1um to 2 um. In other embodiments, a single layer passivation layer 300 of plasma enhanced nitride may also be deposited on the surface of the single layer passivation layer 300 of plasma enhanced tetraethyl orthosilicate, to which point the bilayer passivation layer 300 has been formed. It is understood that a person skilled in the art can deposit a multi-layered passivation layer 300 according to the teachings of the present invention, in combination with business requirements, without limiting the examples of single or double layered passivation layers 300 shown above or below.
Referring to fig. 3, the passivation layer 300 is patterned, etched and formed into recessed regions 31. in some embodiments, the recessed regions 31 may also be referred to as Anchor zones (Anchor zones). As an example, the single passivation layer 300 is formed by dry etching (Dryetch), and during the etching process, the reactive ions 33 react with the plasma-enhanced tetraethyl orthosilicate of the passivation layer 300 for a fixed time according to the process recipe, so as to remove the plasma-enhanced tetraethyl orthosilicate of a specific thickness in the passivation layer 300.
Referring to fig. 4, an organic film 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recess 31. As an example, the thickness of the organic film layer 400 is 4um to 8 um.
Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100.
The difference from the above embodiments is that, in some embodiments, the recess region 31 is formed on the passivation layer 300 and the interlayer dielectric 24. Each recessed region 31 includes a first recessed portion 311 and a second recessed portion 312, the first recessed portion 311 and the second recessed portion 312 are communicated, and the maximum width of the second recessed portion 312 is greater than the maximum width of the first recessed portion 311 in a direction perpendicular to the predetermined direction, that is, in a horizontal direction substantially parallel to the surface 21 of the edge body structure layer 200.
Referring to fig. 5, a passivation layer 300 is formed by depositing a plasma enhanced nitride on the surfaces of the interlayer dielectric 24 and the top metal layer 25 along a predetermined direction, where the thickness of the passivation layer 300 is in the range of 0.5um to 2 um.
Referring to fig. 6, the passivation layer 300 is patterned by dry etching to form a first recess 311, and during the dry etching, the reactive ions 33 react with the plasma enhanced nitride of the passivation layer 300 at a fixed time according to the process recipe, thereby removing the plasma enhanced nitride of a specific thickness from the passivation layer 300 and stopping at the interlayer dielectric 24.
Referring to fig. 7, the interlayer dielectric 24 is etched to form a second recess 312. As an example, the interlayer dielectric 24 is patterned by Wet etching (Wet etch) to form the second recess 312. The wet etch process uses hydrofluoric acid as a reactant, and during the wet etch process, hydrofluoric acid 34 removes the plasma enhanced tetraethylorthosilicate in a specific thickness of the interlayer dielectric 24 isotropically at a fixed time specified by the process recipe. Due to the high selectivity between plasma enhanced tetraethyl orthosilicate and plasma enhanced nitride under the wet etching method, the shape of the passivation layer 300 is not changed.
Referring to fig. 7 again, the first recess 311 is located on the passivation layer 300, and the second recess 312 is in contact with the interlayer dielectric 24, for example, the surface of the interlayer dielectric 24 may serve as the bottom of the second recess 312. In some embodiments, the second recess 312 may also extend into the interlayer dielectric 24.
Referring to fig. 8, an organic film 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recess 31. As an example, the thickness of the organic film layer 400 is 4um to 8 um.
Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100.
The difference between the above embodiments is that in some embodiments, the initial shape of the recess 31 may be formed on the passivation layer 300 and the interlayer dielectric 24, and then the final shape of the recess 31 is formed.
Referring to fig. 9, a passivation layer 300 is formed by depositing a plasma enhanced nitride on the surfaces of the interlayer dielectric 24 and the top metal layer 25 along a predetermined direction, wherein the thickness of the passivation layer 300 is in the range of 0.5um to 2um, and then patterning the passivation layer 300 by a photolithography process and a reactive ion etching process.
Referring to fig. 10, the passivation layer 300 and the interlayer dielectric 24 are patterned by dry etching to form an initial shape of the recess 31. As an example, during the dry etching process, the reactive ions 33 react with the plasma enhanced nitride of the passivation layer 300 and the plasma enhanced tetraethyl orthosilicate of the interlayer dielectric 24 for a fixed time as dictated by the process recipe, thereby removing the plasma enhanced nitride of the passivation layer 300 and the plasma enhanced tetraethyl orthosilicate of the interlayer dielectric 24.
Referring to fig. 11, interlayer dielectric 24 is patterned by wet etching to form the final shape of recess 31. As an example, during the wet etch, hydrofluoric acid 34 is used for a fixed time as dictated by the process recipe to isotropically remove plasma enhanced tetraethylorthosilicate from a particular thickness in the interlayer dielectric 24. Due to the high selectivity between plasma enhanced tetraethyl orthosilicate and plasma enhanced nitride under the wet etching method, the shape of the passivation layer 300 is not changed.
Referring to fig. 12, an organic film 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recess 31. As an example, the thickness of the organic film layer 400 is 4um to 8 um.
Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100.
The difference from the above embodiments is that when the number of passivation layers is 2 or more, the formation method of the recess 31 is different.
Referring to fig. 13, the passivation layer 300 includes: the passivation layer 301 includes a first passivation layer 301 and a second passivation layer 302, wherein the second passivation layer 302 has a first recess 311, and the first passivation layer 301 has a second recess 312.
The first passivation layer 301 is disposed on the surface of the edge body structure layer 200 in a predetermined direction. As an example, the first passivation layer 301 is formed by depositing plasma enhanced tetraethyl orthosilicate on the surfaces of the interlayer dielectric 24 and the top metal layer 25 in a predetermined direction, the thickness of the first passivation layer 301 being in the range of 1um to 2 um.
The second passivation layer 302 is disposed on a surface of the first passivation layer 301 in a preset direction. As an example, the second passivation layer 302 is formed by depositing a plasma enhanced nitride on the surface of the first passivation layer 301 in a predetermined direction. The thickness of the second passivation layer 302 ranges from 0.5um to 2 um. The first passivation layer 301 and the second passivation layer 302 are then patterned by photolithography and reactive ion etching.
Referring to fig. 14, the second passivation layer 302 is patterned by dry etching to form a first recess 311. As an example, during the dry etching process, the reactive ions 33 react with the plasma enhanced nitride of the second passivation layer 302 at a fixed time as prescribed by the process recipe, thereby removing the plasma enhanced nitride of the second passivation layer 302 and stopping at the first passivation layer 301.
Referring to fig. 15, the first passivation layer 301 is patterned by wet etching to form a second recess 312. As an example, in the wet etching process, hydrofluoric acid 34 is fixed for a time as specified by the process recipe to isotropically remove plasma enhanced tetraethyl orthosilicate in a particular thickness in the first passivation layer 301. Due to the high selectivity between plasma enhanced tetraethyl orthosilicate and plasma enhanced nitride under the wet etching method, the shape of the second passivation layer 302 is not changed. The second recess 312 extends into the interlayer dielectric 24.
Referring to fig. 16, an organic film 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recess 31. As an example, the thickness of the organic film layer 400 is 4um to 8 um. The difference from the above embodiments is that after filling the second recess 312 with polyimide, the polyimide can firmly cure the first passivation layer 301, the second passivation layer 302, and the interlayer dielectric 24.
Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100.
The difference between the above embodiments is that the initial shape of the recess 31 can be formed on the second passivation layer 302 and the first passivation layer 301, and then the final shape of the recess 31 is formed.
The processes for forming the first passivation layer 301 and the second passivation layer 302 can refer to the above embodiments, and are not described herein again.
Referring to fig. 17, the second passivation layer 302 and the first passivation layer 301 are patterned by dry etching to form an initial shape of the recess 31. As an example, in the dry etching process, the reactive ions 33 react with the plasma-enhanced nitride of the second passivation layer 302 and the plasma-enhanced tetraethyl orthosilicate of the first passivation layer 301 for a fixed time as prescribed by the process recipe, thereby removing the plasma-enhanced nitride of the second passivation layer 302 and the plasma-enhanced tetraethyl orthosilicate of the first passivation layer 301 to form the initial shape of the recess region 31. During dry etching, the reactive ions 33 may etch a part of the thickness of the first passivation layer 301, and the rest of the thickness of the first passivation layer 301 is etched by wet etching; the reactive ions 33 may also etch through the entire thickness of the first passivation layer 301; the reactive ions 33 may continue to etch a portion of the thickness of the interlayer dielectric 24 even after the first passivation layer 301 is etched.
Referring to fig. 18, the first passivation layer 301 is patterned by wet etching to form the final shape of the recess 31. As an example, in the wet etching process, the hydrofluoric acid 34 is fixed for a time as specified by the process recipe to isotropically remove plasma enhanced tetraethyl orthosilicate in a specific thickness of the first passivation layer 301 and plasma enhanced tetraethyl orthosilicate of the interlayer dielectric 24. Due to the high selectivity between plasma enhanced tetraethyl orthosilicate and plasma enhanced nitride under the wet etching method, the shape of the second passivation layer 302 is not changed.
Referring to fig. 19, an organic film 400 made of polyimide is coated on the surface of the passivation layer 300, and the polyimide fills each recess 31. As an example, the thickness of the organic film layer 400 is 4um to 8 um.
Finally, the organic film layer 400 is patterned and cured to form the final chip edge structure 100.
In the above embodiments, the connection between the first recess 311 and the second recess 312 may be a step transition, and may be a curved transition. Since the maximum width of the second recess 312 is greater than the maximum width of the first recess 311, after the polyimide fills the first recess 311 and the second recess 312, the polyimide can be more firmly cured with the passivation layer 300 or the passivation layer 300 and the interlayer dielectric 24 or the first passivation layer 301 and the second passivation layer 302 or the first passivation layer 301, the second passivation layer 302 and the interlayer dielectric 24.
In the above-described respective embodiments, the planar pattern of each of the recessed areas 31 (anchor areas) includes a plurality of rows of stripes, dotted lines, or dot matrixes. Generally, the number of rows of the planar pattern of the recess regions 31 is 1 to 5 rows.
Referring to fig. 20, the planar pattern of the recess 31 is in the form of a stripe, and the stripe surrounds the entire junction terminal extension of the chip. As an example, the planar pattern of the recess regions 31 is formed of 2 rows of stripes, the width of the stripes is in the range of 3um to 7um, and the stripe-to-stripe distance is in the range of 3um to 10 um.
Referring to fig. 21, the planar pattern of the recess 31 is in the form of dotted lines, and the dotted lines surround the entire terminal extension of the chip, and the dotted lines in each row may be aligned or staggered. As an example, the planar pattern of the recess 31 is formed by 2 lines of dotted lines staggered with each other, the width and the interval of the dotted lines are both in the range of 3um to 7um, the length of the dotted lines is in the range of 5um to 10um, and the distance between the dotted lines and the dotted lines is in the range of 3um to 10 um.
Referring to fig. 22, the planar pattern of the recessed areas 31 is in a lattice shape, and the lattice shape surrounds the entire junction terminal extension structure of the chip, and the lattice shapes of each row may be aligned or staggered. As an example, the planar pattern of the depression region 31 is formed of 2 lines of lattice shapes staggered with each other, the diameter and the pitch of the lattice shapes are both in the range of 3um to 7um, and the distance between the lattice shapes is in the range of 3um to 10 um.
So far, the structural principle and the generation principle of the chip edge structure of the various embodiments described above are provided herein by taking a single passivation layer or a double passivation layer as an example. It is to be understood that the embodiments illustrated herein are for the purpose of assisting the description of the chip edge structure, and are not intended to limit the scope of the present invention, and a person skilled in the art may also generate a chip edge structure including three passivation layers or four passivation layers, etc. according to the teaching of the present invention, for example, a third passivation layer is deposited again on the surface of the second passivation layer 302, wherein the materials of the first passivation layer and the third passivation layer are the same, and the materials of the first passivation layer and the third passivation layer are different from the materials of the second passivation layer. For another example, a fourth passivation layer is deposited again on the surface of the third passivation layer, the first passivation layer and the third passivation layer are made of the same material, the second passivation layer and the fourth passivation layer are made of the same material, and the first passivation layer and the second passivation layer are made of different materials. By analogy, those skilled in the art can generate a chip edge structure with more passivation layers according to the teaching of the present invention, and details thereof are not repeated herein.
As another aspect of the embodiments of the present invention, the embodiments of the present invention provide a method for fabricating a chip edge structure. Referring to fig. 23, a method S500 for fabricating a chip edge structure includes:
s51, providing an edge main body structure layer;
s52, depositing a passivation layer on the surface of the edge main body structure layer;
s53, patterning the passivation layer to form at least one recessed region;
and S54, forming an organic film layer on the surface of the passivation layer, wherein the organic film layer fills each concave region.
The organic film layer can be firmly solidified with the passivation layer because the organic film layer fills the depression region of the passivation layer, so that the organic film layer or the passivation layer is not easy to fall off during the process.
In some embodiments, S53 includes: and patterning the passivation layer by adopting a dry etching mode to form at least one recessed area.
In some embodiments, the edge body structure layer includes a substrate, an epitaxial layer disposed on a surface of the substrate, a doping junction region disposed in a surface region of the epitaxial layer and extending from the surface of the epitaxial layer toward the substrate, an interlayer dielectric disposed on a portion of the surface of the epitaxial layer and in contact with the doping junction region, and a top metal layer disposed on a surface of the doping junction region and in contact with the interlayer dielectric such that at least a portion of the interlayer dielectric is interposed between the doping junction region and the top metal layer.
In some embodiments, each recessed region includes a first recess and a second recess, and the passivation layer is of a different material than the interlayer dielectric. Referring to fig. 24, S53 includes:
s531, patterning the passivation layer by adopting a dry etching mode to form a first concave part;
and S532, patterning the interlayer dielectric by adopting a wet etching mode to form a second concave part.
In some embodiments, the first passivation layer is a different material than the interlayer dielectric, the passivation layer is a plasma enhanced nitride, and the interlayer dielectric is plasma enhanced tetraethyl orthosilicate. Referring to fig. 25, S53 includes:
s533, patterning the passivation layer and the interlayer dielectric in a dry etching mode to form an initial shape of a recess region;
and S534, patterning the interlayer dielectric by adopting a wet etching mode to form the final shape of the concave area.
In some embodiments, the passivation layer includes a first passivation layer and a second passivation layer. Referring to fig. 26, S52 includes:
s521, depositing a first passivation layer on the surfaces of the interlayer dielectric and the top metal layer;
and S522, depositing a second passivation layer on the surface of the first passivation layer.
In some embodiments, each recessed region includes a first recess and a second recess, the first passivation layer and the second passivation layer being of different materials. Referring to fig. 27, S53 includes:
step 535, patterning the second passivation layer by adopting a dry etching mode to form a first concave part;
and S536, patterning the first passivation layer by adopting a wet etching mode to form a second concave part.
In some embodiments, each recess region includes a first recess and a second recess, the first passivation layer and the second passivation layer are different in material, the first passivation layer and the interlayer dielectric are the same in material, the first passivation layer and the interlayer dielectric are both plasma-enhanced tetraethyl orthosilicate, and the second passivation layer is plasma-enhanced nitride. Referring to fig. 28, S53 includes:
s537, respectively patterning the second passivation layer and the first passivation layer by adopting a dry etching mode to form an initial shape of the depression region;
and S538, patterning the first passivation layer in a wet etching mode to form the final shape of the depression region.
It should be noted that, in the foregoing embodiments, a certain order does not necessarily exist between the foregoing steps, and it can be understood by those skilled in the art from the description of the embodiments of the present invention that, in different embodiments, the foregoing steps may have different execution orders, that is, may be executed in parallel, may also be executed in an exchange manner, and the like.
It should be noted that, for the technical details that are not described in detail in the method embodiment for manufacturing the chip edge structure, reference may be made to the chip edge structure provided in the embodiment of the present invention.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (18)
1. A chip edge structure, comprising:
an edge body structure layer;
the passivation layer is arranged on the surface of the edge main body structure layer along a preset direction and is provided with at least one recessed area;
and the organic film layer is arranged on the surface of the passivation layer along the preset direction and fills each concave area.
2. The chip edge structure of claim 1, wherein the edge body structure layer comprises:
a substrate;
the epitaxial layer is arranged on the surface of the substrate along the preset direction;
a doped junction region disposed in a surface region of the epitaxial layer and extending from a surface of the epitaxial layer toward the substrate direction;
an interlayer dielectric disposed on a portion of the surface of the epitaxial layer in the preset direction and contacting the doped junction region;
a top metal layer disposed on a surface of the doped junction region along the preset direction and contacting the interlayer dielectric such that at least a portion of the interlayer dielectric is interposed between the doped junction region and the top metal layer along the preset direction.
3. The chip edge structure according to claim 1 or 2, wherein each of the recessed regions includes a first recessed portion and a second recessed portion, the first recessed portion communicates with the second recessed portion, and a maximum width of the second recessed portion is greater than a maximum width of the first recessed portion in a direction perpendicular to the predetermined direction.
4. The chip edge structure of claim 3, wherein the second recess is in contact with or extends into the interlayer dielectric.
5. The chip edge structure of claim 3, wherein the passivation layer comprises:
the first passivation layer is arranged on the surface of the edge main body structure layer along the preset direction;
and the second passivation layer is arranged on the surface of the first passivation layer along the preset direction, wherein the second passivation layer is provided with the first concave part, and the first passivation layer is provided with the second concave part.
6. The chip edge structure of claim 2, wherein the substrate comprises any one of: a silicon carbide substrate, a silicon substrate, and a gallium nitride substrate.
7. The chip edge structure according to any of claims 1 to 6, wherein the organic film layer comprises a polyimide layer.
8. The chip edge structure according to any one of claims 1 to 6, wherein the planar pattern of each of the recessed regions comprises one or more rows of a stripe-like pattern, a dotted-line-like pattern, or a dot-matrix-like pattern.
9. A method of fabricating a chip edge structure, the method comprising:
providing an edge body structure layer;
depositing a passivation layer on the surface of the edge main body structure layer;
patterning the passivation layer to form at least one recess region;
and forming an organic film layer on the surface of the passivation layer, so that the organic film layer fills each concave region.
10. The method of claim 9, wherein the patterning the passivation layer to form at least one recessed region comprises:
and patterning the passivation layer by adopting a dry etching mode to form at least one recessed area.
11. The method of claim 9, wherein the edge body structure layer comprises a substrate, an epitaxial layer disposed on a surface of the substrate, a doped junction region disposed in a surface region of the epitaxial layer and extending from the surface of the epitaxial layer in a direction toward the substrate, an interlayer dielectric disposed on a portion of the surface of the epitaxial layer and in contact with the doped junction region, and a top metal layer disposed on the surface of the doped junction region and in contact with the interlayer dielectric such that at least a portion of the interlayer dielectric is sandwiched between the doped junction region and the top metal layer.
12. The method of claim 11, wherein each of the recessed regions comprises a first recess and a second recess, the passivation layer being of a different material than the interlayer dielectric;
wherein the patterning the passivation layer to form at least one recess region comprises:
patterning the passivation layer by adopting a dry etching mode to form the first concave part;
and patterning the interlayer dielectric by adopting a wet etching mode to form the second concave part.
13. The method of claim 11, wherein the passivation layer is a different material than the interlayer dielectric;
wherein the patterning the passivation layer to form at least one recess region comprises:
patterning the passivation layer and the interlayer dielectric by adopting a dry etching mode to form an initial shape of the depression region;
and patterning the interlayer dielectric by adopting a wet etching mode to form the final shape of the recess region.
14. The method of claim 12 or 13, wherein the passivation layer is a plasma enhanced nitride and the interlayer dielectric is plasma enhanced tetraethyl orthosilicate.
15. The method of claim 9, wherein the passivation layers comprise a first passivation layer and a second passivation layer;
wherein, depositing a passivation layer on the surface of the edge main body structure layer comprises:
depositing the first passivation layer on the surface of the interlayer dielectric and the top metal layer;
and depositing the second passivation layer on the surface of the first passivation layer.
16. The method of claim 15, wherein each of the recessed regions comprises a first recess and a second recess, the first passivation layer and the second passivation layer being different materials;
wherein the patterning the passivation layer to form at least one recess region comprises:
patterning the second passivation layer by adopting a dry etching mode to form the first sunken part;
and patterning the first passivation layer by adopting a wet etching mode to form the second concave part.
17. The method of claim 15, wherein each of the recessed regions comprises a first recess and a second recess, the first passivation layer being a different material than the second passivation layer, the first passivation layer being the same material as the interlayer dielectric;
wherein the patterning the passivation layer to form at least one recess region comprises:
patterning the second passivation layer and the first passivation layer respectively by adopting a dry etching mode to form an initial shape of the depression region;
and patterning the first passivation layer by adopting a wet etching mode to form the final shape of the depression region.
18. The method of claim 16 or 17, wherein the first passivation layer and the interlayer dielectric are both plasma enhanced tetraethyl orthosilicate and the second passivation layer is plasma enhanced nitride.
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