CN208460745U - A kind of chip edge structure - Google Patents

Abstract

The utility model relates to technical field of semiconductor device, more particularly to a kind of chip edge structure.Wherein, chip edge structure includes edge body structure sheaf, passivation layer and organic film, and the surface of edge body structure sheaf is arranged in along preset direction for passivation layer, and passivation layer has at least one depressed area；The surface of passivation layer is arranged in along preset direction for organic film, and fills each depressed area.Due to the depressed area of organic film filling passivation layer, organic film can solidify with passivation layer securely, and therefore, passivation layer is less likely to occur to peel during technique or obscission.

Description

A kind of chip edge structure

Technical field

The utility model relates to technical field of semiconductor device, more particularly to a kind of chip edge structure.

Background technique

Such as Schottky diode constant power device can work under several hectovolts or even a few kilovoltages, power device work Make under such high electric field, the insulation degree between environment is important design element.

In order to have excellent insulation characterisitic, traditional handicraft deposited one or more layers passivation layer on power device, blunt Changing layer can be used for reducing electric stress, mechanical stress, steam or the chemical attack of power device metal surface.

Inventor in the process of implementing the utility model, although discovery traditional technology the prior art has at least the following problems: power Device have good electrical characteristic, still, the passivation layer of power device in the other links of technique, for example, grinding back surface or When cutting, additional stress can be generated with subsurface material, cause passivation layer to be easy to peel, or even fall off.And these passivation layers Obscission occurs often in the corner of power device chip.

Utility model content

One purpose of the utility model embodiment is intended to provide a kind of chip edge structure, and the fastness of passivation layer compares It is good.

In order to solve the above technical problems, the utility model embodiment the following technical schemes are provided:

In a first aspect, the utility model embodiment provides a kind of chip edge structure, comprising:

Edge body structure sheaf；

The surface of the edge body structure sheaf is arranged in along preset direction for passivation layer, and the passivation layer has extremely A few depressed area；

Organic film, the surface of the passivation layer is arranged in along the preset direction, and fills each depressed area.

Optionally, the edge body structure sheaf includes:

Substrate；

Epitaxial layer, along the surface that the substrate is arranged in the preset direction；

Interface is adulterated, is arranged in the surface region of the epitaxial layer, and from the surface of the epitaxial layer described in Substrate direction extends；

Interlayer dielectric, along a part of surface that the epitaxial layer is arranged in the preset direction, and with the doping Interface contact；

Metal layer at top is situated between along the surface that the doping interface is arranged in the preset direction, and with the interlayer electricity Matter contact, so that at least part of the interlayer dielectric is interposed in the doping interface and the top along the preset direction Between portion's metal layer.

Optionally, the passivation layer is plasma enhanced nitride, and the interlayer dielectric is plasma enhancing original silicon Sour tetra-ethyl ester.

Optionally, each depressed area include the first recessed portion and the second recessed portion, first recessed portion with it is described The connection of second recessed portion, on the direction perpendicular to the preset direction, the maximum width of second recessed portion is greater than described The maximum width of first recessed portion.

Optionally, second recessed portion is contacted or is extended into the interlayer dielectric with the interlayer dielectric.

Optionally, the passivation layer includes:

First passivation layer, along the surface that the edge body structure sheaf is arranged in the preset direction；

Second passivation layer, along the surface that first passivation layer is arranged in the preset direction, wherein described second is blunt Change layer and be equipped with first recessed portion, first passivation layer is equipped with second recessed portion.

Optionally, first passivation layer and the interlayer dielectric are all plasma enhancing tetraethyl orthosilicate, institute Stating the second passivation layer is plasma enhanced nitride.

Optionally, the substrate includes any one of following: silicon carbide substrates, silicon substrate and gallium nitride substrate.

Optionally, the organic film includes polyimide layer.

Optionally, which is characterized in that the plane pattern of each depressed area include a line or multirow ribbon pattern, Empty linear pattern or lattice-like pattern.

In the chip edge structure that each embodiment of the utility model provides, passivation layer is laminated in edge along preset direction The surface of main structure layer, and the surface of passivation layer is equipped at least one depressed area, and organic film is laminated in along preset direction The surface of passivation layer, and fill each depressed area.Due to the depressed area of organic film filling passivation layer, organic film energy Enough to solidify securely with passivation layer, therefore, passivation layer is less likely to occur to peel during technique or obscission.

Detailed description of the invention

One or more embodiments are illustrated by the picture in corresponding attached drawing, these exemplary theorys The bright restriction not constituted to embodiment, the element in attached drawing with same reference numbers label are expressed as similar element, remove Non- to have special statement, composition does not limit the figure in attached drawing.

Fig. 1 is that the utility model embodiment provides a kind of schematic diagram of chip edge structure；

Fig. 2 is the sectional view for forming the edge body structure sheaf after passivation layer that the utility model first embodiment provides；

Fig. 3 is the schematic diagram by dry etching passivation layer formation depressed area that the utility model first embodiment provides；

Fig. 4 is the sectional view for the organic film filling depressed area that the utility model first embodiment provides；

Fig. 5 is the sectional view for forming the edge body structure sheaf after passivation layer that the utility model second embodiment provides；

Fig. 6 is the first recess by dry etching passivation layer formation depressed area that the utility model second embodiment provides The schematic diagram in portion；

Fig. 7 is the offer of the utility model second embodiment by the second of wet etching interlayer dielectric formation depressed area The schematic diagram of recessed portion；

Fig. 8 is the sectional view for the organic film filling depressed area that the utility model second embodiment provides；

Fig. 9 is the sectional view for forming the edge body structure sheaf after passivation layer that the utility model 3rd embodiment provides；

Figure 10 is that being formed by dry etching passivation layer with interlayer dielectric of providing of the utility model 3rd embodiment is recessed Fall into the schematic diagram of the original shape in area；

Figure 11 be the utility model 3rd embodiment provide by wet etching interlayer dielectric formed depressed area most The schematic diagram of end form shape；

Figure 12 is the sectional view for the organic film filling depressed area that the utility model 3rd embodiment provides；

Figure 13 is the edge master after the first passivation layer of formation and the second passivation layer that the utility model fourth embodiment provides The sectional view of body structure sheaf；

Figure 14 be the utility model fourth embodiment provide by the of the second passivation layer formation of dry etching depressed area The schematic diagram of one recessed portion；

Figure 15 be the utility model fourth embodiment provide by the of the first passivation layer formation of wet etching depressed area The schematic diagram of two recessed portions；

Figure 16 is the sectional view for the organic film filling depressed area that the utility model fourth embodiment provides；

Figure 17 is the offer of the 5th embodiment of the utility model by the second passivation layer of dry etching and the first passivation layer shape At the schematic diagram of the original shape of depressed area；

Figure 18 is the offer of the 5th embodiment of the utility model by the first passivation layer of wet etching and interlayer dielectric shape At the schematic diagram of the final shape of depressed area；

Figure 19 is the sectional view for the organic film filling depressed area that the 5th embodiment of the utility model provides；

Figure 20 is the stripped schematic diagram of the plane pattern of depressed area provided by the embodiment of the utility model；

Figure 21 is that the plane pattern of depressed area provided by the embodiment of the utility model is in the schematic diagram of dotted line shape；

Figure 22 is that the plane pattern of depressed area provided by the embodiment of the utility model is in the schematic diagram of lattice-like.

Specific embodiment

In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only to explain this Utility model is not used to limit the utility model.

Although the utility model embodiment indicates each element using term first, second etc., but it is understood that , these elements should not limit by above-mentioned term.Above-mentioned term is only used for distinguishing an element and another element.Example Such as, first element can be named as second element, and similarly, second element can be named as first element, above-mentioned to be made The protection scope that is not intended to limit the utility model of name.Also, the quantity for indicating each element using first, second etc. Including odd number and plural number, unless context explicitly indicates.

The terms "include", "comprise" that the utility model embodiment is related to by use, specify the feature, entirety, The presence of step, operations, elements, and/or components, but be not excluded for one or more of the other feature, entirety, step, operation, element, The presence of component and/or its group is additional.

The utility model embodiment may include any semiconductor structure with semiconductor surface using term " substrate ", In some embodiments, substrate include silicon carbide substrates (Silicon carbide substrate, SiC substrate) or Silicon (Si) substrate or gallium nitride (GaN) substrate, in further embodiments, substrate can also include SiGe (SiGe), germanium (Ge) or GaAs (GaAs).

The term "horizontal" that the utility model embodiment is related to is intended to the surface for describing to be arranged essentially parallel to semiconductor substrate, For example, the surface of silicon carbide substrates.

The term " vertical " that the utility model embodiment is related to is intended to the surface for describing to be arranged essentially parallel to semiconductor substrate Normal direction orientation.

One or more interlayer substances that the utility model embodiment as shown below is related to, position between layers Relationship has used such as term " stacking " or " formation " or " application " or " setting " to be expressed, and those skilled in the art can manage Solution: any term such as " is laminated " or " formation " or " application ", can cover whole modes, type and the skill of " stacking " Art.For example, sputtering, plating, molding, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor are heavy Product (Physical Vapor Deposition, PVD), evaporation, mixing physics-chemical vapor deposition (Hybrid Physical- Chemical Vapor Deposition, HPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) etc..

Chip edge structure provided by the embodiment of the utility model can be formed in knot terminal extended structure (Junction Termination extension, JTE), it can also be multi-region JTE that knot terminal extended structure, which can be list area JTE,.It can manage Solution, chip edge structure can be combined with each type active area and metal electrode is fabricated to each type and specification Power device, for example, power device include Schottky diode (Schottky Barrier Diode, SBD), JBS diode, Ambipolar isolated-gate field effect transistor (IGFET) (IGBT), metal oxide isolated-gate field effect transistor (IGFET) (MOS), thyristor (SCR) Etc..

It will also be appreciated that: power device can also be with other resolution elements (such as power device, capacity cell, electricity Sensing unit, processor etc.) in conjunction with and constitute have realize particular electrical function functional circuit, for example, by igbt transistor The intelligent power module (Intelligent Power Module, IPM) constituted with other resolution elements, alternatively, by multiple two The half-wave rectifier bridge or full-wave rectification bridge that pole pipe is constituted, alternatively, half-bridge drive circuit or the full-bridge driving being made of multiple metal-oxide-semiconductors Circuit etc..

However, it is also possible to be further understood that the functional circuit constituted based on power device, it can be combined with other function Energy circuit or dynamic structure or physical structure, to be configured to realize the electronic equipment of specific function, for example, intelligent power module In conjunction with engine, to realize the power output of unmanned plane.

So far, chip edge structure provided by the embodiment of the utility model can be applied to any suitable industry field, The protection scope that the utility model embodiment is not intended to limit the utility model this example.

Multiple embodiments of the utility model are comprehensively described below with reference to Figure of description.Those skilled in the art can Using understanding: herein by Figure of description as the idealized embodiments of the utility model exemplary multiple sectional views with And other schematic diagrames describe the embodiments of the present invention, therefore, those skilled in the art are expected: due to manufacturing technology And/or the variation of diagram shape caused by tolerance.Therefore, the utility model embodiment should not be interpreted as limited to be shown here The specific shape in region, but include the form variations for example generated by manufacture.For example, being shown as dry etching or wet process erosion Depressed area after quarter will depend on the different degrees of reduction formed and have different binary to change.Therefore, shown in figure Region is actually schematical, and its shape is not intended to indicate the accurate shape in the region of device, and is not intended to limit this reality With novel protection scope.For the various areas Ceng He, the embodiments of the present invention are described with reference to particular polarity conductivity type.So It and is that the polarity in the area Ceng He can be inverted to provide the device of opposite polarity as will be understood by the skilled person in the art.

Referring to Fig. 1, chip edge structure 100 includes: edge body structure sheaf 200, passivation layer 300 and organic film 400。

Edge body structure sheaf 200 is the basic structure layer for realizing the semiconductor function of power device.

The surface 20 of edge body structure sheaf 200 is arranged in along preset direction for passivation layer 300, and passivation layer 300 has Depressed area 31, wherein the quantity of depressed area 31 can be one, can also be multiple.In the present embodiment, those skilled in the art Member is it is to be understood that purpose of utility model for the utility model embodiment, preset direction are that the setting of passivation layer 300 exists The surface 20 of edge body structure sheaf 200 and be configured to realize power device electrical functions reasonable direction, for example, with basic The direction for being parallel to the surface 20 of edge body structure sheaf 200 is horizontal direction, and preset direction is basic with the horizontal direction Direction where vertical normal is correspondingly arranged method by selection, and according to vertical direction, passivation layer 300 is arranged at edge On the surface 20 of main structure layer 200.

In some embodiments, the number of plies of passivation layer 300 can be single layer, can also be multilayer.Passivation layer 300 is using blunt Change material, for example, passivation layer 300 selects plasma enhancing tetraethyl orthosilicate (Plasma enhanced tetraethyl Orthosilicate, PETEOS), can also select plasma enhanced nitride (Plasma enhanced nitride, PENit)。

Organic film 400 is arranged in the surface 32 of passivation layer 300 along preset direction, and organic film 400 fill it is each Depressed area 31.For example, accepting above-mentioned example, organic film 400 is vertically disposed at the surface 32 of passivation layer 300, setting When, organic film 400 flows into each depressed area 31, and then, organic film 400 fills each depressed area 31.

After organic film 400 is filled into each depressed area 31, organic film 400 can be solid with passivation layer 300 securely Change, therefore, passivation layer 300 is less likely to occur to peel during technique or obscission.

In some embodiments, organic film 400 can be polyimide layer (Polyimide), can also be other conjunctions Suitable organism layer.In general, polyimides has the characteristics such as light-weight, flexible, heat-resisting and chemicals-resistant, suitable for guarantor Protect silicon carbide power device.Polyimides is generally together with plasma enhanced chemical vapor deposition material composition multilayer passivation layer It uses, for example, polyimides is used together with plasma enhancing tetraethyl orthosilicate or plasma-enhanced nitride, to obtain Obtain more preferably electrical and mechanical property.

In some embodiments, referring to Fig. 2, edge body structure sheaf 200 includes: substrate 21 (Substrate), extension 22 (Epitaxy) of layer, doping interface 23 (Doped junction region), (the Inter layer of interlayer dielectric 24 Dielectric, ILD) and metal layer at top 25 (Top metal layer).

Substrate 21 can be by all types of semi-conducting material manufacturings at such as silicon carbide substrates.As an example, substrate 21 can be with It is formed by the silicon carbide of the first conduction type (for example, N-type or p-type).Substrate 21 is highly doped silicon carbide, with a thickness of 350um, Resistivity is in the range of 0.02 Ω cm to 0.03 Ω cm.Wherein, the semiconductor type of substrate is carried by most in semiconductor Stream determine, if the majority carrier of the first conduction type be hole, the first conduction type be p-type, the first of heavy doping Conduction type is P+ type, and the first kind being lightly doped is P-type；If the majority carrier of the first conduction type is electronics, the One conduction type is N-type, and the first conduction type of heavy doping is N+ type, and the first kind being lightly doped is N-type.If first is conductive When type is N-type, then the second conduction type is p-type, and vice versa.

Epitaxial layer 22 is along the surface that substrate 21 is arranged in preset direction.As an example, epitaxial layer 22 is on substrate 21 The silicon carbide of the first conduction type (for example, N-type or p-type) of growth.Epitaxial layer 22 is the silicon carbide being lightly doped, and thickness exists In the range of 5um to 30um, doping concentration is in 1e15cm^-3To 2e16cm^-3In the range of.

Doping interface 23 is arranged in the surface region of epitaxial layer 22, and from the surface of epitaxial layer 22 towards 21 side of substrate To extension, for example, doping interface 23 passes through ion implanting and diffusing, doping in the part of the surface of epitaxial layer 22 along preset direction. As an example, doping interface 23 is the second conduction type (for example, p-type or N-type) that doping concentration is higher than epitaxial layer 22.Doping knot The junction depth in area 23 is within the scope of 0.3um to 1.2um, and doping concentration is in 1e18cm^-3To 1e20cm^-3In the range of.

Interlayer dielectric 24 is arranged in a part of surface of epitaxial layer 22 along preset direction, also, interlayer dielectric 24 with Interface 23 is adulterated to contact.Interlayer dielectric 24 is deposited in the surface of epitaxial layer 22, and is patterned to expose contact zone 241. Interlayer dielectric 24 can be formed by oxide appropriate, such as silane (SiH4) base oxide or tetraethyl orthosilicate (TEOS) base Oxide.Oxide as interlayer dielectric 24 can be formed by appropriate technique, and technique appropriate includes but is not limited to low pressure Chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma CVD etc..

In some embodiments, tetraethyl orthosilicate is enhanced by deposition plasma and forms interlayer dielectric 24, interlayer The thickness of dielectric 24 is within the scope of 1um to 2um.

Metal layer at top 25 is along the surface that doping interface 23 is arranged in preset direction, and metal layer at top 25 and interlayer Dielectric 24 contacts, so that at least part of interlayer dielectric 24 is interposed in doping interface 23 and top metal along preset direction Between layer 25.Metal layer at top 25 is metal layer, such as the metal material that metal layer at top 25 uses includes aluminium (Al), titanium (Ti), nickel (Ni) or the more metal layers formed by above two or various metals be can be.In some embodiments, top Metal layer 25 is aluminium, and thickness is in the range of 1um to 4um.

Cutting Road 26 (Scribe line) is also shown in Fig. 2.

The surface of interlayer dielectric 24 Yu metal layer at top 25 is arranged in along preset direction for passivation layer 300.For example, some In embodiment, the passivation layer 300 that tetraethyl orthosilicate forms single layer, the thickness of passivation layer 300 are enhanced by deposition plasma Within the scope of 1um to 2um.It in further embodiments, can also be in the blunt of the single layer of plasma enhancing tetraethyl orthosilicate On the surface for changing layer 300, deposition plasma enhances the passivation layer 300 of the single layer of nitride, so far, has formed the blunt of bilayer Change layer 300.It is understood that the content that those skilled in the art are instructed and guided according to the utility model can in conjunction with business demand To deposit the passivation layer 300 of multilayer, showing for the passivation layer 300 of single or double layer shown hereinbefore or hereinafter is not limited to herein Example.

Referring to Fig. 3, passivation layer 300 is patterned processing, etches and form depressed area 31, it is in some embodiments, recessed Anchoring area (Anchor zone) can also be known as by falling into area 31.As an example, the passivation layer 300 of single layer uses dry etching (Dry Etch) mode, in etching process, plasma of the reactive ion 33 according to the set time as defined in process recipe, with passivation layer 300 Body enhances tetraethyl orthosilicate reaction, to remove the plasma enhancing tetraethyl orthosilicate of specific thicknesses in passivation layer 300.

Referring to Fig. 4, using the organic film 400 of polyimides, and polyimides in the coating of the surface of passivation layer 300 Fill each depressed area 31.As an example, organic film 400 with a thickness of 4um to 8um.

Finally, by 400 patterned process of organic film and solidifying to form final chip edge structure 100.

With above-mentioned each embodiment the difference lies in that in some embodiments, depressed area 31 is formed in passivation layer 300 and layer Between on dielectric 24.Each depressed area 31 includes the first recessed portion 311 and the second recessed portion 312, the first recessed portion 311 and second Recessed portion 312 is connected to, on the direction perpendicular to preset direction, also that is, in the table for being basically parallel to edge body structure sheaf 200 In the horizontal direction in face 21, the maximum width of the second recessed portion 312 is greater than the maximum width of the first recessed portion 311.

Referring to Fig. 5, by along preset direction interlayer dielectric 24 and metal layer at top 25 surface deposition plasma Body enhances nitride, and to form passivation layer 300, herein, the thickness of passivation layer 300 is within the scope of 0.5um to 2um.

Referring to Fig. 6, using dry etching mode patterned process passivation layer 300, to form the first recessed portion 311, In dry etch process, plasma enhancing of the reactive ion 33 according to the set time as defined in process recipe, with passivation layer 300 Nitride reaction to remove the plasma-enhanced nitride of specific thicknesses in passivation layer 300, and stops at interlayer electricity Jie At matter 24.

Referring to Fig. 7, interlayer dielectric 24 is etched to form the second recessed portion 312.As an example, using wet etching (Wet etch) mode patterned process interlayer dielectric 24, to form the second recessed portion 312.Wet etching mode is mainly with hydrogen Fluoric acid is reactant, and in wet etch process, hydrofluoric acid 34 is according to the set time as defined in process recipe, with isotropically Remove the plasma enhancing tetraethyl orthosilicate in interlayer dielectric 24 in specific thicknesses.Due under wet etch process, Highly selective between plasma enhancing tetraethyl orthosilicate and plasma-enhanced nitride, the shape of passivation layer 300 is not It can be changed.

Referring to Fig. 7, the first recessed portion 311 is located on passivation layer 300, the second recessed portion 312 and interlayer dielectric 24 contacts, for example, the surface of interlayer dielectric 24 can be used as the bottom of the second recessed portion 312.In some embodiments, second is recessed Concave portion 312 can also extend into interlayer dielectric 24.

Referring to Fig. 8, using the organic film 400 of polyimides, and polyimides in the coating of the surface of passivation layer 300 Fill each depressed area 31.As an example, organic film 400 with a thickness of 4um to 8um.

Finally, by 400 patterned process of organic film and solidifying to form final chip edge structure 100.

With above-mentioned each embodiment the difference lies in that in some embodiments, the original shape of depressed area 31 can be formed in On passivation layer 300 and interlayer dielectric 24, subsequent to re-form, the final shape of depressed area 31.

Referring to Fig. 9, by along preset direction interlayer dielectric 24 and metal layer at top 25 surface deposition plasma Body enhances nitride, and to form passivation layer 300, herein, the thickness of passivation layer 300 leads to again later within the scope of 0.5um to 2um Cross photoetching process and reactive ion etching mode patterned process passivation layer 300.

Referring to Fig. 10, using dry etching mode patterned process passivation layer 300 and interlayer dielectric 24, it is recessed to be formed Fall into the original shape in area 31.As an example, in dry etch process, when reactive ion 33 as defined in process recipe according to fixing Between, with the plasma-enhanced nitride of passivation layer 300 and the plasma enhancing tetraethyl orthosilicate of interlayer dielectric 24 Reaction, to remove the plasma-enhanced nitride of passivation layer 300 and the plasma enhancing original silicon of interlayer dielectric 24 Sour tetra-ethyl ester.

Figure 11 is please referred to, using wet etching mode patterned process interlayer dielectric 24, to form depressed area 31 most End form shape.As an example, hydrofluoric acid 34 is according to the set time as defined in process recipe, with each to same in wet etch process Remove to property the plasma enhancing tetraethyl orthosilicate in interlayer dielectric 24 in specific thicknesses.Due in wet etch process Under, highly selective between plasma enhancing tetraethyl orthosilicate and plasma-enhanced nitride, the shape of passivation layer 300 It will not be changed.

Figure 12 is please referred to, coating uses the organic film 400 of polyimides on the surface of passivation layer 300, and polyamides is sub- Amine fills each depressed area 31.As an example, organic film 400 with a thickness of 4um to 8um.

Finally, by 400 patterned process of organic film and solidifying to form final chip edge structure 100.

With above-mentioned each embodiment the difference lies in that the number of plies of passivation layer be 2 layers or more when, the formation side of depressed area 31 Formula exists different.

Figure 13 is please referred to, passivation layer 300 includes: the first passivation layer 301 and the second passivation layer 302, wherein the second passivation layer 302 are equipped with the first recessed portion 311, and the first passivation layer 301 is equipped with the second recessed portion 312.

First passivation layer 301 is along the surface that edge body structure sheaf 200 is arranged in preset direction.As an example, passing through Enhance tetraethyl orthosilicate in the surface deposition plasma of interlayer dielectric 24 and metal layer at top 25 along preset direction, with shape At the first passivation layer 301, the thickness of the first passivation layer 301 is within the scope of 1um to 2um.

Second passivation layer 302 is along the surface that the first passivation layer 301 is arranged in preset direction.As an example, by along pre- Set direction enhances nitride in the surface deposition plasma of the first passivation layer 301, to form the second passivation layer 302.Second is blunt Change the thickness of layer 302 in 0.5um to 2um range.Pass through photoetching process and reactive ion etching mode patterned process again later First passivation layer 301 and the second passivation layer 302.

Figure 14 is please referred to, using the second passivation layer of dry etching mode patterned process 302, to form the first recessed portion 311.As an example, reactive ion 33 is according to the set time as defined in process recipe, with the second passivation in dry etch process The plasma-enhanced nitride reaction of layer 302, so that the plasma-enhanced nitride of the second passivation layer 302 is removed, and It stops at the first passivation layer 301.

Figure 15 is please referred to, using the first passivation layer of wet etching mode patterned process 301, to form the second recessed portion 312.As an example, hydrofluoric acid 34 is according to the set time as defined in process recipe, in wet etch process with isotropically Remove the plasma enhancing tetraethyl orthosilicate in the first passivation layer 301 in specific thicknesses.Due under wet etch process, It is highly selective between plasma enhancing tetraethyl orthosilicate and plasma-enhanced nitride, the shape of the second passivation layer 302 Shape will not be changed.Second recessed portion 312 extends into interlayer dielectric 24.

Figure 16 is please referred to, coating uses the organic film 400 of polyimides on the surface of passivation layer 300, and polyamides is sub- Amine fills each depressed area 31.As an example, organic film 400 with a thickness of 4um to 8um.Not with above-mentioned each embodiment It is with putting, polyimides is filled to the second recessed portion 312, and polyimides can be securely by the first passivation layer 301, second Passivation layer 302 and interlayer dielectric 24 solidify.

Finally, by 400 patterned process of organic film and solidifying to form final chip edge structure 100.

With above-mentioned each embodiment the difference lies in that the original shape of depressed area 31 can be formed in the second passivation layer 302 with On first passivation layer 301, the subsequent final shape for re-forming depressed area 31.

The formation process of first passivation layer 301 and the second passivation layer 302 can refer to above-described embodiment, no longer superfluous herein It states.

Figure 17 is please referred to, patterned process the second passivation layer 302 and the first passivation layer are distinguished using dry etching mode 301, to form the original shape of depressed area 31.As an example, reactive ion 33 is according to process recipe in dry etch process The defined set time increases with the plasma-enhanced nitride of the second passivation layer 302 and the plasma of the first passivation layer 301 Strong tetraethyl orthosilicate reaction, to remove the plasma-enhanced nitride and the first passivation layer 301 of the second passivation layer 302 Plasma enhancing tetraethyl orthosilicate, to form the original shape of depressed area 31.When dry etching, reactive ion 33 can lose The first passivation layer 301 of segment thickness is carved, the first passivation layer 301 of remainder thickness is etched by wet etching；Reaction Ion 33 can also through manner, etch the first passivation layer 301 of full depth；Reactive ion 33 can even etch Continue the interlayer dielectric 24 of etching part thickness after complete first passivation layer 301.

Figure 18 is please referred to, using the first passivation layer of wet etching mode patterned process 301, to form depressed area 31 most End form shape.As an example, hydrofluoric acid 34 is according to the set time as defined in process recipe, with each to same in wet etch process Remove to property the plasma enhancing tetraethyl orthosilicate and interlayer dielectric 24 in the first passivation layer 301 in specific thicknesses Plasma enhancing tetraethyl orthosilicate.Due under wet etch process, plasma enhancing tetraethyl orthosilicate and it is equal from Highly selective between daughter enhancing nitride, the shape of the second passivation layer 302 will not be changed.

Figure 19 is please referred to, coating uses the organic film 400 of polyimides on the surface of passivation layer 300, and polyamides is sub- Amine fills each depressed area 31.As an example, organic film 400 with a thickness of 4um to 8um.

Finally, by 400 patterned process of organic film and solidifying to form final chip edge structure 100.

In above-mentioned each embodiment, the junction between the first recessed portion 311 and the second recessed portion 312 can be step Transition can be surface blending.Since the maximum width of the second recessed portion 312 is greater than the maximum width of the first recessed portion 311, gather After acid imide fills the first recessed portion 311 and the second recessed portion 312 respectively, polyimides can strongerlyly and passivation layer 300 or passivation layer 300 and interlayer dielectric 24 or the first passivation layer 301 and the second passivation layer 302 or the first passivation layer 301, the second passivation layer 302 and interlayer dielectric 24 solidify.

In above-mentioned each embodiment, the plane pattern of each depressed area 31 (anchoring area) includes the ribbon of several rows, void Linear or lattice-like.In general, the line number of the plane pattern of depressed area 31 is 1 to 5 row.

Figure 20 is please referred to, the plane pattern of depressed area 31 is stripped, and ribbon toroid is around the entire knot terminal of chip Extended structure.As an example, the plane pattern of depressed area 31 is formed by 2 row's bands, the range of the width of band in 3um to 7um Interior, band and band distance are in the range of 3um to 10um.

Figure 21 is please referred to, the plane pattern of depressed area 31 is in dotted line shape, and the whole knot of dotted line shape around chip is whole Extended structure is held, every row dotted line shape can be aligned, can also interlock.As an example, the plane pattern of depressed area 31 by handing over each other 2 wrong row dotted line shapes are formed, the width and spacing of dotted line shape in the range of 3um to 7um, the length of dotted line shape 5um extremely In the range of 10um, the distance between dotted line shape and dotted line shape are in the range of 3um to 10um.

Figure 22 is please referred to, the plane pattern of depressed area 31 is in lattice-like, and the whole knot of lattice-like around chip is whole Extended structure is held, every row lattice-like can be aligned, can also interlock.As an example, the plane pattern of depressed area 31 by handing over each other 2 wrong row lattice-likes are formed, and the diameter and spacing of lattice-like are in the range of 3um to 7um, between lattice-like and lattice-like Distance is in the range of 3um to 10um.

So far, herein with single layer passivation layer or double layer passivation layer as an example, providing above-mentioned each embodiment about core The structural principle and generating principle of piece marginal texture.It is understood that embodiment cited herein is to aid in illustrating Chip edge structure, the protection scope being not intended to limit the utility model, those skilled in the art are according to the utility model institute The content of instruction and guide can also generate the chip edge structure including three layers of passivation layer or four layers of passivation layer etc., for example, herein On the surface for the second passivation layer 302 that each embodiment is illustrated, again deposit third passivation layer, wherein the first passivation layer with The material of third passivation layer is identical, and the first passivation layer is different with the material of the second passivation layer from the material of third passivation layer.Example again Such as, the 4th passivation layer is deposited again on the surface of third passivation layer, the first passivation layer is identical as the material of third passivation layer, the Two passivation layers are identical as the material of the 4th passivation layer, and the material of the first passivation layer is different from the material of the second passivation layer.Class according to this It pushes away, those skilled in the art hold in the utility model is instructed and guided, and the chip edge knot of more layers passivation layer can be generated Structure, details are not described herein.

Finally, it should be noted that above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations； Under the thinking of the utility model, it can also be combined between the technical characteristic in above embodiments or different embodiments, Step can be realized with random order, and there are many other variations of the different aspect of the utility model as described above, be Simplicity, they do not provide in details；Although the utility model is described in detail with reference to the foregoing embodiments, this The those of ordinary skill in field it is understood that it is still possible to modify the technical solutions described in the foregoing embodiments, Or equivalent replacement of some of the technical features；And these are modified or replaceed, and do not make the sheet of corresponding technical solution Matter is detached from the range of each embodiment technical solution of the application.

Claims (10)

1. a kind of chip edge structure characterized by comprising

Edge body structure sheaf；

The surface of the edge body structure sheaf is arranged in along preset direction for passivation layer, and the passivation layer has at least one A depressed area；

Organic film, the surface of the passivation layer is arranged in along the preset direction, and fills each depressed area.

2. chip edge structure according to claim 1, which is characterized in that the edge body structure sheaf includes:

Substrate；

Epitaxial layer, along the surface that the substrate is arranged in the preset direction；

Interface is adulterated, is arranged in the surface region of the epitaxial layer, and from the surface of the epitaxial layer towards the substrate Direction extends；

Interlayer dielectric, along a part of surface that the epitaxial layer is arranged in the preset direction, and with the doping interface Contact；

Metal layer at top along the surface that the doping interface is arranged in the preset direction, and connects with the interlayer dielectric Touching, so that at least part of the interlayer dielectric is interposed in the doping interface and the top-gold along the preset direction Belong between layer.

3. chip edge structure according to claim 2, which is characterized in that the passivation layer is plasma enhanced silicon nitride Object, the interlayer dielectric are plasma enhancing tetraethyl orthosilicate.

4. chip edge structure according to claim 2, which is characterized in that each depressed area includes the first recessed portion With the second recessed portion, first recessed portion is connected to second recessed portion, on the direction perpendicular to the preset direction, The maximum width of second recessed portion is greater than the maximum width of first recessed portion.

5. chip edge structure according to claim 4, which is characterized in that second recessed portion and the interlayer electricity are situated between Matter is contacted or is extended into the interlayer dielectric.

6. chip edge structure according to claim 4, which is characterized in that the passivation layer includes:

First passivation layer, along the surface that the edge body structure sheaf is arranged in the preset direction；

Second passivation layer, along the surface that first passivation layer is arranged in the preset direction, wherein second passivation layer Equipped with first recessed portion, first passivation layer is equipped with second recessed portion.

7. chip edge structure according to claim 6, which is characterized in that first passivation layer and the interlayer electricity are situated between Matter is all plasma enhancing tetraethyl orthosilicate, and second passivation layer is plasma enhanced nitride.

8. chip edge structure according to claim 2, which is characterized in that the substrate includes any one of following: carbonization Silicon substrate, silicon substrate and gallium nitride substrate.

9. chip edge structure according to any one of claim 1 to 8, which is characterized in that the organic film includes Polyimide layer.

10. chip edge structure according to any one of claim 1 to 8, which is characterized in that each depressed area Plane pattern includes the ribbon pattern, empty linear pattern or lattice-like pattern of a line or multirow.