CN212991039U - Wafer with semiconductor device and semiconductor device - Google Patents

Abstract

The utility model discloses a wafer and semiconductor device with semiconductor device, wafer include that the branch locates a plurality of semiconductor devices on the wafer and distributes in the scribing region around the semiconductor device, and the semiconductor device comprises epitaxial layer, electrode structure, the metal interconnection structure that forms on and by the substrate at least in proper order, and the scribing region has the slot, and slot opening direction is located metal interconnection structure one side and degree of depth to substrate, and the slot bottom has the isolation layer. It has the following advantages: the damage caused by mechanical stress and electrical stress generated in the wafer cutting process is prevented from spreading to the epitaxial active region, and the reliability of the semiconductor device is improved.

Description

Wafer with semiconductor device and semiconductor device

Technical Field

The utility model relates to a semiconductor field especially relates to a wafer and semiconductor device with semiconductor device.

Background

Electronic power technology plays an important role in the production and life of modern human beings, and power electronic devices are ubiquitous from household appliances in daily life to industrial production, electric appliance transportation and new energy technology. In electronic power equipment, in order to realize efficient power conversion, higher performance requirements such as low conduction loss, high voltage resistance, high temperature resistance and the like need to be provided for electronic power devices, and the operating efficiency of the electronic power equipment is directly influenced by the quality of the devices or chips. Gallium nitride as a third-generation wide bandgap semiconductor material has the advantages of high saturated electron mobility, high breakdown electric field and the like, and has the inherent advantages of being used as an electronic power device. The application of the silicon-based gallium nitride technology greatly reduces the preparation cost of the gallium nitride semiconductor device and provides possibility for the preparation of 8 'and 12' silicon-based gallium nitride in the future.

However, in the process of manufacturing the silicon-based gallium nitride semiconductor device, due to lattice mismatch and thermal stress mismatch between the gallium nitride epitaxial layer and the silicon substrate, many defects such as dislocation and stacking fault are generated in the epitaxial layer; these defects will exist all the time, and will gradually extend to the epitaxial active region of the device due to the wheel knife and laser during the dicing process of the wafer, which will seriously affect the electrical property and reliability of the device. Therefore, there is a need for an improved structure of semiconductor devices on a wafer to reduce the influence of epitaxial defects on the devices during the dicing process, thereby improving the quality and reliability of silicon-based gallium nitride semiconductor devices.

SUMMERY OF THE UTILITY MODEL

The utility model provides a wafer and semiconductor device with semiconductor device, it has overcome the not enough of prior art.

The utility model provides a technical scheme that its technical problem adopted is:

a wafer with semiconductor devices comprises a plurality of semiconductor devices arranged on the wafer in a dividing mode and scribing areas distributed around the semiconductor devices, wherein each semiconductor device at least comprises a substrate, an epitaxial layer, an electrode structure and a metal interconnection structure, the epitaxial layer, the electrode structure and the metal interconnection structure are sequentially formed on the substrate, each scribing area is provided with a groove, the opening direction of each groove is located on one side of the metal interconnection structure, the depth of each groove reaches the substrate, and an isolation layer is arranged at the bottom of each groove. In addition, both ends of the isolation layer may extend toward the boundary of the bottom of the trench and deep into the substrate of the semiconductor device.

In one embodiment, the trench bottom is planar and has a width of 60-120 μm.

In one embodiment, the thickness of the isolation layer is 0.1-1 μm.

In one embodiment, the two isolation layers are respectively disposed on two sides of the bottom of the trench.

In one embodiment, the sum of the widths of the two isolation layers is greater than or equal to two-thirds of the width of the bottom of the trench.

In one embodiment, the thickness of the bottom of the trench extending into the substrate to the depth is greater than or equal to one fifth of the thickness of the substrate and less than the thickness of the substrate.

In one embodiment, the isolation layer is an electrostatic isolation layer. In addition, the electrostatic isolation layer may be formed by ion implantation of nitrogen ions, oxygen ions, or the like, which can form electrostatic isolation.

In one embodiment, the semiconductor device further comprises a passivation layer covering the side portions of the trench, wherein the passivation layer extends from the side portions of the trench to the bottom portion to at least partially cover the isolation layer.

In one embodiment, the passivation layer extends to cover the upper part of the semiconductor device in the direction of the trench opening, and has an opening above the metal interconnection structure.

The semiconductor device is formed by cutting the wafer with the semiconductor device, and a circle of electrostatic isolation layer is arranged in a cutting area of the outer peripheral surface of the substrate.

Compared with the prior art, the technical scheme has the following advantages:

1. the groove is arranged between the semiconductor devices, the opening direction of the groove is positioned at one side of the metal interconnection structure and the depth of the groove reaches the substrate, and the groove separates the space between the epitaxial active region and the cutting position of the semiconductor devices, so that the crystal damage caused by the mechanical stress and the electrical stress generated in the subsequent wafer cutting process can not spread to the active region of the devices through the epitaxial layer; at the same time, mechanical stress due to substrate lattice mismatch can also be mitigated.

2. The bottom of the groove is provided with the isolation layer, and a circle of electric insulation barrier can be formed around the substrate of the semiconductor device, so that electrostatic breakdown caused by mechanical friction in the subsequent cutting process is avoided.

3. The passivation layer covers the side portion of the groove, so that the peripheral surface of an epitaxial active region of the semiconductor device is further protected, and the stability and the reliability of the device are improved.

Drawings

The present invention will be further explained with reference to the drawings and examples.

FIG. 1 is a schematic partial cross-sectional view of a wafer having semiconductor devices.

FIG. 2 is a schematic cross-sectional view of an ion isolation layer according to a preferred embodiment.

FIG. 3 is a schematic cross-sectional view of an ion isolation layer according to another preferred embodiment.

Icon: 1-a substrate; 2-epitaxy; 21-a gallium nitride buffer layer; 22-aluminum gallium nitrogen barrier layer; 3-source drain gate electrode structure; 4-metal interconnect structures; 41-a first dielectric layer; 42-a second dielectric layer; m1 — first metal interconnect layer; m2 — second metal interconnect layer; 5-an isolating layer; 6-a passivation layer; 7-a groove; 8-masking;

Detailed Description

As shown in fig. 1 to 2, a wafer with semiconductor devices includes a plurality of semiconductor devices separately disposed on the wafer and a scribe area (i.e., a cutting area of each semiconductor device) distributed around the semiconductor devices, where the semiconductor devices are composed of at least a substrate 1 and an epitaxial layer 2, an electrode structure 3, and a metal interconnection structure 4 sequentially formed thereon, and the substrate 1 is a Si-containing substrate. The scribing region is provided with a groove 7, and the opening direction of the groove 7 is positioned at one side of the metal interconnection structure 4 and the depth of the groove is up to the substrate 1. Space separation is formed between the active region and the cutting position, so that damage caused by a subsequent cutting process cannot spread to the active region of the device through the epitaxial layer 2; at the same time, mechanical stresses due to lattice mismatch of the substrate 1 can also be relieved. The trench 7 may be formed by etching using a dry etching technique such as plasma etching or inductive coupling.

The trench has a spacer 5 at the bottom. The two ends of the isolation layer 5 may also extend towards the boundary of the bottom of the trench 7 and deep into the substrate 1 of the semiconductor device. The bottom of the trench 7 is planar and has a width of 60-120 μm. The thickness of the isolation layer 5 is 0.1-1 μm. The isolation layer 5 is specifically an electrostatic isolation layer formed by ion implantation that can form electrostatic isolation, such as nitrogen ions, oxygen ions, and the like. The introduction of the isolation layer 5 can form a ring of electrically insulating barriers around the active region, thereby avoiding potential electrostatic breakdown due to mechanical friction during subsequent dicing.

The isolation layer 5 can be one or two, as shown in fig. 3, and two isolation layers 5 are respectively disposed on two sides of the bottom of the trench 7. The two isolation layers 5 are formed by firstly arranging a mask 8 between two sides of the bottom of the trench 7 and then performing ion implantation, and the sum of the widths of the two isolation layers 5 is greater than or equal to two thirds of the width of the bottom of the trench 7.

The thickness of the bottom of the trench 7 extending into the substrate 1 is greater than or equal to one fifth of the thickness of the substrate 1 and less than the thickness of the substrate 1.

In the cutting process, both wheel cutter cutting and laser cutting expose the semiconductor device to a critical environment. In order to further protect the semiconductor device and improve the stability and reliability of the semiconductor device, the passivation layer 6 may be covered by deposition (or spin coating) or the like on the side of the trench 7, and the passivation layer 6 extends at least partially on the isolation layer 5 from the side of the trench 7 to the bottom. The passivation layer 6 includes, but is not limited to, a common insulating material such as silicon oxide, silicon nitride, or a high molecular organic material such as polyimide (polyimide) or benzocyclobutene (BCB). The passivation layer 6 may also extend over the upper portion of the semiconductor device in the direction of the opening of the trench 7 and have an opening above the metal interconnect structure 4.

In this embodiment, the semiconductor device may be a group III-V compound semiconductor device such as a gallium nitride device or a gallium arsenide device.

The preparation process of the wafer with the semiconductor device described in this embodiment is as follows:

step 1: preparing a basic epitaxial layer structure of the gallium nitride-based semiconductor device on the epitaxial layer 2 on the substrate 1 by using a general semiconductor device preparation method (such as metal organic vapor deposition, ion implantation, etching, photoetching and other methods), wherein the basic epitaxial layer structure comprises a gallium nitride buffer layer 21 and an aluminum gallium nitrogen barrier layer 22;

step 2: preparing electrodes on the epitaxial layer 2, wherein the electrodes comprise source, drain and gate metal electrodes;

and step 3: after the three-terminal metal electrode is finished, growing a first dielectric layer 41 by using a thin film technology and preparing a first metal interconnection layer M1;

and 4, step 4: on the basis of the step 3, growing a second dielectric layer 42 again by using a thin film technology and preparing a second metal interconnection layer M2;

and 5: and etching the epitaxial material and other dielectric materials in the cutting region around each semiconductor bare chip by using a dry etching method and the like until the Si substrate is exposed, thereby forming the groove 7. The etched die active areas are separated in space to form a separated table top;

step 6: and (3) carrying out ion implantation isolation near the side wall of the trench 7 by using an ion implantation technology, and forming an isolation layer 5 at the bottom of the trench 7. Implanted ions include, but are not limited to, ions that form an electrostatic separation layer in the semiconductor material, such as nitrogen ions, oxygen ions, and the like;

and 7: a passivation layer 6 is formed on the surface of the active region of the chip by a conventional method of semiconductor fabrication such as deposition (or spin coating) and extends to the ion isolation layer 5. The passivation layer 6 includes, but is not limited to, a common insulating material such as silicon oxide, silicon nitride, or a high molecular organic material such as polyimide (polyimide) or benzocyclobutene (BCB).

A semiconductor device is formed by cutting the wafer with the semiconductor device, and a circle of electrostatic isolation layer is arranged in a cutting area of the outer peripheral surface of a substrate.

The above description is only a preferred embodiment of the present invention, and therefore the scope of the present invention should not be limited by this description, and all equivalent changes and modifications made within the scope and the specification of the present invention should be covered by the present invention.

Claims (10)

1. A wafer with semiconductor devices comprises a plurality of semiconductor devices arranged on the wafer and a scribing area distributed around the semiconductor devices, and is characterized in that: the semiconductor device at least comprises a substrate, an epitaxial layer, an electrode structure and a metal interconnection structure which are sequentially formed on the substrate, wherein a scribing area is provided with a groove, the opening direction of the groove is positioned on one side of the metal interconnection structure and extends to the substrate in depth, and an isolation layer is arranged at the bottom of the groove.

2. The wafer with the semiconductor device according to claim 1, wherein: the bottom of the groove is a plane and the width of the groove is 60-120 mu m.

3. The wafer with the semiconductor device according to claim 1, wherein: the thickness of the isolation layer is 0.1-1 μm.

4. The wafer with the semiconductor device according to claim 1, wherein: the two isolation layers are respectively arranged on two sides of the bottom of the groove.

5. The wafer with the semiconductor device as claimed in claim 4, wherein: the sum of the widths of the two isolation layers is greater than or equal to two thirds of the width of the bottom of the groove.

6. The wafer with the semiconductor device according to claim 1, wherein: the thickness of the bottom of the groove extending into the substrate to the extending part is larger than or equal to one fifth of the thickness of the substrate and smaller than the thickness of the substrate.

7. The wafer with the semiconductor device according to claim 1, wherein: the isolation layer is an electrostatic isolation layer.

8. The wafer with the semiconductor device according to any one of claims 1 to 7, wherein: the semiconductor device further comprises a passivation layer covering the side portions of the trench, wherein the passivation layer extends from the side portions of the trench to the bottom portion to at least partially cover the isolation layer.

9. The wafer with the semiconductor device according to claim 8, wherein: the passivation layer extends to the direction of the groove opening to cover the upper part of the semiconductor device, and an opening is formed above the metal interconnection structure.

10. A semiconductor device obtained by dicing the wafer having semiconductor devices according to any one of claims 1 to 9, characterized in that: the cutting area of the peripheral surface of the substrate is provided with a ring of electrostatic isolation layer.

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