CN210296775U - USB3.0 and SpaceWire conversion interface - Google Patents
USB3.0 and SpaceWire conversion interface Download PDFInfo
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- CN210296775U CN210296775U CN201921254607.7U CN201921254607U CN210296775U CN 210296775 U CN210296775 U CN 210296775U CN 201921254607 U CN201921254607 U CN 201921254607U CN 210296775 U CN210296775 U CN 210296775U
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Abstract
The application provides a USB3.0 and SpaceWire conversion interface, which is characterized by comprising a USB connecting terminal, a USB data temporary storage, a USB terminal control circuit, a first SpaceWire connecting terminal, a first SpaceWire data temporary storage, a first SpaceWire interface controller, a second SpaceWire connecting terminal, a second SpaceWire data temporary storage, a second SpaceWire interface controller, a SpaceWire shunt switch and a data buffer. The utility model discloses a USB3.0 realizes the electronic communication equipment who disposes USB3.0 interface with spaceborne equipment or test equipment through spaceborne wire serial bus interface with spaceborne wire conversion interface when needing to be connected interface conversion, and it can realize the asynchronous receiving and dispatching transmission of effectual data to and reach clock coordination between USB3.0 and spaceborne wire.
Description
Technical Field
The application relates to the field of electronic components, in particular to a USB3.0 and SpaceWire conversion interface.
Background
SpaceWire is a high-performance (high-speed, low-power consumption and high-reliability) serial bus interface designed by the European Space Agency (ESA) for aerospace field application, and is currently used for data communication between spacecraft-mounted devices and between the spacecraft-mounted devices and external test equipment.
Fig. 2 shows a device connection mode based on a SpaceWire serial bus interface. It can be seen that the SpaceWire serial bus interface comprises a plurality of parallel ports, and a satellite-borne device configured with the SpaceWire serial bus interface can be communicated with the outside through the plurality of parallel ports of the interface, when the port 1 is occupied, if other ports, such as the port 2, are idle, the communication connection between the device and the outside can be realized through the port 2 without waiting for the port 1 to be idle, so that the data transmission efficiency is improved, and the data transmission reliability of the SpaceWire serial bus interface is fully ensured.
The SpaceWire serial bus interface is a special data interface for satellite-borne equipment communication, satellite-ground signal communication and satellite-borne equipment test application. However, many electronic communication devices in the non-dedicated and spacecraft fields are not configured with external interfaces supporting SpaceWire. Currently, USB interfaces are widely used in various electronic devices, wherein 8 ports are provided in the currently more advanced USB3.0 interface, including a power port, a ground port and 6 (3 pairs) data ports.
Therefore, when the electronic communication device configured with the USB3.0 interface needs to be connected with the satellite-borne device or the test device through the SpaceWire serial bus interface, the electronic communication device needs to be switched between the two interfaces.
SUMMERY OF THE UTILITY MODEL
In view of this, an object of the present application is to provide a USB3.0 and SpaceWire conversion interface, so as to implement interface conversion when an electronic communication device configured with a USB3.0 interface needs to be connected with a satellite-borne device or a testing device through a SpaceWire serial bus interface.
Based on the above-mentioned purpose, the utility model provides a pair of USB3.0 and SpaceWire conversion interface, a serial communication port, including USB connecting terminal, USB data temporary storage device, USB terminal control circuit, the first SpaceWire connecting terminal of the same kind, the first SpaceWire data temporary storage device of the same kind, the first SpaceWire interface controller of the same kind, second SpaceWire connecting terminal of the same kind, second SpaceWire data temporary storage device, second SpaceWire interface controller of the same kind, SpaceWire shunt change over switch and data buffer.
The USB connecting terminal is used for connecting electronic communication equipment with a USB3.0 interface, and is connected with the USB data temporary register through a serial connection line in the conversion interface; the USB data temporary storage is connected with the data buffer; the data buffer is connected with the SpaceWire shunt switch and is connected with the first SpaceWire data temporary memory and the second SpaceWire data temporary memory through the SpaceWire shunt switch; the first SpaceWire data temporary storage is connected with the first SpaceWire connecting terminal, and the second SpaceWire data temporary storage is connected with the second SpaceWire connecting terminal.
The USB terminal control circuit is connected with the USB data temporary storage and the USB connecting terminal.
The first SpaceWire interface controller is connected with the first SpaceWire data register and the first SpaceWire connecting terminal; the second SpaceWire interface controller is connected with the second SpaceWire data temporary storage and the second SpaceWire connecting terminal.
The USB3.0 and SpaceWire conversion interface further comprises an FPGA clock circuit, a reference clock signal input end of the FPGA clock circuit is connected with the first SpaceWire interface controller and the second SpaceWire interface controller, and a clock signal output end of the FPGA clock circuit is connected with the USB terminal control circuit.
The USB3.0 and SpaceWire conversion interface further comprises a power circuit.
The USB data temporary storage adopts an FIFO register chip.
The first SpaceWire data temporary storage and the second SpaceWire data temporary storage are both FIFO register chips.
The data buffer is an SRAM cache chip.
The USB connecting terminal is provided with a power supply port, a ground port and 6 data ports of a USB3.0 protocol.
It can be seen that, the utility model discloses a USB3.0 realizes the electronic communication equipment who disposes USB3.0 interface with spaceWire conversion interface and needs to be connected interface conversion when carrying out with spaceborne equipment or test equipment through spaceWire serial bus interface, and it can realize effectual data asynchronous receiving and dispatching transmission to and reach clock coordination between USB3.0 and spaceWire.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a USB3.0 and SpaceWire conversion interface structure according to an embodiment of the present application;
fig. 2 is a device connection diagram of a SpaceWire serial bus interface in the prior art.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not limiting of the invention. It should be noted that, for convenience of description, only the relevant portions of the related inventions are shown in the drawings.
As shown in fig. 1, the utility model provides a USB3.0 and SpaceWire conversion interface, a serial communication port, include: the USB interface circuit comprises a USB connecting terminal 1, a USB data temporary memory 2, a USB terminal control circuit 3, a first SpaceWire connecting terminal 4, a first SpaceWire data temporary memory 5, a first SpaceWire interface controller 6, a second SpaceWire connecting terminal 7, a second SpaceWire data temporary memory 8, a second SpaceWire interface controller 9, a SpaceWire shunt switch 10, a data buffer 11, an FPGA clock circuit 12 and a power supply circuit 13.
The USB connecting terminal 1 is used for connecting electronic communication equipment with a USB3.0 interface, and the USB connecting terminal 1 is provided with a power supply port, a grounding port and 6 data ports according to a USB3.0 protocol. The USB connecting terminal 1 is connected with the USB data temporary storage 2 through a serial connection line inside the conversion interface; the USB data temporary storage 2 is connected with the data buffer 11; the data buffer 11 is connected with the SpaceWire shunt switch 10, and is connected with the first SpaceWire data register 5 and the second SpaceWire data register 8 through the SpaceWire shunt switch 10; the first SpaceWire data register 5 is connected with the first SpaceWire connecting terminal 4, and the second SpaceWire data register 8 is connected with the second SpaceWire connecting terminal 7. Thus, the conversion interface can realize the interface conversion between any one path between the USB connecting terminal 1 and the two paths of SpaceWire connecting terminals 4 and 7, and the switching between the two paths of SpaceWire connecting terminals is realized through the SpaceWire shunt switch 10. The data received by the USB connecting terminal 1 is cached in the USB data temporary memory 2, and then is transferred to the first SpaceWire data temporary memory 5 or the second SpaceWire data temporary memory 8 through the data buffer 11, and then is further provided for the first SpaceWire connecting terminal 4 or the second SpaceWire connecting terminal 7. Similarly, the data received by the first-path SpaceWire connection terminal 4 or the second-path SpaceWire connection terminal 7 is cached in the first-path SpaceWire data temporary memory 5 or the second-path SpaceWire data temporary memory 8, then is transferred to the USB data temporary memory 2 through the data buffer 11, and then is sent to the USB connection terminal 1.
The USB terminal control circuit 3 is connected to the USB data temporary storage 2 and the USB connection terminal 1. The USB terminal control circuit 3 controls data transmission and reception and signal conversion of the USB connection terminal. The first SpaceWire interface controller 6 is connected with the first SpaceWire data register 5 and the first SpaceWire connecting terminal 4; the second SpaceWire interface controller 9 is connected with the second SpaceWire data temporary storage 8 and the second SpaceWire connecting terminal 7. The two SpaceWire interface controllers respectively control data receiving and transmitting and signal conversion of the two SpaceWire connecting terminals.
The USB3.0 and SpaceWire conversion interface further comprises an FPGA clock circuit 12, a reference clock signal input end of the FPGA clock circuit 12 is connected with the first SpaceWire interface controller 6 and the second SpaceWire interface controller 9, and a clock signal output end of the FPGA clock circuit 12 is connected with the USB terminal control circuit 3. Therefore, in the aspect of clock coordination, the conversion interface takes the clock of the SpaceWire interface as a reference, and coordinates the clock of the USB interface to keep synchronous coordination with the clock. The USB3.0 and SpaceWire conversion interface further comprises a power circuit 13, and power supply of all parts is achieved.
The USB data temporary storage 2 adopts an FIFO register chip. The first SpaceWire data register 5 and the second SpaceWire data register 8 both adopt FIFO register chips. The data buffer 11 is an SRAM cache chip.
It can be seen that, the utility model discloses a USB3.0 realizes the electronic communication equipment who disposes USB3.0 interface with spaceWire conversion interface and needs to be connected interface conversion when carrying out with spaceborne equipment or test equipment through spaceWire serial bus interface, and it can realize effectual data asynchronous receiving and dispatching transmission to and reach clock coordination between USB3.0 and spaceWire.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be understood by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, but also covers other embodiments formed by any combination of the above-mentioned features or their equivalents without departing from the spirit of the present invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (10)
1. The utility model provides a USB3.0 and spaceWire conversion interface, its characterized in that, including USB connecting terminal, USB data temporary storage, USB terminal control circuit, first way spaceWire connecting terminal, first way spaceWire data temporary storage, first way spaceWire interface controller, second way spaceWire connecting terminal, second way spaceWire data temporary storage, second way spaceWire interface controller, spaceWire shunt switch and data buffer.
2. The USB3.0 and SpaceWire interface of claim 1, wherein the USB connection terminal is used to connect the electronic communication device configuring the USB3.0 interface, and the USB connection terminal is connected to the USB data temporary storage device via the internal serial connection of the interface; the USB data temporary storage is connected with the data buffer; the data buffer is connected with the SpaceWire shunt switch and is connected with the first SpaceWire data temporary memory and the second SpaceWire data temporary memory through the SpaceWire shunt switch; the first SpaceWire data temporary storage is connected with the first SpaceWire connecting terminal, and the second SpaceWire data temporary storage is connected with the second SpaceWire connecting terminal.
3. The USB3.0 and SpaceWire interface as claimed in claim 2, wherein said USB terminal control circuit is connected to said USB data buffer and said USB connection terminal.
4. The USB3.0 and SpaceWire conversion interface of claim 3, wherein the first SpaceWire interface controller is connected to the first SpaceWire data register and the first SpaceWire connection terminal; the second SpaceWire interface controller is connected with the second SpaceWire data temporary storage and the second SpaceWire connecting terminal.
5. The interface as claimed in claim 4, wherein the interface comprises a FPGA clock circuit, a reference clock signal input terminal of the FPGA clock circuit is connected to the first SpaceWire interface controller and the second SpaceWire interface controller, and a clock signal output terminal of the FPGA clock circuit is connected to the USB terminal control circuit.
6. The USB3.0 and SpaceWire interface as recited in claim 5, wherein the USB3.0 and SpaceWire interface further comprises a power circuit.
7. The USB3.0 and SpaceWire interface as recited in claim 6, wherein the USB data buffer is implemented using a FIFO register chip.
8. The USB3.0 and SpaceWire interface of claim 7, wherein the first SpaceWire data register and the second SpaceWire data register are FIFO register chips.
9. The USB3.0 and SpaceWire interface as recited in claim 8, wherein the data buffer is an SRAM cache chip.
10. The USB3.0 to SpaceWire interface as claimed in claim 9 wherein the USB connection terminals are configured with a power port, a ground port and 6 data ports of USB3.0 protocol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921254607.7U CN210296775U (en) | 2019-08-05 | 2019-08-05 | USB3.0 and SpaceWire conversion interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921254607.7U CN210296775U (en) | 2019-08-05 | 2019-08-05 | USB3.0 and SpaceWire conversion interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210296775U true CN210296775U (en) | 2020-04-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921254607.7U Active CN210296775U (en) | 2019-08-05 | 2019-08-05 | USB3.0 and SpaceWire conversion interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210296775U (en) |
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2019
- 2019-08-05 CN CN201921254607.7U patent/CN210296775U/en active Active
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