CN210224043U - Floating junction type Schottky diode - Google Patents
Floating junction type Schottky diode Download PDFInfo
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- CN210224043U CN210224043U CN201920806493.6U CN201920806493U CN210224043U CN 210224043 U CN210224043 U CN 210224043U CN 201920806493 U CN201920806493 U CN 201920806493U CN 210224043 U CN210224043 U CN 210224043U
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Abstract
The utility model relates to a float knot formula schottky diode, include: a substrate layer 1; the epitaxial layer 2 is positioned on the upper layer of the substrate layer 1; the floating junction region 3 is positioned in the rectangular groove in the middle of the epitaxial layer 2; an insulation type polysilicon layer 4 positioned on the upper layer of the floating junction region 3; the groove 5 is positioned on the upper layer of the insulation type polycrystalline silicon layer 4; a cathode 6 of Schottky contact is positioned at the lower layer of the substrate layer 1; and an anode 7 of Schottky contact covers the epitaxial layer 2, the insulating polycrystalline silicon layer 4 and the groove 5. The utility model provides a diode through the process steps who has improved the formula of floating junction schottky diode, does not need the secondary growth epitaxial layer, simultaneously, has increased device breakdown voltage, has reduced on-resistance, has promoted the power merit, has reduced the technology degree of difficulty and cost.
Description
Technical Field
The utility model belongs to the technical field of the microelectronics is made, concretely relates to float knot formula schottky diode.
Background
The SiC Schottky barrier diode is used as a wide bandgap semiconductor device to replace a Si device in the technical field of power electronics. The greatest advantage of SiC schottky barrier diodes in the field of power electronics is their excellent reverse recovery characteristics. At present, commercial SiC schottky barrier diodes are widely used in the fields of high-frequency switching power supplies, power factor correction, motor driving and the like. When used in conjunction with the best current power MOSFETs, the switching frequency can reach 400kHz and is expected to be higher than 1 MHz. Many companies use SiC schottky barrier diodes instead of Si fast recovery diodes in their IGBT inverter or inverter devices with overall benefits far exceeding the cost increase due to the price difference between SiC and Si devices.
Compared with the Si Schottky barrier diode, the SiC Schottky barrier diode has the advantages of low leakage current, high switching speed and the like, and has great potential in the aspect of power application. However, there is still a contradiction between the breakdown voltage and the on-resistance that is a constraint that the high breakdown voltage and the low on-resistance cannot be satisfied at the same time. Meanwhile, in the process of manufacturing the common Schottky barrier diode with the floating junction structure, the epitaxial layer needs to grow twice, and the process difficulty and the cost are high.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned problem that exists among the prior art, the utility model provides a 4H-SiC floats junction barrier schottky diode. The to-be-solved technical problem of the utility model is realized through following technical scheme:
the embodiment of the utility model provides a 4H-SiC of slot floats knot barrier schottky diode, include:
a substrate layer;
the epitaxial layer is positioned on the upper layer of the substrate layer;
the floating junction area is positioned in the rectangular groove in the middle of the epitaxial layer;
an insulation type polysilicon layer located on the upper layer of the floating junction region;
the groove is positioned on the upper layer of the insulation type polycrystalline silicon layer;
the cathode of the Schottky contact is positioned at the lower layer of the substrate layer;
and the anode of the Schottky contact covers the epitaxial layer, the insulating polycrystalline silicon layer and the groove.
In an embodiment of the present invention, the epitaxial layer is made of N-The thickness of the ion-doped 4H-SiC is 5-15 mu m.
In one embodiment of the present invention, the depth of the rectangular groove is 0.5 μm to 1.5 μm, and the width is 1 μm to 3 μm.
In one embodiment of the present invention, the thickness of the insulating polysilicon layer is 0.8 μm to 1 μm, and the width is 0.5 μm to 1.5 μm.
In one embodiment of the present invention, the cathode of the schottky contact is made of Ti/Ni/Ag metal.
In one embodiment of the present invention, the anode of the schottky contact is made of Ti/Al metal.
Compared with the prior art, the beneficial effects of the utility model are that:
1. the utility model provides a diode has increased device breakdown voltage, has reduced on-resistance, has promoted the power optimal value.
2. The utility model provides a manufacturing method of diode has improved the process steps of 4H-SiC floating junction formula schottky barrier diode, does not need the secondary growth epitaxial layer, has reduced the technology degree of difficulty and cost.
Drawings
Fig. 1 is a schematic cross-sectional view of a diode in a floating junction schottky barrier diode according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a floating junction schottky barrier diode according to an embodiment of the present invention;
fig. 3 is a schematic view of a manufacturing process in a method for manufacturing a floating junction schottky barrier diode according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the present invention is not limited thereto.
Example one
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and to simplify the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present invention, unless otherwise expressly specified or limited, the first feature "on" or "under" the second feature may include both the first and second features being in direct contact, and may also include the first and second features being in contact, not being in direct contact, but rather being in contact with each other via additional features between them. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description of the present invention, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a diode in a floating junction schottky barrier diode according to an embodiment of the present invention, where the diode includes:
a substrate layer 1;
the epitaxial layer 2 is positioned on the upper layer of the substrate layer 1;
the floating junction area 3 is positioned in the rectangular groove in the middle of the epitaxial layer 2;
an insulation type polysilicon layer 4 positioned on the upper layer of the floating junction region 3;
a trench 5 located on the upper layer of the insulation type polysilicon layer 4;
a cathode 6 in Schottky contact, which is positioned at the lower layer of the substrate layer 1;
and an anode 7 of the Schottky contact covers the epitaxial layer 2, the insulating polycrystalline silicon layer 4 and the trench 5.
In particular, the upper layer mentioned in the present invention refers to the upper layer adjacent to and above the upper layer; the middle of the epitaxial layer 2 mentioned in the utility model refers to the transverse middle of the epitaxial layer 2 which is longitudinally on the upper part; the middle of the insulated polysilicon 4 mentioned in the utility model refers to the transverse middle and the longitudinal upper part of the insulated polysilicon 4; the lower layer mentioned in the utility model is adjacent to the lower layer and is positioned below the lower layer.
In a specific embodiment, the substrate layer 1 may be selected to be N+The prefix 4H refers to the structure type of SiC, SiC can form different crystal structures under different physical and chemical environments, the crystals with the same components and different shapes, structures and physical characteristics are called homogeneous multi-image variants, the SiC homogeneous multi-image variants are found at present more than 200, the most common homogeneous multi-image variant structures of SiC are 3C-SiC (zinc blende structure), 2H-SiC (zinc blende structure), 4H-SiC and 6H-SiC, wherein 3C-SiC is also called β -SiC, 2H-SiC is called α -SiC, and the N is selected as the novel silicon nitride, the silicon carbide has the advantages of large forbidden band width, high breakdown electric field intensity, high saturated electron drift velocity, large heat conductivity, small dielectric constant, strong radiation resistance, good chemical stability and the like, and is particularly suitable for manufacturing high-temperature, high-frequency, high-power and radiation-resistant devices+The ion-doped 4H-SiC can ensure that the Schottky diode has extremely fast switching response speed, the switching characteristic is not influenced by junction temperature, the switching loss is extremely low, and the reverberation recovery time is almost zero.
In the embodiment of the present invention, N can be selected as the material of the epitaxial layer 2-The ion-doped 4H-SiC can be 5 μm to 15 μm thick.
In a specific embodiment, the epitaxial layer 2 is positioned on the substrate layer 1, by being in the N+Growing a layer of N on the ion-doped 4H-SiC substrate by adopting a horizontal hot-wall CVD method-Ion-doped 4H-SiC of 5-15 μm thicknessEpitaxial layer 2, wherein N-The doping concentration of the ions is 1X 1016cm-3～3×1016cm-3。
In the embodiment of the utility model, the depth of the rectangular groove is 0.5 μm to 1.5 μm, and the width is 1 μm to 3 μm.
In one embodiment, SiO is deposited on the N-epitaxial layer 22Mask layer, mask thickness 2 μm. The mask pattern is formed by a photolithography etching process. And forming a rectangular groove by an ICP (inductively coupled plasma) etching method, wherein the depth of the rectangular groove is 0.5-1.5 mu m, the width of the rectangular groove is 1-3 mu m, and the rectangular groove is used for reducing the peak value of the electric field at the vertex angle. In the development process of power semiconductor devices, higher current and higher reverse blocking voltage are always pursued, and in order to realize high breakdown voltage, in recent years, in the research on new structures of power semiconductor devices, the hottest is a super junction structure, a semi-super junction structure and a floating junction structure. However, since the manufacturing difficulty of the super junction is very large, multiple times of alternating ion implantation and epitaxial growth are required, and compared with the floating junction device, the floating junction device is easier to realize.
Subsequently, the SiO is cleaned2Masking layer, and forming new SiO by deposition process2And forming a mask layer with the thickness of 2 mu m, and forming a mask pattern by using a photoetching process. Forming a P + region structure in the rectangular groove by Al ion implantation, wherein the concentration of the P + region structure is 5 multiplied by 1016cm-3。
Cleaning the mask layer of the implantation process, and forming new SiO by deposition process2A mask layer with a thickness of 2 μm, forming a mask pattern by photolithography and etching, and forming an N + region structure on the P + region structure by N ion implantation with a concentration of 1 × 1019cm-3。
And then, performing carbon film protection on the surface of the epitaxial layer 2 by using a carbon film sputtering machine, activating the injected ions by high-temperature annealing at 1650 ℃ for 45min to form the floating junction region 3, and then removing the carbon film by an oxidation method.
Then sacrificial oxidation is carried out, and a layer of SiO is deposited after the oxide layer is removed2Forming a source region after photoetching and windowing, and then using heatGrowing a layer of SiO by oxidation2And as a gate dielectric, annealing in an NO atmosphere at 1200 ℃ for 1 h.
In the embodiment of the present invention, the thickness of the insulating polysilicon layer 4 may be 0.8 μm to 1 μm, and the width may be 0.5 μm to 1.5 μm. Such parameters are selected to provide devices with good forward electrical, breakdown, and reverse recovery characteristics.
In a specific embodiment, the trench 5 is located in the middle of the insulating polysilicon layer 4, and the cross-sectional area of the trench 5 is smaller than that of the insulating polysilicon layer 4, so as to uniform the current density distribution in the device, thereby facilitating the subsequent test and analysis.
The utility model discloses in the embodiment, the material of the negative pole 6 of schottky contact is Ti/Ni/Ag metal, and thickness can be 300nm ~ 600nm, and wherein the content ratio of metal Ti, metal Ni, metal Ag is 3: 1: 1.
in the embodiment of the present invention, the anode 7 of the schottky contact is made of Al/Ti metal, the thickness is 400 nm-600 nm, wherein the content ratio of metal Al and metal Ti is 3: 1.
the utility model provides a schottky diode through the process steps who improves the formula of floating schottky barrier diode, does not need the secondary growth epitaxial layer, has increased device breakdown voltage, has reduced on-resistance, has promoted the power merit, and the stability of device is better.
The utility model discloses another embodiment provides a preparation method of floating junction formula schottky diode, include:
s1, selecting a substrate layer 1;
s2, forming an epitaxial layer 2 on the substrate layer 1;
s3, etching the epitaxial layer 2 to form a rectangular groove in the middle of the epitaxial layer 2;
s4, forming a floating junction area 3 in the rectangular groove;
s5, depositing an insulation type polysilicon layer 4 on the upper layer of the floating junction region 3;
s6, etching the insulation type polycrystalline silicon layer 4 to form a groove 5;
s7, forming a Schottky contact cathode 6 on the lower layer of the substrate layer 1;
and S8, forming a Schottky contact anode 7, and covering the epitaxial layer 2, the insulating polycrystalline silicon layer 4 and the trench 5.
Specifically, as shown in FIG. 2 and FIG. 3, first, a thickness range of 0.4 μm to 1 μm is selected, and the material is N+Ion-doped 4H-SiC is used as substrate layer 1.
In N+A layer of N with the thickness of 5-15 mu m is grown on the ion-doped 4H-SiC sample wafer by adopting a horizontal hot-wall CVD method-Ion-doped 4H-SiC, forming epitaxial layer 2, the precursor gases used are monosilane and propane in a hydrogen atmosphere. The growth pressure is kept at 250Mbar, and the content ratio of C and Si is 0.6-1.5. Wherein N is-The ion doping concentration is 1 × 1016cm-3～3×1016cm-3. The horizontal hot-wall CVD is adopted to finish the growth of the SiC homoepitaxial material, and the thickness concentration uniformity of the SiC epitaxial layer can be effectively improved by optimizing the flow rate and the C/Si ratio of the carrier gas H2. The method is carried out in a horizontal hot wall type CVD VP508GFR epitaxial furnace with SiH4-C3H8-H2, which is produced by EPIGRESS company, wherein the typical epitaxial temperature is 1550-1600 ℃, the growth pressure is 50-150 mbar, H2 is used as diluent gas and carrier gas, nitrogen is used as an N-type doping source, SiH4 and C3H8 are used as growth sources, a base rotates by air flotation to improve the thickness uniformity of epitaxial concentration, and the growth rate is 2-12 mu m/H.
Then cleaning the SiC sample wafer by using a standard RCA process for removing particle contamination and metal impurities by utilizing H2O2Oxidation produces an oxide film which is in turn coated with NH4OH corrosion, which is immediately followed by oxidation, repeats oxidation and corrosion, and particles adhering to the surface of the sample fall into the cleaning solution as well.
Deposition of SiO on the N-epitaxial layer 22Mask layer, mask thickness 2 μm. The mask pattern is formed by a photolithography etching process. And forming a rectangular groove by an ICP (inductively coupled plasma) etching method, wherein the width of the rectangular groove is 2 micrometers, and the depth of the rectangular groove is 1 micrometer, and the rectangular groove is used for reducing the peak value of an electric field at a vertex angle. The development of power semiconductor devices has been pursued to increase current and increase reverse currentIn order to achieve a high breakdown voltage toward the blocking voltage, in recent years, in the research on new structures of power semiconductor devices, the hottest is a super junction structure, a semi-super junction structure, and a floating junction structure. However, since the manufacturing difficulty of the super junction is very large, multiple times of alternating ion implantation and epitaxial growth are required, and compared with the floating junction device, the floating junction device is easier to realize.
Subsequently, the SiO is cleaned2Masking layer, and forming new SiO by deposition process2And forming a mask layer with the thickness of 2 mu m, and forming a mask pattern by using a photoetching process. Forming a P + region structure in the rectangular groove by Al ion implantation, wherein the concentration of the P + region structure is 5 multiplied by 1016cm-3。
Cleaning the mask layer of the implantation process, and forming new SiO by deposition process2A mask layer with a thickness of 2 μm, forming a mask pattern by photolithography and etching, and forming an N + region structure on the P + region structure by N ion implantation with a concentration of 1 × 1019cm-3。
And then, performing carbon film protection on the surface of the epitaxial layer 2 by using a carbon film sputtering machine, activating the injected ions by high-temperature annealing at 1650 ℃ for 45min to form the floating junction region 3, and then removing the carbon film by an oxidation method.
Then sacrificial oxidation is carried out, and a layer of SiO is deposited after the oxide layer is removed2Forming a source region after photoetching and windowing, and growing a layer of SiO by a thermal oxidation method2And as a gate dielectric, annealing in an NO atmosphere at 1200 ℃ for 1 h.
Depositing an insulating polycrystalline silicon layer 4 with the thickness of 4-6 mu m and the width of 0.4-0.6 mu m by adopting a low-pressure chemical vapor deposition method;
and then, an ICP etching method is adopted to enable the epitaxial layer 2 and the insulating polycrystalline silicon layer 4 to be positioned on the same plane, and a groove 5 which is aligned with the edge of the insulating polycrystalline silicon layer 4 and has a cross section area smaller than that of the insulating polycrystalline silicon layer 4 is etched.
Then Ti/Ni/Ag alloy with the thickness ratio of 300nm/100nm/100nm is deposited on the lower layer of the epitaxial layer 2 to form a cathode 6 with Schottky contact, and annealing is carried out for 3min in a nitrogen atmosphere at 1050 ℃.
And then depositing an Al/Ti alloy with the thickness ratio of 400 nm/100nm on the plane where the epitaxial layer 2 and the insulating polycrystalline silicon layer 4 are positioned to form a Schottky contact anode 7 covering the epitaxial layer 2, the insulating polycrystalline silicon layer 4 and the groove 5, and annealing for 3min in a nitrogen atmosphere at 1050 ℃, thereby forming the floating junction type Schottky barrier diode.
The utility model provides a preparation technology does not need the secondary growth epitaxial layer, has increased device breakdown voltage, has reduced on-resistance, has promoted the power merit, and the stability of device is better. The prepared diode can be applied to a high-power integrated circuit to replace a Si diode to provide more excellent power characteristics, and is widely applied to the fields of power electronic systems and electric automobiles.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.
Claims (6)
1. A floating junction schottky diode, comprising:
a substrate layer (1);
the epitaxial layer (2) is positioned on the upper layer of the substrate layer (1);
the floating junction region (3) is positioned in the rectangular groove in the middle of the epitaxial layer (2);
an insulation type polysilicon layer (4) positioned on the upper layer of the floating junction region (3);
the groove (5) is positioned on the upper layer of the insulation type polycrystalline silicon layer (4);
a cathode (6) in Schottky contact, which is positioned below the substrate layer (1);
an anode (7) of Schottky contact covering the epitaxial layer (2), the insulating polysilicon layer (4) and the trench (5).
2. Diode according to claim 1, characterized in that the epitaxial layer (2) material is N-The thickness of the ion-doped 4H-SiC is 5-15 mu m.
3. The diode of claim 1, wherein said rectangular slot has a depth of 0.5 to 1.5 μm and a width of 1 to 3 μm.
4. The diode according to claim 1, wherein the insulating polysilicon layer (4) has a thickness of 0.8 μm to 1 μm and a width of 0.5 μm to 1.5 μm.
5. Diode according to claim 1, characterized in that the material of the cathode (6) of the schottky contact is Ti/Ni/Ag metal.
6. Diode according to claim 1, characterized in that the material of the anode (7) of the schottky contact is Ti/Al metal.
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| CN110190135A (en) * | 2019-05-29 | 2019-08-30 | 西安电子科技大学芜湖研究院 | A kind of floating junction type Schottky diode and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110190135A (en) * | 2019-05-29 | 2019-08-30 | 西安电子科技大学芜湖研究院 | A kind of floating junction type Schottky diode and preparation method thereof |
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