CN210141869U

CN210141869U - Circuit for improving linearity of capacitive sensor

Info

Publication number: CN210141869U
Application number: CN201920836904.6U
Authority: CN
Inventors: 陶宪博
Original assignee: Suzhou Yimu Electronic Technology Co ltd
Current assignee: Suzhou Yimu Electronic Technology Co ltd
Priority date: 2019-06-04
Filing date: 2019-06-04
Publication date: 2020-03-13
Anticipated expiration: 2029-06-04

Abstract

The utility model relates to an improvement circuit of capacitive sensor linearity, the circuit includes voltage buffer one M1, two M2 of voltage buffer, three M3 of voltage buffer and four M4 of voltage buffer, and above-mentioned four M4 of voltage buffer, one M1 of voltage buffer, three M3 of voltage buffer and two M2 of voltage buffer are established ties in proper order between high level Vdd and earthing terminal Vss, and four M4 of voltage buffer are connected with input signal through a level shifter, the junction point between three M3 of voltage buffer and two M2 of voltage buffer is connected with the current source that together output load current equals. The utility model relates to an improvement circuit of capacitive sensor linearity, the electric current that flows through voltage buffer M1 does not receive output current source influence to keep Ibias.

Description

Circuit for improving linearity of capacitive sensor

Technical Field

The utility model relates to a circuit for improving capacitive sensor's linearity.

Background

Currently, in a capacitive sensor, an input capacitor is converted into a voltage signal at a front end and then buffered and input to a subsequent circuit, such as a PGA (programmable gain amplifier) and an ADC (analog-to-digital converter). In many applications, the linearity of the data signal is very important. For example, when the thickness of the display screen of the smart phone is increased, the linearity requirement of the capacitive sensor needs to be satisfied as much as possible to adapt to subsequent digital processing in addition to the requirement of maximized sensitivity; the higher the linearity at that time, the lower the False Acceptance Rate (FAR) and the lower the False Recognition Rate (FRR) of the fingerprint acceptance.

Voltage buffers play an important role in improving linearity, in the case of fingerprint capacitive sensors: the linear distortion is due to the fact that the voltage buffers inside the sensor are not in fact ideal, or due to the fact that the buffers associated with these signals are not in ideal, either due to the fact that the voltage buffers inside the Multiplexer (MUX) output are subsequently connected.

In the prior art, a typical voltage buffer is a MOS source follower as shown in fig. 1, a first voltage buffer M1 is a conventional drain source follower NMOS transistor, and a second voltage buffer M2 and a third voltage buffer M3 are current sources biasing the first voltage buffer M1; CL is the output load capacitance.

On the one hand, the source follower function of the first voltage buffer M1 at the output terminal is distorted, especially under the short channel effect, due to the output impedance of the first voltage buffer M1; on the other hand, the load current iL changes the voltage buffer-M1, which causes signal distortion and reduces the linearity of the buffer.

Disclosure of Invention

An object of the utility model is to overcome above-mentioned not enough, provide a circuit that effectively improves capacitive sensor linearity.

The purpose of the utility model is realized like this:

a circuit for improving linearity of a capacitive sensor comprises a first voltage buffer M1, a second voltage buffer M2, a third voltage buffer M3 and a fourth voltage buffer M4, wherein the fourth voltage buffer M4, the first voltage buffer M1, the third voltage buffer M3 and the second voltage buffer M2 are sequentially connected in series between a high level Vdd and a ground terminal Vss, the fourth voltage buffer M4 is connected with an input signal through a level shifter, and a connecting point between the third voltage buffer M3 and the second voltage buffer M2 is connected with a current source which outputs the same load current together.

The utility model relates to an improvement circuit of capacitive sensor linearity is connected with output electric capacity CL between output and earthing terminal VSS.

Compared with the prior art, the beneficial effects of the utility model are that:

the utility model discloses a fourth introduction of voltage buffer, and leading-in mirror current to make the electric current that flows through voltage buffer one not influenced by output current source and keep at Ibias, improved the linearity.

Drawings

Fig. 1 is a circuit diagram of a conventional linearity enhancement circuit for a capacitive sensor.

Fig. 2 is a circuit diagram of a linearity improvement circuit of a capacitive sensor according to the present invention.

Detailed Description

The utility model relates to an improvement circuit of capacitive sensor linearity, the circuit includes voltage buffer one M1, voltage buffer two M2, voltage buffer three M3 and voltage buffer four M4, above-mentioned voltage buffer four M4, voltage buffer one M1, voltage buffer three M3 and voltage buffer two M2 establish ties IN proper order between high level Vdd and earthing terminal Vss, voltage buffer four M4 is connected with the input signal through a level shifter, thereby make no matter how the input signal of input IN changes, all can make the VDS (drain-source voltage) change of voltage buffer one M1 keep unchanged or change the minimum; the output impedance of the voltage buffer one M1 is effectively improved;

meanwhile, a connection point between the three voltage buffers M3 and the two voltage buffers M2 is connected with a current source which outputs the same load current;

an output capacitor CL is connected between the output terminal and the ground terminal VSS, since the node N2 is a low impedance and can be considered as a virtual ground approximately, at this time, a capacitor C equivalent to the output capacitor is connected to the input terminal IN and the node N2, and since the voltages of the input terminal and the output terminal of the voltage buffer one M1 are approximately equal, the current flowing through the capacitor C is approximately the same as the load current iL; in this compensation mode, the current flowing through the voltage buffer one M1 is not affected by the output current source to maintain Ibias.

Referring to fig. 2, specifically, the circuit for improving linearity of a capacitive sensor includes a first voltage buffer M1, a second voltage buffer M2, a third voltage buffer M3 and a fourth voltage buffer M4, wherein the fourth voltage buffer M4, the first voltage buffer M1, the third voltage buffer M3 and the second voltage buffer M2 are sequentially connected IN series between a high level Vdd and a ground Vss, an input terminal IN is connected to a gate of the first voltage buffer M1, the input terminal IN is connected to a gate of the fourth voltage buffer M4 through a level shifter, and the input terminal IN is connected between a source of the second voltage buffer M2 and a drain of the third voltage buffer M3 through a level shifter;

in addition: it should be noted that the above-mentioned embodiment is only a preferred embodiment of the present patent, and any modification or improvement made by those skilled in the art based on the above-mentioned conception is within the protection scope of the present patent. In addition: it should be noted that the above-mentioned embodiment is only a preferred embodiment of the present patent, and any modification or improvement made by those skilled in the art based on the above-mentioned conception is within the protection scope of the present patent.

Claims

1. A circuit for improving linearity of a capacitive sensor is characterized in that: the circuit comprises a first voltage buffer M1, a second voltage buffer M2, a third voltage buffer M3 and a fourth voltage buffer M4, wherein the fourth voltage buffer M4, the first voltage buffer M1, the third voltage buffer M3 and the second voltage buffer M2 are sequentially connected in series between a high level Vdd and a ground terminal Vss, the fourth voltage buffer M4 is connected with an input signal through a level shifter, and a connecting point between the third voltage buffer M3 and the second voltage buffer M2 is connected with a current source which outputs the same load current together.

2. The circuit for improving linearity of a capacitive sensor of claim 1, wherein: an output capacitor CL is connected between the output terminal and the ground terminal VSS.