CN101594139A - A kind of buffer based on source follower - Google Patents
A kind of buffer based on source follower Download PDFInfo
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- CN101594139A CN101594139A CNA2009103034969A CN200910303496A CN101594139A CN 101594139 A CN101594139 A CN 101594139A CN A2009103034969 A CNA2009103034969 A CN A2009103034969A CN 200910303496 A CN200910303496 A CN 200910303496A CN 101594139 A CN101594139 A CN 101594139A
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Abstract
The invention discloses a kind of buffer, belong to technical field of analog integrated circuit design based on source follower.Described buffer comprises: the pseudo-differential input stage is used to receive differential input signal; The cross-couplings common-source stage links to each other with the pseudo-differential input stage, is used to form negative resistance, offsets the output resistance of buffer; Current source links to each other with the pseudo-differential input stage, is used to provide the buffer branch current; Capacitive load links to each other with the pseudo-differential input stage, is used for the output loading as buffer.The present invention forms negative resistance by the cross-couplings common-source stage, and then offsets the output resistance of high-speed buffer, has realized the output of unit gain buffering; By theory analysis and simulating, verifying, the present invention has realized the buffer based on source follower of ultrahigh speed, the output of unit gain buffering and high dynamic characteristic.
Description
Technical field
The present invention relates to technical field of analog integrated circuit design, particularly a kind of buffer based on source follower.
Background technology
All-parallel A/D converter (flash ADC) is the fastest a kind of of conversion speed in all kinds analog to digital converter, and it is mainly used in the data collecting field of low precision and ultrahigh speed (sample frequency is greater than 1GHz).Fig. 1 shows the analog front circuit schematic diagram of all-parallel A/D converter, and it mainly comprises open loop sampling holding circuit, ultrahigh speed buffer and prime amplifier.Generally, because all-parallel A/D converter needs the analog signal of parallel processing input, also need 2 simultaneously
N-1 parallel connection of prime amplifier, therefore, need increase one-level ultrahigh speed buffer in the output of open loop sampling holding circuit, so that drive 2 of follow-up parallel connection to increase input capacitance
N-1 prime amplifier.
Fig. 2 shows the electrical block diagram of traditional ultrahigh speed buffer, and this circuit is based on the transistorized source follower of simple PMOS.By this circuit is carried out small-signal analysis, the gain that can draw this circuit is:
Wherein, g
M1,2Be the mutual conductance of PMOS transistor Mp1 and Mp2, r
0It is the all-in resistance of output node.Can learn gain A by formula (1)
vLess than 1, for the analog input signal of analog to digital converter, input signal Vin becomes A through signal amplitude after front-end sampling holding circuit and the ultrahigh speed buffer
vVin has influenced the overall dynamics performance of analog-digital conversion process thereby made front end open loop sampling holding circuit and ultrahigh speed buffer.Fig. 3 shows a kind of electrical block diagram of automatic biasing ultrahigh speed buffer, and by this circuit is carried out small-signal analysis, the gain that can draw this circuit is:
Wherein, g
M1,2Be the mutual conductance of PMOS transistor Mp1 and Mp2, g
M3,4Be the mutual conductance of PMOS transistor Mp3 and Mp4, r
0It is the all-in resistance of output node; Can learn that by formula (2) this high-speed buffer has been realized unit gain.
But, traditional ultrahigh speed buffer since to the circuit gain of small-signal less than 1, make that the analog input signal loss is excessive; Though automatic biasing ultrahigh speed buffer has been realized unit gain, because dynamic bias PMOS transistor Mp3 and Mp4 will enter linear zone when operate as normal, make the dynamic property variation of this circuit, need to increase calibration circuit to improve the dynamic property of circuit, will reduce requirement like this front-end circuit dynamic property.
Summary of the invention
For solve existing high-speed buffer signal gain less than 1, the analog input signal loss is big and problem such as bad dynamic performance, the present invention proposes a kind of buffer based on source follower, described buffer comprises:
The pseudo-differential input stage is used to receive differential input signal;
The cross-couplings common-source stage links to each other with described pseudo-differential input stage, is used to form negative resistance, offsets the output resistance of buffer;
Current source links to each other with described pseudo-differential input stage, is used to provide the buffer branch current;
Capacitive load links to each other with described pseudo-differential input stage, is used for the output loading as buffer.
Described pseudo-differential input stage comprises the first transistor and transistor seconds; The grounded drain voltage of described the first transistor, the grid of described the first transistor connects first input end, and the source electrode of described the first transistor and substrate connect first output; The grounded drain voltage of described transistor seconds, the grid of described transistor seconds connects second input, and the source electrode of described second crystal and substrate connect second output.
Described cross-couplings common-source stage comprises the 3rd transistor and the 4th transistor; Described the 3rd transistor drain links to each other with described first output, and the described the 3rd transistorized grid links to each other with described second output, the described the 3rd transistorized source electrode and substrate earthed voltage; Described the 4th transistor drain links to each other with described second output, and the described the 4th transistorized grid links to each other with described first output, the described the 4th transistorized source electrode and substrate earthed voltage.
Described cross-couplings common-source stage comprises the 3rd transistor and the 4th transistor; Described the 3rd transistor drain links to each other with described first output, and the described the 3rd transistorized grid links to each other with described second output, and the described the 3rd transistorized source electrode and substrate connect supply voltage; Described the 4th transistor drain links to each other with described second output, and the described the 4th transistorized grid links to each other with described first output, and the described the 4th transistorized source electrode and substrate connect supply voltage.
Described current source comprises first current source and second current source; The input of described first current source links to each other with supply voltage, and the output of described first current source links to each other with described first output; The input of described second current source links to each other with supply voltage, and the output of described second current source links to each other with described second output.
Described capacitive load comprises first capacitive load and second capacitive load; One end of described first capacitive load links to each other with described first output, and the other end of described first capacitive load is received ground voltage; One end of described second capacitive load links to each other with described second output, and the other end of described second capacitive load is received ground voltage.
Described the first transistor and transistor seconds are the pmos type transistor.
Described the 3rd transistor and the 4th transistor are nmos type transistor.
Described the 3rd transistor and the 4th transistor are the pmos type transistor.
Beneficial effect: the present invention forms negative resistance by the cross-couplings common-source stage, and then offsets the output resistance of high-speed buffer, has realized the output of unit gain buffering; By theory analysis and simulating, verifying, the present invention has realized the buffer based on source follower of ultrahigh speed, the output of unit gain buffering and high dynamic characteristic.
Description of drawings
Fig. 1 is the circuit theory schematic diagram of AFE (analog front end) in the prior art all-parallel A/D converter;
Fig. 2 is the electrical block diagram of prior art tradition ultrahigh speed buffer;
Fig. 3 is the electrical block diagram of prior art automatic biasing ultrahigh speed buffer;
Fig. 4 is the electrical block diagram of the embodiment of the invention 1 based on the buffer of source follower;
Fig. 5 is the electrical block diagram of the embodiment of the invention 2 based on the buffer of source follower;
Fig. 6 is the transfer curve figure of the embodiment of the invention based on the buffer of source follower;
Fig. 7 is the dynamic characteristic figure of the embodiment of the invention based on the buffer of source follower.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
Referring to Fig. 4, the embodiment of the invention provides a kind of buffer based on source follower, and this buffer comprises:
The pseudo-differential input stage is used to receive differential input signal;
The cross-couplings common-source stage links to each other with the pseudo-differential input stage, is used to form negative resistance, offsets the output resistance of buffer;
Current source links to each other with the pseudo-differential input stage, is used to provide the buffer branch current;
Capacitive load links to each other with the pseudo-differential input stage, is used for the output loading as buffer.
Wherein, the pseudo-differential input stage comprises a PMOS transistor 110 (Mp1) and the 2nd PMOS transistor 111 (Mp2); The grounded drain voltage GND (141) of the one PMOS transistor 110, the grid of a PMOS transistor 110 connects first input end 102 (Vip), and the source electrode of a PMOS transistor 110 and substrate connect first output 106 (Vop); The grounded drain voltage GND (141) of the 2nd PMOS transistor 111, the grid of the 2nd PMOS transistor 111 connect second input 104 (Vin), and the source electrode of the 2nd PMOS transistor 111 and substrate connect second output 108 (Von).
Wherein, the cross-couplings common-source stage comprises the 3rd nmos pass transistor 112 (Mn3) and the 4th nmos pass transistor 113 (Mn4); The drain electrode of the 3rd nmos pass transistor 112 links to each other with first output 106, and the grid of the 3rd nmos pass transistor 112 links to each other with second output 108, the source electrode of the 3rd nmos pass transistor 112 and substrate earthed voltage GND (141); The drain electrode of the 4th nmos pass transistor 113 (Mn4) links to each other with second output 108, and the grid of the 4th nmos pass transistor 113 links to each other with first output 106, the source electrode of the 4th nmos pass transistor 113 and substrate earthed voltage GND (141).
Wherein, current source comprises first current source 122 (Ib) and second current source 121 (Ib); The input of first current source 122 links to each other with supply voltage VDD (142), and the output of first current source 122 links to each other with first output 106; The input of second current source 121 links to each other with supply voltage VDD (142), and the output of second current source 121 links to each other with second output 108.
Wherein, capacitive load comprises first capacitive load, 131 (C
L) and second capacitive load, 132 (C
L); One end of first capacitive load 131 links to each other with first output 106, and the other end of first capacitive load 131 is received ground voltage GND (141); One end of second capacitive load 132 links to each other with second output 108, and the other end of second capacitive load 132 is received ground voltage GND (141).
The cross-couplings common-source stage based in the buffer of source follower that present embodiment provides has formed negative resistance, thereby has offset the output resistance of buffer, has realized the output of unit gain buffering.
Referring to Fig. 5, the embodiment of the invention also provides another kind of buffer based on source follower, and described buffer comprises:
The pseudo-differential input stage is used to receive differential input signal;
The cross-couplings common-source stage links to each other with the pseudo-differential input stage, is used to form negative resistance, offsets the output resistance of buffer;
Current source links to each other with the pseudo-differential input stage, is used to provide the buffer branch current;
Capacitive load links to each other with the pseudo-differential input stage, is used for the output loading as buffer.
Wherein, the pseudo-differential input stage comprises a PMOS transistor 210 (Mp1) and the 2nd PMOS transistor 211 (Mp2); The grounded drain voltage GND (241) of the one PMOS transistor 210, the grid of a PMOS transistor 210 connects first input end 202 (Vip), and the source electrode of a PMOS transistor 210 and substrate connect first output 206 (Vop); The grounded drain voltage GND (241) of the 2nd PMOS transistor 211 (Mp2), the grid of the 2nd PMOS transistor 211 connect second input 204 (Vin), and the source electrode of the 2nd PMOS transistor 211 and substrate connect second output 208 (Von).
Wherein, the cross-couplings common-source stage comprises the 3rd PMOS transistor 212 (Mp3) and the 4th PMOS transistor 213 (Mp4); The drain electrode of the 3rd PMOS transistor 212 links to each other with first output 206, and the grid of the 3rd PMOS transistor 212 links to each other with second output 208, and the source electrode of the 3rd PMOS transistor 212 and substrate meet supply voltage VDD (242); The drain electrode of the 4th PMOS transistor 213 links to each other with second output 208, and the grid of the 4th PMOS transistor 213 links to each other with first output 206, and the source electrode of the 4th PMOS transistor 213 and substrate meet supply voltage VDD (242).
Wherein, current source comprises first current source 222 (Ib) and second current source 221 (Ib); The input of first current source 222 links to each other with supply voltage VDD (242), and the output of first current source 222 links to each other with first output 206; The input of second current source 221 links to each other with supply voltage VDD (242), and the output of second current source 221 links to each other with second output 208.
Wherein, capacitive load comprises first capacitive load, 231 (C
L) and second capacitive load, 232 (C
L); One end of first capacitive load 231 links to each other with first output 206, and the other end of first capacitive load 231 is received ground voltage GND (241); One end of second capacitive load 232 (Mn4) links to each other with second output 208, and the other end of second capacitive load 232 is received ground voltage GND (241).
The cross-couplings common-source stage based in the buffer of source follower that present embodiment provides has formed negative resistance, thereby has offset the output resistance of buffer, has realized the output of unit gain buffering.
For being described in further detail, the buffer based on source follower that the embodiment of the invention provides to realize that unit gain cushions output, carries out following quantitative analysis.As shown in Figure 4, the cross-couplings common-source stage forms negative resistance, offsets the output resistance of buffer.If only consider the principal element of influence buffering output transmission characteristic, ignore transistorized parasitic capacitance, can obtain the transfer function of embodiment of the invention buffer:
Wherein, g
M1,2Be the mutual conductance of PMOS transistor Mp1 and Mp2, g
M3,4Be the mutual conductance of nmos pass transistor Mn3 and Mn4, r
0Be the output node all-in resistance, by formula (3) as can be known this buffer realized unit gain.
Adopt the CMOS of SMIC (SMIC integrated circuit Manufacturing Co., Ltd)
The ultrahigh speed buffer that the mixed signal process simulation is shown in Figure 4 obtains the transfer curve figure of this ultrahigh speed buffer as shown in Figure 6, and the ordinate of this curve chart and abscissa are represented amplitude characteristic and correspondent frequency (Hz) respectively.By this curve chart as can be known this ultrahigh speed buffer realized unit gain buffering output, signal bandwidth output gain when 700MHz is 1, thereby has verified formula (3), has realized the output of unit gain buffering.
Adopt the CMOS of SMIC
Mixed signal technology is verified its dynamic property with open loop sampling holding circuit and ultrahigh speed buffer associative simulation.Sample frequency is 2GHz, and frequency input signal is 696.09375MHz, is applied among the 6bit 2GHz sample rate f lash ADC, requires the SFDR of open loop sampling holding circuit and ultrahigh speed buffer to be at least 55dB.Adopt HSPICE to carry out time-domain-simulation, do fft analysis at MATLAB then, as shown in Figure 7.At the 10mA electric current, under the 1.8V voltage, Spurious Free Dynamic Range (SFDR) can reach 57.79dB, and total harmonic distortion is-57.12dB.Under identical power consumption, the dynamic characteristic of traditional ultrahigh speed buffer can reach 58dB.Though automatic biasing ultrahigh speed buffer has been realized the output of unit gain buffering, its dynamic property makes its total harmonic distortion be-50dB because dynamic bias transistor work meeting enters linear zone.
The embodiment of the invention forms negative resistance by the cross-couplings common-source stage, and then offsets the output resistance of high-speed buffer, has realized the output of unit gain buffering; By theory analysis and simulating, verifying, the present invention has realized that ultrahigh speed (2GHz sample rate), unit gain cushion the buffer based on source follower of output (more than or equal to 1), high dynamic characteristic (57.79dB is applied in 6bit 2GHz sample rate f lash ADC).
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. the buffer based on source follower is characterized in that, described buffer comprises:
The pseudo-differential input stage is used to receive differential input signal;
The cross-couplings common-source stage links to each other with described pseudo-differential input stage, is used to form negative resistance, offsets the output resistance of buffer;
Current source links to each other with described pseudo-differential input stage, is used to provide the buffer branch current;
Capacitive load links to each other with described pseudo-differential input stage, is used for the output loading as buffer.
2. the buffer based on source follower as claimed in claim 1 is characterized in that, described pseudo-differential input stage comprises the first transistor and transistor seconds; The grounded drain voltage of described the first transistor, the grid of described the first transistor connects first input end, and the source electrode of described the first transistor and substrate connect first output; The grounded drain voltage of described transistor seconds, the grid of described transistor seconds connects second input, and the source electrode of described second crystal and substrate connect second output.
3. the buffer based on source follower as claimed in claim 2 is characterized in that, described cross-couplings common-source stage comprises the 3rd transistor and the 4th transistor; Described the 3rd transistor drain links to each other with described first output, and the described the 3rd transistorized grid links to each other with described second output, the described the 3rd transistorized source electrode and substrate earthed voltage; Described the 4th transistor drain links to each other with described second output, and the described the 4th transistorized grid links to each other with described first output, the described the 4th transistorized source electrode and substrate earthed voltage.
4. the buffer based on source follower as claimed in claim 2 is characterized in that, described cross-couplings common-source stage comprises the 3rd transistor and the 4th transistor; Described the 3rd transistor drain links to each other with described first output, and the described the 3rd transistorized grid links to each other with described second output, and the described the 3rd transistorized source electrode and substrate connect supply voltage; Described the 4th transistor drain links to each other with described second output, and the described the 4th transistorized grid links to each other with described first output, and the described the 4th transistorized source electrode and substrate connect supply voltage.
5. as claim 3 or 4 described buffers, it is characterized in that described current source comprises first current source and second current source based on source follower; The input of described first current source links to each other with supply voltage, and the output of described first current source links to each other with described first output; The input of described second current source links to each other with supply voltage, and the output of described second current source links to each other with described second output.
6. as claim 3 or 4 described buffers, it is characterized in that described capacitive load comprises first capacitive load and second capacitive load based on source follower; One end of described first capacitive load links to each other with described first output, and the other end of described first capacitive load is received ground voltage; One end of described second capacitive load links to each other with described second output, and the other end of described second capacitive load is received ground voltage.
7. the buffer based on source follower as claimed in claim 2 is characterized in that, described the first transistor and transistor seconds are the pmos type transistor.
8. the buffer based on source follower as claimed in claim 3 is characterized in that, described the 3rd transistor and the 4th transistor are nmos type transistor.
9. the buffer based on source follower as claimed in claim 4 is characterized in that, described the 3rd transistor and the 4th transistor are the pmos type transistor.
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| CN102522106A (en) * | 2011-12-13 | 2012-06-27 | 北京大学 | High-speed low-power WTA (winner-take-all) sensitive amplifier |
| CN102771052A (en) * | 2010-02-24 | 2012-11-07 | 德州仪器公司 | Source follower input buffer |
| CN102835025A (en) * | 2009-12-08 | 2012-12-19 | 黑沙技术有限公司 | Low output impedance RF amplifier |
| CN103107782A (en) * | 2011-11-14 | 2013-05-15 | 孙茂友 | High-gain front-arranged amplifier for electret electrochemical machining (ECM) microphone |
| CN103199848A (en) * | 2013-03-11 | 2013-07-10 | 香港中国模拟技术有限公司 | Source electrode follower based on PMOS transistor |
| CN103199849A (en) * | 2013-03-11 | 2013-07-10 | 香港中国模拟技术有限公司 | Source electrode follower based on deep N-well N-channel metal oxide semiconductor (NMOS) transistor |
| CN103490766A (en) * | 2013-08-29 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | High-speed high-precision source electrode follower circuit |
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| CN108627815A (en) * | 2017-03-21 | 2018-10-09 | 线性技术有限责任公司 | Unity gain buffer with 2 states |
| CN109194330A (en) * | 2018-08-27 | 2019-01-11 | 中国电子科技集团公司第二十四研究所 | buffer circuit and buffer |
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| CN110620552A (en) * | 2019-08-30 | 2019-12-27 | 苏州闻颂智能科技有限公司 | Linear voltage-controlled oscillator based on capacitance compensation technology |
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| CN115951750A (en) * | 2023-02-13 | 2023-04-11 | 集益威半导体(上海)有限公司 | Voltage buffer based on source follower |
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| CN103107782A (en) * | 2011-11-14 | 2013-05-15 | 孙茂友 | High-gain front-arranged amplifier for electret electrochemical machining (ECM) microphone |
| CN102522106A (en) * | 2011-12-13 | 2012-06-27 | 北京大学 | High-speed low-power WTA (winner-take-all) sensitive amplifier |
| CN103199849B (en) * | 2013-03-11 | 2016-05-11 | 芯锋宽泰科技（北京）有限公司 | Based on the source follower of dark N trap nmos pass transistor |
| CN103199848A (en) * | 2013-03-11 | 2013-07-10 | 香港中国模拟技术有限公司 | Source electrode follower based on PMOS transistor |
| CN103199849A (en) * | 2013-03-11 | 2013-07-10 | 香港中国模拟技术有限公司 | Source electrode follower based on deep N-well N-channel metal oxide semiconductor (NMOS) transistor |
| CN103490766A (en) * | 2013-08-29 | 2014-01-01 | 苏州苏尔达信息科技有限公司 | High-speed high-precision source electrode follower circuit |
| CN105322947A (en) * | 2014-07-11 | 2016-02-10 | 台湾积体电路制造股份有限公司 | Unity gain buffers and related method |
| CN105322947B (en) * | 2014-07-11 | 2019-05-07 | 台湾积体电路制造股份有限公司 | Unity gain buffer and correlation technique |
| CN108627815A (en) * | 2017-03-21 | 2018-10-09 | 线性技术有限责任公司 | Unity gain buffer with 2 states |
| CN108627815B (en) * | 2017-03-21 | 2022-09-27 | 亚德诺半导体国际无限责任公司 | Unity gain buffer with 2 state |
| CN109194330A (en) * | 2018-08-27 | 2019-01-11 | 中国电子科技集团公司第二十四研究所 | buffer circuit and buffer |
| CN109194330B (en) * | 2018-08-27 | 2020-08-11 | 中国电子科技集团公司第二十四研究所 | Buffer circuit and buffer |
| CN110380699A (en) * | 2019-07-29 | 2019-10-25 | 深圳市锐能微科技有限公司 | Input buffer, differential input buffer and integrated circuit |
| CN110620552A (en) * | 2019-08-30 | 2019-12-27 | 苏州闻颂智能科技有限公司 | Linear voltage-controlled oscillator based on capacitance compensation technology |
| CN112234948A (en) * | 2020-10-26 | 2021-01-15 | 成都华微电子科技有限公司 | High-speed high-linearity time-interleaved dynamic operational amplifier circuit |
| CN112234948B (en) * | 2020-10-26 | 2022-09-06 | 成都华微电子科技股份有限公司 | High-speed high-linearity time-interleaved dynamic operational amplifier circuit |
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