CN210052756U

CN210052756U - Chip structure

Info

Publication number: CN210052756U
Application number: CN201921159378.0U
Authority: CN
Inventors: 李祈昕; 燕英强; 曾昭烩; 胡川; 刘晓燕; 陈志涛
Original assignee: Guangdong Semiconductor Industry Technology Research Institute
Current assignee: Institute of Semiconductors of Guangdong Academy of Sciences
Priority date: 2019-07-22
Filing date: 2019-07-22
Publication date: 2020-02-11
Anticipated expiration: 2029-07-22

Abstract

The application provides a chip structure, and relates to the field of semiconductors. The chip structure comprises a light emitting layer, wherein a P electrode layer and an N electrode layer are arranged on one side of the light emitting layer, and a packaging layer is located on one side of the light emitting layer, a plurality of through holes are formed in the packaging layer, each through hole is communicated to the P electrode layer or the N electrode layer, a heat dissipation conductive medium is filled in each through hole, and the heat dissipation conductive medium is connected with the P electrode layer or the N electrode layer. The chip structure that this application provided has that the heat-sinking capability is better, the effect that the thermal resistance is lower.

Description

Chip structure

Technical Field

The application relates to the field of semiconductors, in particular to a chip structure.

Background

The ultraviolet LED light source has the advantages of small volume, no toxicity, environmental protection, long service life, low voltage and the like, has wide and important application prospect in various fields such as water purification, medical appliances, full-color display, optical storage, gas sensing and the like, and becomes a research hotspot in the field of solid-state semiconductors.

However, the current ultraviolet LED generally has a problem of poor heat dissipation capability of the chip.

SUMMERY OF THE UTILITY MODEL

An object of this application is to provide a chip architecture to solve the problem that ultraviolet LED chip heat-sinking capability is not good among the prior art.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

the embodiment of the utility model provides a chip structure, chip structure includes:

the light emitting diode comprises a light emitting layer, wherein a P electrode layer and an N electrode layer are arranged on one side of the light emitting layer;

and the packaging layer is positioned on one side of the light emitting layer and is provided with a plurality of through holes, each through hole is communicated to the P electrode layer or the N electrode layer, a heat dissipation conductive medium is filled in each through hole, and the heat dissipation conductive medium is connected with the P electrode layer or the N electrode layer.

Furthermore, the chip structure comprises pin pads, the pin pads are located on one side of the packaging layer, which is far away from the light-emitting layer, and each pin pad is connected with the heat dissipation conductive medium filled in the through holes.

Further, the chip structure further comprises a passivation layer, an optical material layer and an adhesive layer;

the passivation layer is positioned on one side of the light-emitting layer far away from the packaging layer;

the optical material layer is positioned on one side of the passivation layer, which is far away from the light-emitting layer, and the passivation layer is connected with the optical material layer through the bonding layer.

Further, the light emitting layer further comprises an N-type nitride layer, a multi-quantum well layer and a P-type layer, the N-type nitride layer, the multi-quantum well layer and the P-type layer are sequentially connected, the P-type electrode layer is connected with the P-type layer, and the N-type electrode layer is connected with the N-type nitride layer.

Further, the N-type nitride layer includes a first region and a second region, a plane of the second region is lower than a plane of the first region, the first region is sequentially connected to the mqw layer and the P-type layer, and the second region is connected to the N-electrode layer.

Further, the light emitting layer further comprises an N-type ohmic contact layer, a P-type ohmic contact layer, an N-type electrode connecting layer and a P-type electrode connecting layer, the P-type ohmic contact layer, the P-type electrode connecting layer and the P electrode layer are sequentially connected, and the N-type nitride layer, the N-type ohmic contact layer, the N-type electrode connecting layer and the N electrode layer are sequentially connected.

Furthermore, the chip structure further comprises a barrier metal layer, wherein the barrier metal layer is located between the P-type ohmic contact layer and the P-type electrode connecting layer.

Furthermore, insulating layers are filled among the N-type ohmic contact layer, the N-type electrode connecting layer, the P-type ohmic contact layer and the P-type electrode connecting layer.

Further, the P electrode layer and the N electrode layer are in the same plane on the side close to the packaging layer.

Further, the heat dissipation conductive medium includes copper.

Compared with the prior art, the method has the following beneficial effects:

the embodiment of the utility model provides a chip structure, this chip structure include the luminescent layer, and wherein, one side of luminescent layer is provided with P electrode layer and N electrode layer to and be located the encapsulated layer of luminescent layer one side, and wherein, the encapsulated layer is provided with a plurality of through-holes, and every through-hole intercommunication extremely P electrode layer or N electrode layer, and all pack in every through-hole has the heat dissipation conducting medium, and the heat dissipation conducting medium is connected with P electrode layer or N electrode layer. On one hand, the packaging layer is arranged on the luminous layer, so that the luminous layer is not required to be packaged again, and the cost is saved. On the other hand, as the heat dissipation and conductive medium is filled in the through hole, the heat dissipation and conductive medium can realize both the electric conduction and the heat conduction, so that the heat dissipation capability of the whole chip structure is better, and the thermal resistance is lower.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic cross-sectional view of a chip structure according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view of another chip structure according to an embodiment of the present disclosure.

In the figure: 100-chip architecture; 110-a light emitting layer; a 111-N type nitride layer; 112-multiple quantum well layer; a 113-P type layer; 114-P type ohmic contact layer; 115-barrier metal layer; 116-an N-type ohmic contact layer; 117 — a first insulating layer; 118-P type electrode connection layer; 119-N type electrode connection layer; 120-a second insulating layer; a 121-P electrode layer; 122-N electrode layer; 130-an encapsulation layer; 131-a through hole; 140-heat dissipating conductive media; 150-pin pad; 160-a passivation layer; 170-a layer of optical material; 180-adhesive layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

Referring to fig. 1, an embodiment of the present invention provides a chip structure 100, wherein the chip structure 100 includes a light emitting layer 110 and an encapsulation layer 130, and a P electrode layer 121 and an N electrode layer 122 are disposed on one side of the light emitting layer 110. The package layer 130 is located on one side of the light emitting layer 110, and the package layer 130 is provided with a plurality of through holes 131, each through hole 131 is communicated to the P electrode layer 121 or the N electrode layer 122, a heat dissipation conductive medium 140 is filled in each through hole 131, and the heat dissipation conductive medium 140 is connected with the P electrode layer 121 or the N electrode layer 122.

Through the utility model provides a chip structure 100, on the one hand, owing to set up encapsulating layer 130 on luminescent layer 110, consequently need not luminescent layer 110 and encapsulates once more, saved the cost. On the other hand, because the heat dissipation conductive medium 140 is filled in the through hole 131, the heat dissipation conductive medium 140 can achieve both the electric conduction and the heat conduction, so that the heat dissipation capability of the whole chip structure 100 is better and the thermal resistance is lower.

Specifically, referring to fig. 2, in the present embodiment, in order to more conveniently mount the package layer 130, a side of the P electrode layer 121 or the N electrode layer 122 close to the package layer 130 is in the same plane, that is, when the chip structure 100 is disposed as in fig. 1, the P electrode layer 121 and the N electrode layer 122 are as high as each other.

Further, the encapsulation layer 130 provided in the present embodiment is an insulating material layer, for example, the encapsulation layer 130 is made of epoxy resin, and the light emitting layer 110 is encapsulated by using an insulating material, wherein the structure including, but not limited to, the P electrode layer 121 and the N electrode layer 122 is encapsulated by using an insulating material, so as to form the encapsulation layer 130.

After encapsulation, in order to supply power to the P electrode layer 121 and the N electrode layer 122, a plurality of through holes 131 are provided in the encapsulation layer 130, and the through holes 131 are communicated with the P electrode layer 121 or the N electrode layer 122. For example, the through holes 131 are formed on the package layer 130 by photolithography, laser drilling, or the like.

After the through holes 131 are formed, the heat dissipation conductive medium 140 needs to be filled in each through hole 131, the heat dissipation conductive medium 140 is electrically connected to the P electrode layer 121 or the N electrode layer 122, and the heat dissipation conductive medium 140 is filled until the height of the heat dissipation conductive medium is equal to the height of the through hole 131, so that when the chip structure 100 needs to be used, wires can be respectively connected to the heat dissipation conductive medium 140 connected to the P electrode layer 121 and the heat dissipation conductive medium 140 connected to the N electrode layer 122, and the chip structure 100 can be used.

Moreover, because the heat dissipation conductive medium 140 is adopted, heat generated during the operation of the chip structure 100 can be discharged through the heat dissipation conductive medium 140, and a better heat dissipation capability effect of the chip structure 100 is achieved. That is, the heat dissipation conductive medium 140 provided in this embodiment is used as both an electrical connection channel and a thermal conduction channel, so that the heat dissipation capability of the entire chip structure 100 is better and the thermal resistance is lower.

The heat dissipation conductive medium 140 provided in this embodiment may be made of copper, which is used as a good conductor of electricity and heat, and can effectively achieve the effects of both electricity conduction and heat conduction. Of course, the heat dissipation conductive medium 140 can also be made of other materials, such as aluminum.

Further, the chip structure 100 provided in this embodiment includes the pin pads 150, the pin pads 150 are located on a side of the package layer 130 away from the light emitting layer 110, and each of the pin pads 150 is connected to the heat dissipation conductive medium 140 filled in the plurality of through holes 131. Through setting up pin pad 150, can realize realizing the effect of being connected with a plurality of pupils through a pin pad 150, it is more convenient when connecting wire, and luminous efficacy is stronger.

In addition, in order to make the light emitting effect of the chip structure 100 provided in this embodiment better, in the embodiment, the chip structure 100 further includes a passivation layer 160, an optical material layer 170, and an adhesive layer 180, wherein the passivation layer 160 is located on a side of the light emitting layer 110 away from the encapsulation layer 130, the optical material layer 170 is located on a side of the passivation layer 160 away from the light emitting layer 110, and the passivation layer 160 is connected to the optical material layer 170 through the adhesive layer 180. The optical material layer 170 provided in the present application includes a material that can transmit light, such as glass, and the adhesive layer 180 is bonded by using a material such as a tin-silver alloy. By arranging the passivation layer 160 and the optical material layer 170, the absorption of light in the light emitting process of the chip structure 100 can be reduced, and a better light emitting effect can be achieved.

In addition, in the process of epitaxially growing the light emitting layer 110, the buffer layer and the light emitting layer 110 are epitaxially grown on the substrate, and the encapsulation layer 130 is formed on one side of the light emitting layer 110. Then, the substrate is stripped, and the buffer layer is removed by a dry/wet etching process, and then the passivation layer 160 and the optical material layer 170 are formed on the side of the light emitting layer 110 away from the encapsulation layer 130. Therefore, by peeling the substrate and then fabricating the passivation layer 160 and the optical material layer 170, absorption of light from the substrate chip can be avoided.

Specifically, the light-emitting layer 110 includes an N-type nitride layer 111, a multiple quantum well layer 112, and a P-type layer 113, in which the N-type nitride layer 111, the multiple quantum well layer 112, and the P-type layer 113 are sequentially connected, a P-type electrode layer 121 is connected to the P-type layer 113, and an N-type electrode layer 122 is connected to the N-type nitride layer 111, and the effect of emitting light in the multiple quantum well layer 112 can be achieved by voltage excitation between the P-type electrode layer 121 and the N-type electrode layer 122.

Specifically, in the manufacturing process, a buffer layer, an N-type nitride layer 111, a multiple quantum well layer 112, and a P-type layer 113 are sequentially epitaxially grown on a substrate, where the substrate may be a sapphire substrate, the buffer layer is used to reduce lattice mismatch between the substrate and the N-type nitride layer 111, and the buffer layer may be a nitride buffer layer, for example, a GaN buffer layer. Further, N-type nitride layer 111 may be made of a material such as N-type AlGaN or N-type GaN, and P-type layer 113 may be made of a material such as P-type AlGaN or N-type GaN, and is not particularly limited again.

The N-type nitride layer 111 includes a first region and a second region, the plane of the second region is lower than the plane of the first region, the first region is connected to the mqw layer 112 and the P-type layer 113 in this order, and the second region is connected to the N-electrode layer 122. In this embodiment, after the N-type nitride layer 111, the multiple quantum well layer 112, and the P-type layer 113 are fabricated, the active region is defined by using a photolithography technique, and the P-type layer 113, the multiple quantum well layer 112, and the N-type nitride layer 111 with a partial thickness in a local region are removed by using dry etching or other processes, so that the entire N-type nitride layer 111 is divided into a first region and a second region, and the fabricated N-electrode layer 122 and the fabricated P-electrode layer 121 can be located on the same side of the N-type nitride layer 111, and the volume of the chip structure 100 is smaller.

In addition, in this embodiment, by etching a portion of the N-type nitride layer 111, it can be ensured that no other impurities exist between the electrode and the N-type nitride, and the connection effect is better.

Furthermore, the light emitting layer 110 further includes an N-type ohmic contact layer 116, a P-type ohmic contact layer 114, an N-type electrode connection layer 119, and a P-type electrode connection layer 118, the P-type layer 113, the P-type ohmic contact layer 114, the P-type electrode connection layer 118, and the P-type electrode layer 121 are sequentially connected, and the N-type nitride layer 111, the N-type ohmic contact layer 116, the N-type electrode connection layer 119, and the N-type electrode layer 122 are sequentially connected.

After etching part of the N-type nitride layer 111, cleaning and surface treatment are carried out on the surface of the P-type layer 113 by adopting an organic solvent, acid-base or dry etching process, then a layer of ohmic contact metal is deposited on the surface of the P-type layer 113 by adopting a magnetron sputtering or electron beam evaporation process, then the P-type ohmic contact layer 114 is manufactured by utilizing photoetching and corrosion work, and annealing is carried out to form P-ohmic contact.

Similarly, an N-ohm contact area is formed by adopting a photoetching process, a layer of N-ohm contact metal is deposited on the surface 3A of the N-AlGaN layer of the N-ohm contact area by utilizing a magnetron sputtering or electron beam evaporation process, an N-type ohm contact layer 116 is formed by a metal stripping process, finally, N-ohm contact is formed by annealing, and then a P-type electrode connecting layer 118 is manufactured.

Further, in order to prevent random diffusion of charges between the P-type ohmic contact layer 114 and the P-type electrode connection layer 118, the chip structure 100 provided by the present embodiment further includes a barrier metal layer 115. Specifically, a layer of barrier metal layer 115 is deposited on the surface of the P-type ohmic contact layer 114 by magnetron sputtering or electron beam evaporation, and then the excess metal is removed by photolithography and wet/dry etching, so that the barrier metal layer 115 covers the P-type ohmic contact layer 114.

Meanwhile, in order to fill a blank region between the N-type nitride layer 111 and the P-type layer 113 and to achieve isolation between the N-type nitride layer 111 and the P-type layer 113, an insulating layer is further filled between the N-type nitride layer 111 and the P-type layer 113. That is, the insulating layer is filled between the N-type ohmic contact layer 116 and the N-type electrode connection layer 119 and the P-type ohmic contact layer 114 and the P-type electrode connection layer 118. In this embodiment, the insulating layer includes a first insulating layer 117 and a second insulating layer 120.

Specifically, a first insulating layer 117 is deposited, for example, a SiO2 or/and Si3N4 insulating layer is deposited on the surfaces of the barrier metal layer 115, the N-type nitride layer 111, and the P-type layer 113, and the sidewall of the epitaxial layer removal region, and the first insulating layer 117 over the second region of the N-type nitride layer is subjected to photolithography to expose the surface of the N-type nitride layer 111, forming an N-type ohmic contact opening region; meanwhile, photolithography is performed above the P-type electrode connection layer 118 to expose the surface of the P-type electrode connection layer 118, and a P-type ohmic contact opening region is formed, wherein the N-type ohmic contact opening region and the P-type ohmic contact opening region are isolated by the first insulating layer 117.

Then, a layer of N-type ohmic contact metal is deposited in the N-type ohmic contact opening area by utilizing a magnetron sputtering or electron beam evaporation process, an N-type ohmic contact layer 116 is formed through a metal stripping process, and finally, N-type ohmic contact is formed through annealing.

Meanwhile, a P-electrode connection layer region and an N-electrode connection layer region are formed by a photolithography process, then connection layer metals are prepared on the barrier metal layer 115, the N-type ohmic contact layer 116 and a part of the first insulation layer 117 region in the electrode connection layer region by processes such as vacuum evaporation, magnetron sputtering or electroplating, and a P-type electrode connection layer 118 and an N-type electrode connection layer 119 are formed by a metal lift-off process. The sequential connection of the N-type nitride layer 111, the N-type ohmic contact layer 116, the N-type electrode connecting layer 119 and the N electrode layer 122 is realized, and the sequential connection of the P-type layer 113, the P-type ohmic contact layer 114, the P-type electrode connecting layer 118 and the P electrode layer 121 is realized.

Meanwhile, a second insulating layer 120, such as SiO2 or/and Si3N4, is deposited on the surfaces of the first insulating layer 117, the P-type electrode connecting layer 118, and the N-type electrode connecting layer 119, and a first opening and a second opening are formed on the second insulating layer 120 by using photolithography, wet or dry etching, laser drilling, and the like, wherein the first opening is connected to the surface of the P-type electrode connecting layer 118, the second opening is connected to the surface of the N-type electrode connecting layer 119, and the first opening and the second opening are isolated by the second insulating layer 120.

And then depositing electrode metal on the first opening, the second opening and a part of the second insulating layer 120 area by utilizing a vacuum evaporation process, a magnetron sputtering process, an electroplating process or the like, and forming a P electrode layer 121 and an N electrode layer 122 through a metal stripping process.

After the substrate and the buffer layer are peeled off, the surface of the N-type nitride layer 111 away from the package layer 130 is roughened, and the roughened light emitting surface can further enhance the light, so as to achieve the effect of higher light emitting efficiency.

Through the chip structure that this application provided, first aspect, its volume is littleer, and manufacturing process is simpler. In the prior art, when the substrate is stripped, the secondary substrate needs to be bonded, however, in the application, because the chip structure is thick, the secondary substrate does not need to be bonded for stripping the substrate, the manufacturing process is simplified, and the cost is saved. In a second aspect, a plurality of through holes are formed in the packaging layer, and the heat dissipation and conduction medium filled in the through holes can conduct electricity and conduct heat, so that the heat dissipation capability of the chip structure is better, and the thermal resistance is lower. In a third aspect, because the wafer level packaging is already completed by the chip structure provided by the application, the re-packaging is not needed, the cost is lower, the reliability is high, and the structure can realize the air-tight packaging. In the fourth aspect, the passivation layer and the optical material layer are manufactured on one side of the light emitting layer, which is far away from the packaging layer, so that the absorption of the substrate and the metal electrode on the light emitting of the chip structure can be avoided, meanwhile, the light emitting surface of the coarsening can further enhance the light, and the light emitting effect of the chip structure is better.

To sum up, the embodiment of the utility model provides a chip structure, this chip structure include the luminescent layer, and wherein, one side of luminescent layer is provided with P electrode layer and N electrode layer to and be located the encapsulated layer of luminescent layer one side, and wherein, the encapsulated layer is provided with a plurality of through-holes, and every through-hole intercommunication extremely P electrode layer or N electrode layer, and all pack in every through-hole has the heat dissipation conducting medium, and the heat dissipation conducting medium is connected with P electrode layer or N electrode layer. On one hand, the packaging layer is arranged on the luminous layer, so that the luminous layer is not required to be packaged again, and the cost is saved. On the other hand, as the heat dissipation and conductive medium is filled in the through hole, the heat dissipation and conductive medium can realize both the electric conduction and the heat conduction, so that the heat dissipation capability of the whole chip structure is better, and the thermal resistance is lower.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A chip structure, comprising:

2. The chip structure of claim 1, wherein the chip structure comprises pin pads located on a side of the encapsulation layer away from the light-emitting layer, and each of the pin pads is connected to a heat-dissipating conductive medium filled in the plurality of through holes.

3. The chip structure of claim 1, wherein the chip structure further comprises a passivation layer, an optical material layer, and an adhesive layer;

4. The chip structure according to claim 1, wherein the light emitting layer further comprises an N-type nitride layer, a mqw layer, and a P-type layer, the N-type nitride layer, the mqw layer, and the P-type layer are sequentially connected, and the P-electrode layer is connected to the P-type layer, and the N-electrode layer is connected to the N-type nitride layer.

5. The chip structure according to claim 4, wherein the N-type nitride layer comprises a first region and a second region, the second region having a lower plane than the first region, the first region being connected to the MQW layer and the P-type layer in this order, the second region being connected to the N-electrode layer.

6. The chip structure according to claim 4, wherein the light emitting layer further comprises an N-type ohmic contact layer, a P-type ohmic contact layer, an N-type electrode connection layer and a P-type electrode connection layer, the P-type ohmic contact layer, the P-type electrode connection layer and the P-electrode layer are sequentially connected, and the N-type nitride layer, the N-type ohmic contact layer, the N-type electrode connection layer and the N-electrode layer are sequentially connected.

7. The chip structure according to claim 6, further comprising a barrier metal layer between the P-type ohmic contact layer and the P-type electrode connection layer.

8. The chip structure according to claim 6, wherein insulating layers are filled between the N-type ohmic contact layer, the N-type electrode connection layer, the P-type ohmic contact layer and the P-type electrode connection layer.

9. The chip structure of claim 1, wherein the P electrode layer is in the same plane as a side of the N electrode layer adjacent to the encapsulation layer.

10. The chip structure of claim 1 wherein said heat sink conductive medium comprises copper.