CN210042351U

CN210042351U - PCB single board and PCB makeup

Info

Publication number: CN210042351U
Application number: CN201821745486.1U
Authority: CN
Inventors: 郎允森; 万声国; 赵平强
Original assignee: Weifang Goertek Electronics Co Ltd
Current assignee: Weifang Goertek Electronics Co Ltd
Priority date: 2018-10-26
Filing date: 2018-10-26
Publication date: 2020-02-07
Anticipated expiration: 2028-10-26

Abstract

The utility model discloses a PCB veneer and PCB makeup. The PCB makeup comprises: the PCB testing system comprises a plurality of PCBs and a process edge, wherein a first testing point corresponding to each PCB is arranged on the process edge, and the first testing point is connected with a testing connecting line on the first edge side of the corresponding PCB. The PCB single board comprises: the test connecting line is arranged on the first edge side of the PCB single plate, one end of the test connecting line is used for connecting an internal circuit of the PCB single plate, and the other end of the test connecting line is used for being connected with a first test point on a PCB makeup process edge formed by PCB single plate makeup. The utility model discloses a reasonable wiring sets up the test point at the technology edge of the PCB makeup that is formed by the PCB veneer makeup to reduced the degree of difficulty of device overall arrangement in the PCB veneer, also improved the test coverage rate of device and the test efficiency of production in the PCB veneer simultaneously, be favorable to selecting defective product, improve product reliability.

Description

PCB single board and PCB makeup

Technical Field

The utility model relates to a PCB veneer and PCB makeup.

Background

With the continuous improvement of the integration of electronic technology, the size of a Printed Circuit Board (PCB) is smaller and smaller, especially for consumer electronics, the available design space of the PCB is smaller and smaller, and more electronic devices need to be arranged in the limited PCB space, so that the smaller devices and the higher device arrangement density in the package are used to adapt to the pressure caused by the reduction of the PCB space. However, the small-package high-density PCB design brings difficulty to the test of the PCBA, and it becomes a challenge to increase the test coverage of the PCBA patch device to identify the production defect by adding more test points under the limit that the size of the PCB space is reduced and the size of the test probes cannot be reduced.

SUMMERY OF THE UTILITY MODEL

The utility model provides a PCB veneer and PCB makeup to the solution is in the PCB space of littleer and littleer, under the condition that PCB device overall arrangement density is higher and higher, adds the test point and improves the more difficult problem of test coverage of PCBA paster device.

An aspect of the present invention provides a PCB single board, including: the test connecting line is arranged on the first edge side of the PCB single plate, one end of the test connecting line is used for connecting an internal circuit of the PCB single plate, and the other end of the test connecting line is used for being connected with a first test point on a PCB makeup process edge formed by PCB single plate makeup.

Preferably, the distance between adjacent test connections is greater than 0.5 mm.

Preferably, the PCB single board further includes a second test point disposed on a side surface of the second edge of the PCB single board, the second test point includes a first pad located on the side surface of the PCB single board, a second pad located on the front surface of the PCB single board and connected to the front surface line, and a third pad located on the back surface of the PCB single board and connected to the back surface line, and the first pad is connected to the second pad and the third pad, respectively.

Preferably, a groove is formed in the side face of the PCB single board, the first pad of the second test point is arranged in the groove, and the depth of the groove is 0.2 mm.

Preferably, the length of the second pad on the front side of the single PCB is equal to the length of the groove, and the length of the third pad on the back side of the single PCB is equal to the length of the groove; the second pad and the third pad have a set width dimension, the width dimension is 0.3m, and the length of the groove is 1.6 mm.

Preferably, the groove is provided with a chamfer.

Preferably, the first pad, the second pad and the third pad are all solder mask-free copper foils.

Preferably, the thickness of the PCB single plate is greater than or equal to a set thickness dimension, and the thickness dimension is 0.6 mm.

Preferably, a plurality of second test points are arranged on the side surface of the PCB single board, and the distance between the edges of the adjacent second test points is greater than or equal to 0.2 mm.

The utility model discloses an aspect provides a PCB makeup, include: the PCB testing method comprises the steps that a plurality of PCB single boards and a process edge are arranged, a first testing point area corresponding to each PCB single board is arranged on the process edge, a first testing point is arranged in the first testing point area, and the first testing point is connected with a testing connecting line on the first edge side of the corresponding PCB single board.

The utility model discloses a reasonable wiring sets up the test point at the technology edge of the PCB makeup that is formed by the PCB veneer makeup to reduced the degree of difficulty of device overall arrangement in the PCB veneer, also improved the test coverage rate of device and the test efficiency of production in the PCB veneer simultaneously, be favorable to selecting defective product, improve product reliability.

Drawings

Fig. 1 is a schematic diagram of a layout of a PCB according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a front surface, a back surface and a side surface of a PCB single board according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a second test point pad according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is intended to be illustrative only and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The words "a", "an" and "the" and the like as used herein are also intended to include the meanings of "a plurality" and "the" unless the context clearly dictates otherwise. Furthermore, the terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.

Some block diagrams and/or flow diagrams are shown in the figures. It will be understood that some blocks of the block diagrams and/or flowchart illustrations, or combinations thereof, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the instructions, which execute via the processor, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.

Generally, test points (test points) on a PCB single board are arranged in the PCB single board, but due to the reduction of the space of the PCB single board and the increase of the density of the arranged devices, the diameter of the test point pads arranged on the PCB single board is smaller and smaller, and the distance between the test point pads is smaller and smaller, so that even in this way, more test points pads can not be added in the PCB single board to perform test safety coverage on all devices. Based on the circumstances, the embodiment of the utility model provides a set up the test line in PCB veneer edge side, when PCB veneer makeup forms the PCB makeup that has the technology limit, through will setting up the test point on the technology limit with be connected with the test line on the PCB veneer, carry out PCB makeup test.

The embodiment of the utility model provides an aspect provides a PCB makeup.

Fig. 1 is a schematic diagram of a PCB imposition shown in an embodiment of the present invention, as shown in fig. 1, the PCB imposition in the embodiment of the present invention includes: the PCB comprises a plurality of PCB single boards and process edges, such as PCB single boards A-F in figure 1, wherein an area defined by boundary lines corresponding to a label 1 in figure 1 is a PCB single board A, and an area 3 defined by boundary lines corresponding to a label 2 in figure 1 is a process edge area. In this embodiment, a first test point area corresponding to each PCB board is disposed on the process edge, a first test point 4 is disposed in the first test point area, and the first test point 4 is connected to

test connection lines

5 and 6 on the first edge side of the corresponding PCB board.

The number of the PCB single boards required by the PCB makeup is determined according to the specific size of the PCB single boards, the first test point on the process edge can be designed according to the distance between the specific test fixture test probes, and the process edge of the PCB makeup can be designed according to the production process of Surface Mount Technology (SMT).

In this embodiment, test points are set on the process edge of the makeup of the PCB, and after the test of the PCB is completed, board splitting processing is required, referring to the label 6 in fig. 1, and after board splitting, a copper exposure phenomenon occurs at the connecting line of the first test point and the appearance of the single board of the PCB.

The embodiment of the utility model provides a another aspect provides a PCB veneer.

Referring to fig. 1, the PCB board of the present embodiment includes a test connection line (a connection line denoted by reference numeral 6 in fig. 1) disposed at a first edge side of the PCB board, where one end of the test connection line is used to connect an internal circuit of the PCB board, and the other end of the test connection line is used to connect to a first test point on a PCB imposition process edge formed by a PCB board imposition.

In the embodiment, the test points are arranged on the process edge of the PCB makeup formed by the PCB single board makeup through reasonable wiring, so that the difficulty of the layout of the devices in the PCB single board is reduced, the test coverage rate of the devices in the PCB single board and the test efficiency of production are improved, defective products can be screened out, and the reliability of the products is improved.

In this embodiment, the test connection line is preferably a copper wire, and the test connection line should be as thin as possible, for example, the test connection line is 5mil, and the distance between adjacent test connection lines is greater than 0.5mm, so that even if there is a copper exposure phenomenon at the connection point with the first test point after board splitting, the short circuit problem will not be caused.

Generally, in a PCB single board after the splitting and the splitting of the PCB, a copper wire connected to a first test point has a wire end pigtail of about 0.2mm (the pigtail is related to a process of a PCB single board supplier, and in this embodiment, a ground GND network copper foil in the PCB single board needs to be arranged to be close to the appearance of the PCB).

In the embodiment, the design size of the process edge in fig. 1 is reduced by arranging the test point on the side surface of the PCB single board, so that the area utilization rate of the PCB single board is improved, and the product cost is reduced.

As shown in fig. 2-3, taking the PCB board a in fig. 1 as an example, the PCB board further includes a second test point (labeled as P in fig. 2) disposed on the upper portion of the side surface at the second edge of the PCB board a, where the first edge and the second edge of the PCB board are different edge positions; the second test point comprises a first pad (marked as Pm in fig. 3) located on the side surface of the PCB single board, a second pad (marked as Pt in fig. 3) located on the front surface of the PCB single board and connected with the front surface line, and a third pad (marked as Pb in fig. 3) located on the back surface of the PCB single board and connected with the back surface line, and the first pad is connected with the second pad and the third pad respectively.

By arranging the test points on the side face of the PCB single board, the area of the side face of the PCB single board can be effectively utilized, the effective design area of the front face and the back face of the PCB single board is increased, the size of the PCB makeup process edge can be reduced, and the production cost is saved.

In this embodiment, in order to prevent the test probes test probe from deviating on the line in the contact region, as shown in fig. 2, a groove is disposed on a side surface of the PCB board, and the first pad of the second test point is disposed in the groove.

In order to improve the manufacturability of the product, the chamfer of the groove is added in the embodiment, as shown in fig. 2, the size of the chamfer R2 is more than or equal to 0.4 mm.

The length of the second pad on the front surface of the PCB single board is equal to the length of the groove, the length of the third pad on the back surface of the PCB single board is equal to the length of the groove, the lengths of the second pad, the third pad and the groove in fig. 2 are denoted by a label C2, and the length dimension C2 is slightly different for different PCB processes. In one example, C2 is 1.6mm, the length dimension of the contactable area of the test probe testprobe on the first pad is a2 in combination with the chamfer R2 of the groove, the a2 dimension is preferably 1.0mm in consideration of the manufacturing deviation of the test jig, and the opening dimension B2 of the groove is set to 1.4mm for the chamfer dimension R2 of the groove in order to improve manufacturability of a2, F2 and R2.

In this embodiment, the second pad and the third pad have a set width, and the width of the second pad and the third pad is denoted by a label G2 in fig. 2, in order to improve the manufacturability of the product, in one example, the size of G2 is 0.3mm, different PCB single board processes are different, and the size of G2 is slightly different. In this embodiment, the thickness H of the PCB single board is greater than or equal to a set thickness dimension, for example, the dimension H is greater than or equal to 0.6 mm.

In this embodiment, the first bonding pad, the second bonding pad and the third bonding pad are all made of non-solder-resist copper foil, and as shown in fig. 2, the copper foil of the first bonding pad is attached to the inner surface of the whole groove.

Referring to fig. 2, in the present embodiment, a plurality of test points are disposed on a side surface of a PCB single board, and in order to improve manufacturability of a product, a distance D2 between edges of adjacent test points is greater than or equal to 0.2mm, or a center-to-center distance E2 between adjacent test points is greater than or equal to 1.8 mm.

The PCB single board provided by the embodiment can reduce the technical edge size of the PCB makeup by testing the connecting line on the PCB single board and arranging the test points on the side surface, thereby saving the production cost and ensuring that the PCB single board has more space for arranging electronic devices except the test points; in the embodiment, the PCBA test at the production end is possible by adding the test points on the process edge of the PCB makeup and/or the side face of the PCB single board in the limited PCB space, and the test coverage rate of the product of the production line is improved by adding more test points in the non-PCB design space.

In view of the above, it is only the specific embodiments of the present invention that other modifications and variations can be made by those skilled in the art based on the above-described embodiments in light of the above teachings. It should be understood by those skilled in the art that the foregoing detailed description is for the purpose of better explaining the present invention, and the scope of the present invention should be determined by the scope of the claims.

Claims

1. A PCB veneer, comprising: the test connecting line is arranged on the first edge side of the PCB single plate, one end of the test connecting line is used for connecting an internal circuit of the PCB single plate, and the other end of the test connecting line is used for being connected with a first test point on a PCB makeup process edge formed by the PCB single plate makeup.

2. The PCB board of claim 1, wherein a distance between adjacent test connection lines is greater than 0.5 mm.

3. The PCB board of claim 1, further comprising a second test point disposed on a side surface of a second edge of the PCB board, wherein the second test point includes a first pad located on the side surface of the PCB board, a second pad located on the front surface of the PCB board and connected to the front surface circuit, and a third pad located on the back surface of the PCB board and connected to the back surface circuit, and the first pad is connected to the second pad and the third pad, respectively.

4. The PCB single board of claim 3, wherein a groove is disposed on a side surface of the PCB single board, the first pad of the second test point is disposed in the groove, and a depth of the groove is 0.2 mm.

5. The PCB single board of claim 4, wherein the length of the second pad on the front side of the PCB single board is equal to the length of the groove, and the length of the third pad on the back side of the PCB single board is equal to the length of the groove; the second pad and the third pad have a set width dimension, the width dimension is 0.3m, and the groove length is 1.6 mm.

6. The PCB veneer of claim 4, wherein the groove is provided with a chamfer.

7. The PCB veneer according to any one of claims 3-6, wherein the first bonding pad, the second bonding pad and the third bonding pad are all solderless copper foils.

8. The PCB veneer of claim 7, wherein the thickness of the PCB veneer is greater than or equal to a set thickness dimension, and the thickness dimension is 0.6 mm.

9. The PCB single board of claim 7, wherein a plurality of the second test points are arranged on a side surface of the PCB single board, and a distance between edges of adjacent second test points is greater than or equal to 0.2 mm.

10. A PCB imposition, comprising: a plurality of PCB boards and a process edge according to any of claims 1 to 9, wherein a first test point area corresponding to each PCB board is disposed on the process edge, the first test point area is provided with a first test point, and the first test point is connected to a test connection line on the first edge side of the corresponding PCB board.