CN209982468U - High-speed instantaneous floating-point amplifier based on undersampling - Google Patents
High-speed instantaneous floating-point amplifier based on undersampling Download PDFInfo
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- CN209982468U CN209982468U CN201920845762.XU CN201920845762U CN209982468U CN 209982468 U CN209982468 U CN 209982468U CN 201920845762 U CN201920845762 U CN 201920845762U CN 209982468 U CN209982468 U CN 209982468U
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Abstract
The utility model discloses a high-speed instantaneous floating point amplifier based on undersampling, which comprises a pre-sampling circuit module, a sampling circuit module and an FPGA unit; the pre-sampling circuit is connected with the FPGA unit, and the sampling circuit is connected with the FPGA unit; the pre-sampling circuit comprises a reference voltage circuit module and a step code generation circuit module, wherein the reference voltage circuit module is connected with the step code generation circuit module; the sampling circuit comprises a plurality of channels of sampling circuits and a multi-channel AD, and the sampling circuit of each channel is provided with a programmable gain amplifier which is connected with the multi-channel AD. The utility model discloses break through instantaneous floating point amplifier's bottleneck, improved the enlarged speed of instantaneous floating point.
Description
Technical Field
The utility model relates to an amplifier technical field, more specifically relates to a high-speed instantaneous floating point amplifier based on undersampling.
Background
The instantaneous floating-point amplifier is based on programmable gain amplifier and based on the absolute value of the input signal, the gain of the amplifier is quickly detected and switched to regulate the optimal amplification gain of each sampling point, so as to achieve the purpose of optimal sampling effect, and the block diagram is as shown in fig. 1.
The amplifier of instantaneous floating point has already been very extensive application in the detection trade, especially apply in the detection field that the signal instantaneous dynamic range fluctuation is very big such as earthquake detection, therefore derive the instantaneous floating point amplifier that many different ways realize too, there are several similar schemes below.
1. A floating point type pile foundation nondestructive detector (CN 96212322);
2. parallel transient floating-point amplifiers (CN92110957), etc.
In the above schemes, the instantaneous floating-point amplifier is based on the gain controllable characteristic of the gain programmable amplifier, and adjusts the appropriate gain output in real time according to the magnitude of the input signal, and finally the sampling is carried out on the AD device.
In this technology, there are two key devices:
1) a programmable gain amplifier;
the programmable gain amplifier needs to consume a period of time after the gain is modified until the output signal is stable, the parameter is called the set-up time, and the set-up time can reach the microsecond (us) level at present.
2) An AD chip;
the sampling rate of the signal link has a direct relation with the sampling rate of the AD chip;
at present, the programmable gain amplifier can reach microsecond (us) level with the fastest establishment time, but the sampling rate of an AD conversion chip is also very much in nanosecond (ns) level.
According to the "barrel principle", the overall sampling rate of the system depends on the lowest rate device, and therefore the rate of the instantaneous floating-point amplifier depends entirely on the settling time of the programmable gain amplifier.
Therefore, the above scheme of the instantaneous floating-point amplifier has a common disadvantage that the sampling cannot break through the limitation of the setup time of the programmable gain amplifier.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art's not enough, provide a high-speed instantaneous floating point amplifier based on undersampling, broken through instantaneous floating point amplifier's bottleneck, further improved the enlarged speed of instantaneous floating point.
The purpose of the utility model is realized through the following technical scheme:
a high-speed instantaneous floating-point amplifier based on undersampling comprises a pre-sampling circuit module, a sampling circuit module and an FPGA unit; the pre-sampling circuit is connected with the FPGA unit, and the sampling circuit is connected with the FPGA unit; the pre-sampling circuit comprises a reference voltage circuit module and a step code generation circuit module, wherein the reference voltage circuit module is connected with the step code generation circuit module; the sampling circuit comprises a plurality of channels of sampling circuits and a multi-channel AD, the sampling circuit of each channel is provided with a programmable gain amplifier, and the programmable gain amplifier is connected with the multi-channel AD.
Furthermore, the sampling circuit comprises six channels of sampling circuits and a six-channel AD, and the sampling circuit of each channel in the six channels is provided with a programmable gain amplifier, and the six programmable gain amplifiers are respectively connected with the six-channel AD.
And furthermore, the sampling circuit comprises a signal input end and a pre-filter, wherein the signal input end is connected with the pre-filter, and the pre-filter is connected with the sampling circuit module.
Further, the step code generating circuit module comprises a same-direction comparator C1, a same-direction comparator C2, an inverse comparator C3 and an inverse comparator C4; a first end of the homodromous comparator C1 is connected with a first reference voltage output end, a second end of the homodromous comparator C1 is connected with a signal input end, and a third end of the homodromous comparator C1 is connected with the FPGA unit; a first end of the homodromous comparator C2 is connected with a second reference voltage output end, a second end of the homodromous comparator C2 is connected with a signal input end, and a third end of the homodromous comparator C2 is connected with the FPGA unit; the first end of the reverse comparator C3 is connected with the third reference voltage output end, the second end of the reverse comparator C3 is connected with the signal input end, and the third end of the reverse comparator C3 is connected with the FPGA unit; the first end of the inverting comparator C4 is connected with the fourth reference voltage output end, the second end of the inverting comparator C4 is connected with the signal input end, and the third end of the inverting comparator C4 is connected with the FPGA unit.
Further, the programmable gain amplifier includes AD 8253.
Further, the multichannel AD includes ADs 8365.
The utility model has the advantages that:
(1) the utility model discloses a sampling circuit module, sampling circuit module and FPGA unit etc. in advance use the undersampling technique, when signal frequency is higher than programmable gain amplifier's setup time promptly, utilize a plurality of passageways undersampling, inside FPGA, recombine a plurality of passageway data and integrate into a signal, can break through this bottleneck of instantaneous floating point amplifier, further improved the speed that instantaneous floating point was enlargied.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a block diagram of a transient floating-point amplifier.
Fig. 2 is a schematic block diagram of the present invention.
Fig. 3 is a circuit diagram of the pre-sampling of the present invention.
Fig. 4 is the AD sampling timing chart of the present invention.
Fig. 5 is a circuit diagram of the pre-sampling of the embodiment of the present invention.
Fig. 6 is a circuit diagram of the embodiment of the present invention.
Fig. 7 is a circuit diagram of an FPGA interface according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is described in further detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following description. All of the features disclosed in this specification, or all of the steps of a method or process so disclosed, may be combined in any combination, except combinations where mutually exclusive features and/or steps are used.
Any feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the invention. In other instances, well-known circuits, software, or methods have not been described in detail so as not to obscure the present invention.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Before describing the embodiments, some necessary terms need to be explained. For example:
if the terms "first," "second," etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a "first" element discussed below could also be termed a "second" element without departing from the teachings of the present invention. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
The various terms appearing in this application are used for the purpose of describing particular embodiments only and are not intended as limitations on the invention, except where the context clearly dictates otherwise, the singular is intended to include the plural as well.
When the terms "comprises" and/or "comprising" are used in this specification, these terms are intended to specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence and/or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Referring to fig. 1 to 7, an under-sampling based high-speed instantaneous floating-point amplifier includes a pre-sampling circuit module, a sampling circuit module and an FPGA unit; the pre-sampling circuit is connected with the FPGA unit, and the sampling circuit is connected with the FPGA unit; the pre-sampling circuit comprises a reference voltage circuit module and a step code generation circuit module, wherein the reference voltage circuit module is connected with the step code generation circuit module; the sampling circuit comprises a plurality of channels of sampling circuits and a multi-channel AD, the sampling circuit of each channel is provided with a programmable gain amplifier, and the programmable gain amplifier is connected with the multi-channel AD.
Furthermore, the sampling circuit comprises six channels of sampling circuits and a six-channel AD, and the sampling circuit of each channel in the six channels is provided with a programmable gain amplifier, and the six programmable gain amplifiers are respectively connected with the six-channel AD.
And furthermore, the sampling circuit comprises a signal input end and a pre-filter, wherein the signal input end is connected with the pre-filter, and the pre-filter is connected with the sampling circuit module.
Further, the step code generating circuit module comprises a same-direction comparator C1, a same-direction comparator C2, an inverse comparator C3 and an inverse comparator C4; a first end of the homodromous comparator C1 is connected with a first reference voltage output end, a second end of the homodromous comparator C1 is connected with a signal input end, and a third end of the homodromous comparator C1 is connected with the FPGA unit; a first end of the homodromous comparator C2 is connected with a second reference voltage output end, a second end of the homodromous comparator C2 is connected with a signal input end, and a third end of the homodromous comparator C2 is connected with the FPGA unit; the first end of the reverse comparator C3 is connected with the third reference voltage output end, the second end of the reverse comparator C3 is connected with the signal input end, and the third end of the reverse comparator C3 is connected with the FPGA unit; the first end of the inverting comparator C4 is connected with the fourth reference voltage output end, the second end of the inverting comparator C4 is connected with the signal input end, and the third end of the inverting comparator C4 is connected with the FPGA unit.
Further, the programmable gain amplifier includes AD 8253.
Further, the multichannel AD includes ADs 8365.
The utility model relates to an instantaneous floating point amplifier based on undersampling, its characteristics have broken through the rate bottleneck (programmable gain amplifier's the time limit of establishing) of conventional instantaneous floating point amplifier, utilize the undersampling method, and 6 passageway timesharing are to the input signal sampling, make instantaneous floating point amplifier's rate promote 6 times. The sampling circuit comprises 6 paths of instantaneous floating-point amplifiers and a 6-channel AD converter, and each path of instantaneous floating-point amplifier consists of an independently controllable programmable gain amplifier.
The utility model discloses signal processing circuit divides two parts, sampling circuit and sampling circuit in advance. 1) The pre-sampling circuit comprises a reference voltage circuit and a step code generating circuit. The reference voltage circuit provides several groups of standard voltages, the input signal needs to be compared with the several groups of standard voltages respectively, the range of the input signal is determined, and corresponding binary codes are output to provide the basis for setting the gain for the programmable gain amplifier.
The reference voltage is selected in combination with the gain value and the dynamic range of the AD. If the sampling range of the AD device is-U- + U (V), the gain can be controlled to be 1, 10, 100, 1000 times (the utility model is not used for 1000 times), in order to ensure that the signal does not exceed the sampling range of the AD device after the gain amplification,
TABLE 1 order code table
Note that: c1, C2 are homodromous comparators, C3 and C4 are inverse comparators.
2) Sampling circuit
The sampling circuit has 6 channels of sampling circuits and a 6 channel AD. The setup time of the original programmable gain amplifier is Δ T, and if only a single channel is used for sampling, the fastest sampling rate of the system is 1/Δ T, in the utility model, a piece of AD with 6 channels is used, and through program control, sampling is performed in time sharing for 6 channels, as shown in fig. 4.
The time instants in fig. 4 correspond to the sampling channels, as shown in table 2.
TABLE 2 timesharing sampling timetable
| Sampling channel | Time of day |
| Channel 1 | t1、t7 |
| Channel 2 | t2 |
| Channel 3 | t3 |
| Channel 4 | t4 |
| Channel 5 | t5 |
| Channel 6 | t6 |
The FPGA integrates the time-sharing sampled data together according to time to restore the original signal. In the mode, the original establishment time limit delta T is subjected to time-sharing sampling through 6 channels, and then subdivision is carried out for 6 equal parts, namely, the original sampling rate is improved by 6 times.
3) Processor circuit
The utility model discloses in use FPGA as the treater, its main effect as follows:
a) identifying a step code of an input signal;
b) outputting gain control according to the level code;
c) controlling an AD device to collect data;
d) integrating the collected data;
the utility model discloses in used the short programmable gain amplifier device AD8253 of settling time, its settling time can reach 1.8us, in the 1-1000 times enlargies programmable gain amplifier of the same rank, the faster level in prior art of settling time of this chip, and fig. 6 gives my settling time reference value in AD8253 manual.
AD8253 signal stabilizes at 0.001% settling time:
the sampling rate of the AD chip is selectable in nanosecond (ns) level, so the bottleneck of the instantaneous floating-point amplifier is still from the programmable gain amplifier.
The utility model discloses use the undersampling technique, when signal frequency is higher than programmable gain amplifier's the settling time, utilize a plurality of passageways undersampling, inside FPGA, be a signal with a plurality of channel data reorganization integrations, can break through this bottleneck of instantaneous floating point amplifier, further improved the speed that instantaneous floating point was enlargied.
Further, the utility model discloses in, the mode that uses the multichannel is the difference of essence with using among the background art in the multichannel, and "parallel instantaneous floating point amplifier" in the background art, when using the multichannel, finally only has an AD sampling channel, consequently though used the mode of multichannel, does not promote the bottleneck of instantaneous floating point amplifier through the timesharing sampling mode, does not utilize the data of the mode integration of undersampling a plurality of passageways yet. Therefore, the utility model discloses an on the current frame of instantaneous floating point amplifier, introduced the method of undersampling, used the instantaneous floating point amplifier circuit of a plurality of passageways, when signal frequency is higher than programmable gain amplifier's the settling time, made the timesharing sampling of the undersampling of multichannel, obtained the sampling data of each passageway to realize the data reorganization in software, restore original data.
The foregoing is illustrative of the preferred embodiments of the present invention, and it is to be understood that the invention is not limited to the precise forms disclosed herein, and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the invention as defined by the appended claims. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention, which is to be limited only by the claims appended hereto.
Claims (6)
1. A high-speed instantaneous floating-point amplifier based on undersampling is characterized by comprising a pre-sampling circuit module, a sampling circuit module and an FPGA unit; the pre-sampling circuit is connected with the FPGA unit, and the sampling circuit is connected with the FPGA unit; the pre-sampling circuit comprises a reference voltage circuit module and a step code generation circuit module, wherein the reference voltage circuit module is connected with the step code generation circuit module; the sampling circuit comprises a plurality of channels of sampling circuits and a multi-channel AD, the sampling circuit of each channel is provided with a programmable gain amplifier, and the programmable gain amplifier is connected with the multi-channel AD.
2. The under-sampling-based high-speed instantaneous floating-point amplifier according to claim 1, wherein the sampling circuit comprises six channels of sampling circuits and a six-channel AD, and the sampling circuit of each of the six channels is provided with a programmable gain amplifier, and the six programmable gain amplifiers are respectively connected with the six-channel AD.
3. A high-speed instantaneous floating-point amplifier based on undersampling according to claim 1 or 2, characterized by comprising a signal input and a pre-filter, said signal input being connected to the pre-filter, said pre-filter being connected to the sampling circuit block.
4. The undersampling-based high-speed instantaneous floating-point amplifier of claim 3, wherein the level code generation circuit block comprises a homodromous comparator C1, a homodromous comparator C2, an inverse comparator C3 and an inverse comparator C4; a first end of the homodromous comparator C1 is connected with a first reference voltage output end, a second end of the homodromous comparator C1 is connected with a signal input end, and a third end of the homodromous comparator C1 is connected with the FPGA unit; a first end of the homodromous comparator C2 is connected with a second reference voltage output end, a second end of the homodromous comparator C2 is connected with a signal input end, and a third end of the homodromous comparator C2 is connected with the FPGA unit; the first end of the reverse comparator C3 is connected with the third reference voltage output end, the second end of the reverse comparator C3 is connected with the signal input end, and the third end of the reverse comparator C3 is connected with the FPGA unit; the first end of the inverting comparator C4 is connected with the fourth reference voltage output end, the second end of the inverting comparator C4 is connected with the signal input end, and the third end of the inverting comparator C4 is connected with the FPGA unit.
5. The undersampling-based high-speed instantaneous floating-point amplifier of claim 4, in which the programmable gain amplifier comprises AD 8253.
6. The undersampling-based high-speed instantaneous floating-point amplifier of claim 1, in which the multi-channel AD comprises ADs 8365.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920845762.XU CN209982468U (en) | 2019-06-05 | 2019-06-05 | High-speed instantaneous floating-point amplifier based on undersampling |
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|---|---|---|---|
| CN201920845762.XU CN209982468U (en) | 2019-06-05 | 2019-06-05 | High-speed instantaneous floating-point amplifier based on undersampling |
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