CN209946880U

CN209946880U - Test board card for AI heterogeneous server

Info

Publication number: CN209946880U
Application number: CN201920976465.9U
Authority: CN
Inventors: 王安; 刘圣金; 孔祥涛
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-06-26
Filing date: 2019-06-26
Publication date: 2020-01-14
Anticipated expiration: 2029-06-26

Abstract

The utility model provides a test integrated circuit board for different structure server of AI, include: the CPLD control board card, the main chip, the clock module unit, the time sequence control unit, the PCIE Switch and the power supply unit; the CPLD control board, the main chip, the clock module unit and the time sequence control unit are all arranged on the main board card; the clock module unit, the time sequence control unit and the PCIE Switch are all in communication connection with the main chip. The utility model provides a test integrated circuit board for AI heterogeneous server, through simulation GPU integrated circuit board signal and then replace the GPU integrated circuit board to test when system link bandwidth speed tests, not only can reduce AI heterogeneous server test cost, can also reduce the complete machine test time of mill.

Description

Test board card for AI heterogeneous server

Technical Field

The utility model belongs to the technical field of the server, concretely relates to a test integrated circuit board for AI heterogeneous server.

Background

The AI heterogeneous server mainly operates through a large number of GPUs, and the GPUs have two forms at present, namely a standard full-height full-length GPU card form and a GPU board form. The system test of the whole factory machine needs to be matched with real GPU for testing, a research and development team needs to coordinate a batch of GPUs to the factory, each group of servers assembled in the factory after the system receives the GPU can assemble the GPU into the system for one complete machine test, the startup operation script is assembled, whether the link bandwidth speed of the whole system is normal or not is checked, and one set of GPU boards can carry out the assembly test of a plurality of complete machines.

PCIE is used as a protocol bus of high-speed communication in the hardware industry, is the most widely used one on high-speed communication equipment, the speed is gradually improved from PCIE 1.0 and 2.0 to the current PCIE4.0, and after a new generation protocol of PCIE is customized and released in the association, each factory and manufacturer starts to carry out pre-research design, and designs products in advance to occupy the market. PCIE is used as an interface of the current high-speed interconnection and applied to various aspects of servers, NVIDIA is used as a leading company of a GPU, the GPU board in the form of a complete machine is the mainstream application of the current AI server, and one GPU board is expensive and reaches millions.

The GPU card is interconnected with the mainboard through a standard golden finger, the GPU board is connected with the mainboard through an ExaMAX high-density connector, the golden finger and the Slot groove can be normally used for dozens of times of effective plugging, the ExaMAX connector is high in density, the manufacturer specification of the effective plugging times is only dozens of times, if the connector is easily damaged by excessive plugging, one GPU board is high in price, two thirds of cost of the whole server is occupied, the research and development cost is increased by connecting the damaged GPU boards, in addition, the GPU boards are up to dozens of jin, and inconvenience is brought to corresponding transportation and installation. For the bandwidth rate check of the PCIE link, the check is performed in a windows system or a LINUX system, and therefore the check needs to be performed with an operating system, which requires a long time for entering the system, and is tedious in operation.

SUMMERY OF THE UTILITY MODEL

The above-mentioned not enough to prior art, the utility model provides a test integrated circuit board for AI heterogeneous server to solve above-mentioned technical problem.

The utility model provides a test integrated circuit board for different structure server of AI, include: the CPLD control board card, the main chip, the clock module unit, the time sequence control unit, the PCIE Switch and the power supply unit; the CPLD control board, the main chip, the clock module unit and the time sequence control unit are all arranged on the main board card; the clock module unit, the time sequence control unit and the PCIE switch are all in communication connection with the main chip.

In one embodiment of the present application, the timing control unit controls power-on and timing logic of the board using the CPLD.

In one embodiment of the present application, the power supply unit includes a power supply and a VR power supply module, the power supply is a 12V power supply from the home control board end; and the VR power supply module converts the electric signal provided by the power supply into an electric signal required by the main chip.

In one embodiment of the present application, the test board uses 4 upstream ports.

In one embodiment of the present application, the master chip is a PEX88096 chip.

In an embodiment of the present application, the test board is provided with two PCIE switches, and each PCIE Switch supports outputting 4 paths of X16.

In an embodiment of the present application, the PCIE Switch is interconnected with the Host terminal through an ExaMAX high-density connector.

In an embodiment of the present application, the PCIE Switch is connected to the RJ45 network port through an external PHY chip.

The utility model has the advantages that,

the utility model provides a test integrated circuit board for different structure server of AI through set up CPLE control integrated circuit board, main chip, clock module unit, sequential control unit, PCIE Switch and power supply unit on main integrated circuit board, makes this test integrated circuit board can simulate the GPU integrated circuit board, when carrying out system's link bandwidth speed test, need not practical GPU integrated circuit board, can test. The utility model provides a test integrated circuit board for AI heterogeneous server, through simulation GPU integrated circuit board signal and then replace the GPU integrated circuit board to test when system link bandwidth speed tests, not only can reduce AI heterogeneous server test cost, can also reduce the complete machine test time of mill.

Furthermore, the utility model relates to a principle is reliable, and simple structure has very extensive application prospect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of the testing principle of the apparatus of one embodiment of the present application;

Detailed Description

In order to make the technical solutions in the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.

It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict. In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Example 1

Referring to fig. 1, the present embodiment provides a test board for an AI heterogeneous server, including: the CPLD control board card, the main chip, the clock module unit, the time sequence control unit, the PCIE Switch and the power supply unit; the CPLD control board card, the main chip, the clock module unit and the time sequence control unit are all arranged on the main board card; the clock module unit, the time sequence control unit and the PCIE Switch are all in communication connection with the main chip. The test board card uses 4 uplink ports as the connection of the analog GPU card.

In test application, the test board is connected with the CPU through an uplink port and is connected with the Host end through the PCIE Switch. After connection is ready, the test board card simulates the GPU board card to send GPU simulation data to a CPU (local end), and the CPU controls the PCIE switch to transmit the data to the Host end. The Pcie Switch is provided with special link diagnosis and signal quality test software at a PC (far end), and only needs to connect the board card and the PC through a corresponding cable, so that the bandwidth rate of the link, the eye diagram and the error rate of the signal can be graphically checked, and the Pcie Switch is convenient and rapid to operate.

Example 2

The embodiment provides a test board card for an AI heterogeneous server, wherein a clock module unit, a power module unit, a timing control unit and a CPLD control board card are arranged on a main board card. The board card is powered by a 12V power supply from a board making end, then power conversion is carried out through a VR power supply module on the board card, the power supply is converted into a power supply required by a PEX88096 main chip, the main chip can reach 4.0 speed by adopting a PEX88096 chip PCIE, the PCIE link rapid diagnosis test can be compatible with PCIE 1.0 to 4.0, and the bandwidth, the speed and the signal quality of the link can be diagnosed. The time sequence control unit controls the electrification and time sequence logic of the board card by using the CPLD, and can flexibly change according to requirements. 88096 is an PCIE SWITCH chip supporting PCIE4.0 speed, the board supports 4 uplink ports at maximum, each port is 16Lane PCIE, and the design uses 4 uplink ports as connections of the analog GPU card. The Pcie Switch is provided with special link diagnosis and signal quality test software at the PC end, and the board card and the PC are connected only through corresponding cables, so that the bandwidth rate of the link, the eye pattern and the error rate of the signal can be graphically checked, and the Pcie Switch is convenient and quick to operate.

The board card uses two PCIE4.0SWITCH, each SWITCH supports outputting 4 paths of X16, each path is interconnected with a Host end through an ExaMAX high-density connector, and the SWITCH supports remote network management and local UART management. And remote management, wherein the Switch is connected with an RJ45 network port after being externally connected with a PHY chip. The network management supports a plurality of modes, and can support a plurality of modes, including static IP configuration and DHCP configuration. The static management is configured under UART by commanding ipconfig static < IP > < Subnet > < Gateway > and the dynamic IP acquisition is configured by ipconfig dhcp _ auto.

Although the present invention has been described in detail by referring to the drawings in conjunction with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and substance of the present invention, and these modifications or substitutions are intended to be within the scope of the present invention/any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A test board card for an AI heterogeneous server, comprising: the CPLD control board card, the main chip, the clock module unit, the time sequence control unit, the PCIE Switch and the power supply unit; the CPLD control board, the main chip, the clock module unit and the time sequence control unit are all arranged on the main board card; the clock module unit, the time sequence control unit and the PCIE Switch are all in communication connection with the main chip.

2. The test board for the AI heterogeneous servers of claim 1, wherein the timing control unit controls power-on and timing logic of the board using a CPLD.

3. The test board card for the AI heterogeneous server of claim 1, wherein the power supply unit comprises a power supply and a VR power supply module, the power supply being a 12V power supply from a home control board end; and the VR power supply module converts the electric signal provided by the power supply into an electric signal required by the main chip.

4. The test board for the AI heterogeneous servers of claim 1, wherein the test board uses 4 upstream ports.

5. The test board for the AI heterogeneous servers of claim 1, wherein the master chip is a PEX88096 chip.

6. The test board for the AI heterogeneous server of claim 1, wherein the test board is provided with two PCIE switches, and each PCIE Switch supports output of 4-way X16.

7. The test board for the AI heterogeneous server of claim 6, wherein the pcie switch is interconnected with the Host terminal through an ExaMAX high-density connector.

8. The test board for the AI heterogeneous server of claim 6, wherein the pcie switch is connected to the RJ45 port through an external PHY chip.