CN209946729U - Quick response type low dropout regulator - Google Patents
Quick response type low dropout regulator Download PDFInfo
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- CN209946729U CN209946729U CN201921117990.1U CN201921117990U CN209946729U CN 209946729 U CN209946729 U CN 209946729U CN 201921117990 U CN201921117990 U CN 201921117990U CN 209946729 U CN209946729 U CN 209946729U
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Abstract
The utility model relates to a quick response type low dropout linear regulator, which comprises a low dropout linear regulator body; the low dropout linear regulator body comprises an operational amplifier AMP, and the output end of the operational amplifier AMP is connected with the grid end of a power tube MP 1; the transient response enhancement module is in adaptive connection with the operational amplifier AMP, and when the load current of the low dropout linear regulator body jumps from light load to heavy load or from heavy load to light load, the transient response enhancement module and the operational amplifier AMP are matched to increase the driving current Isr loaded to the gate terminal of the power tube MP1 by the operational amplifier AMP so as to reduce sudden change of the output voltage of the low dropout linear regulator body caused by sudden load change. The utility model discloses can strengthen LDO's transient response, the load is when jumping in the short time for LDO's output can be more stable, and the great upper and lower sudden change that arouses along with the load change of alleviating the output improves the stability of low dropout linear voltage regulator.
Description
Technical Field
The utility model relates to a stabiliser, especially a quick response type low dropout regulator belong to the technical field of low dropout regulator.
Background
As shown in fig. 1, the conventional low dropout regulator (LDO) includes a reference power supply and an operational amplifier AMP, the reference voltage provides a reference voltage Vref required by the operational amplifier AMP, MP1 is a PMOS power transistor, a resistor R1 and a resistor R2 are voltage dividing resistors, a resistor R3 is a compensation resistor, a capacitor C1 is a compensation capacitor, a capacitor CAP is a load capacitor, and Vout is an output of the entire LDO (i.e., the circuit schematic diagram of the low dropout regulator body in the following description).
As shown in FIG. 2, the transient response performance of LDO includes response time (Δ t)1+Δt2/Δt3+Δt4) Voltage overshoot (Δ V)3) And undershoot voltage (Δ V)tr-max) (ii) a The specific corresponding expression is:
ΔVtr-max≈Iload-max*Δt1/(CL+Cb)+ΔVesr (1)
ΔV3≈Iload-max*Δt3/(CL+Cb)+ΔVesr
≈Iload-max/(CL+Cb)*BWcl+ΔVesr (2)
Δt1≈1/BWcl+tsr＝1/BWcl+Cpar*ΔVpar/Isr (3)
Δt2≈(ΔVtr-max-ΔV2)*(CL+Cb)/Iload-max(4)
Δt3≈1/BWcl (5)
Δt4≈(CL+Cb)*(ΔV3-ΔVesr)/Ipull-down(6)
wherein, Iload-maxIs the maximum load current, CL is the output capacitance (i.e., the load capacitance CAP) and Cb is the outputThe bypass capacitance at the end, BWcl, is the closed loop bandwidth of the loop, Cpar is the parasitic capacitance of the gate of the power transistor MP1, Δ Vpar is the voltage variation on the parasitic capacitance Cpar, Δ Vesr is the voltage variation on the series equivalent resistance of the output capacitor, and Isr is the driving current at the front end of the gate of the power transistor MP1 (the loop bandwidth can be increased when the driving current Isr is increased). I ispull-downIs the pull-down current on the feedback resistor, tsr is the slew rate time of the parasitic capacitance Cpar, Δ V2The voltage difference of the output voltage is corresponding to the LDO under light load and heavy load. Since there is no off-chip capacitor structure, Δ Vesr takes zero.
In combination with the formula, to reduce Δ t1And Δ t3The loop bandwidth and the drive current Isr of the gate of the power transistor PM1 may be increased. And Δ t2Is determined by the time required for the power tube MP1 to fill the load capacitor CAP and the phase margin of the open loop frequency response, at4Is determined by the current on the feedback resistor. Overshoot voltage Δ V3And undershoot voltage Δ Vtr-maxIs mainly composed of Δ t1，Δt3And Isr decision.
When the load current of the LDO jumps from light load to heavy load in a short time, because the gate voltage of the power tube MP1 cannot respond to the reduction immediately, the load capacitor CAP provides the current needed by the load end, thereby causing the output voltage of the LDO to reduce; when the gate voltage of the power transistor MP1 decreases sufficiently to provide the load current, the output voltage of the LDO increases to the normal value.
When the LDO jumps from a heavy load to a light load, the gate voltage of the power tube MP1 cannot respond to the rise immediately, so that the output voltage of the LDO rises first and then falls. The output voltage of the LDO drops too low, which causes the power supply to be in intermittent power failure, and the output voltage becomes high, which causes the output voltage to be in an overvoltage state.
Disclosure of Invention
The utility model aims at overcoming the not enough of existence among the prior art, provide a quick response type low dropout linear regulator, its transient response that can strengthen LDO, when the load jumps in the short time for the output of LDO can be more stable, and the great upper and lower sudden change that the output that alleviates arouses along with the load change improves the stability of low dropout linear regulator.
According to the technical scheme provided by the utility model, the rapid response type low dropout regulator comprises a low dropout regulator body; the low dropout linear regulator body comprises an operational amplifier AMP, and the output end of the operational amplifier AMP is connected with the grid end of a power tube MP 1;
the transient response enhancement module is in adaptive connection with the operational amplifier AMP, and when the load current of the low dropout linear regulator body jumps from light load to heavy load or from heavy load to light load, the transient response enhancement module and the operational amplifier AMP are matched to increase the driving current Isr loaded to the gate terminal of the power tube MP1 by the operational amplifier AMP so as to reduce sudden change of the output voltage of the low dropout linear regulator body caused by load sudden change.
The low dropout linear regulator body further comprises a reference power supply, a reference voltage Vref at the output end of the reference power supply is connected with the inverting end of the operational amplifier AMP, the source end of the power tube MP1 and the positive power end of the operational amplifier AMP are connected with a voltage VDD, the drain end of the power tube MP1 is connected with one end of a resistor R1, one end of a resistor R3 and one end of a load capacitor CAP, the other end of the load capacitor CAP is grounded, the other end of a resistor R3 is connected with one end of a capacitor C1, the other end of a capacitor C1 is connected with the inverting end of the operational amplifier AMP, the other end of a resistor R1 and one end of a resistor R2, and the other end of the resistor R36;
the transient response enhancement module simultaneously receives a reference voltage Vref loaded to the inverting terminal of the operational amplifier AMP and a feedback voltage Vfb loaded to the non-inverting terminal of the operational amplifier AMP, and the output terminal of the transient response enhancement module is connected with the operational amplifier AMP.
The operational amplifier AMP comprises a PMOS tube MP2 and a PMOS tube MP3, a source terminal of the PMOS tube MP2 and a source terminal of the PMOS tube MP3 are connected with a voltage VDD, a gate terminal of the PMOS tube MP2 is connected with a source terminal of the PMOS tube MP2, a drain terminal of the NMOS tube MN1 and a gate terminal of the PMOS tube MP3, a gate terminal of the NMOS tube MN1 receives a feedback voltage Vfb, a drain terminal of the PMOS tube MP3 is connected with a drain terminal of the NMOS tube MN2, and a gate terminal of the NMOS tube MN2 receives a reference voltage Vref;
the source terminal of the NMOS transistor MN1, the source terminal of the NMOS transistor MN2, and the drain terminal of the NMOS transistor MN3 are connected, the gate terminal of the NMOS transistor MN3 receives the voltage Vb output by the reference power supply, the source terminal of the NMOS transistor MN3, the output terminal of the transient response enhancement module, and the drain terminal of the NMOS transistor MN4 are connected, the gate terminal of the NMOS transistor MN4, the gate terminal of the NMOS transistor MN5, and the drain terminal of the NMOS transistor MN5 are connected, the source terminal of the NMOS transistor MN5, and the source terminal of the NMOS transistor MN4 are grounded, the drain terminal of the NMOS transistor MN5 further receives the reference current Ibias generated by the reference power supply, and the drain terminal of the PMOS transistor MP3, and the drain terminal of the NMOS transistor MN2 are connected to form the output terminal vo.
The transient response enhancement module comprises a hysteresis comparator COMP1 and a hysteresis comparator COMP2, wherein the inverting terminal of the hysteresis comparator COMP1 receives a reference voltage Vref, and the non-inverting terminal of the hysteresis comparator COMP1 receives a feedback voltage Vfb; an inverting terminal of the hysteresis comparator CMOP2 receives a feedback voltage Vfb, a non-inverting terminal of the hysteresis comparator COMP2 receives a reference voltage Vref, a positive power terminal of the hysteresis comparator COMP1 and a positive power terminal of the hysteresis comparator COMP2 are both connected with a voltage VDD, and a negative power terminal of the hysteresis comparator COMP1 and a negative power terminal of the hysteresis comparator COMP2 are both grounded;
the output end of a hysteresis comparator COMP1 is connected with the gate end of an NMOS tube MN6, the output end of a hysteresis comparator COMP2 is connected with the gate end of the NMOS tube MN7, the source end of the NMOS tube MN6 and the source base of the NMOS tube MN7 are grounded, the drain end of the NMOS tube MN6 is connected with one end of a resistor R5, the drain end of the NMOS tube MN7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the other end of a resistor R5, and the other end of the resistor R4 is also connected with the source end of the NMOS tube MN3 and the drain end of the NMOS tube MN 4.
The utility model has the advantages that: when the load current of the low dropout linear regulator body jumps from light load to heavy load or from heavy load to light load, the transient response enhancement module and the operational amplifier AMP are matched to increase the driving current Isr loaded to the grid terminal of the power tube MP1 by the operational amplifier AMP so as to reduce sudden change of the output voltage of the low dropout linear regulator body caused by the sudden change of the load, thereby enhancing the transient response of the LDO.
Drawings
Fig. 1 is a schematic circuit diagram of a conventional low dropout regulator.
Fig. 2 is a schematic diagram of the output voltage variation of the conventional low dropout regulator when the load current jumps.
Fig. 3 is a schematic circuit diagram of the present invention.
Fig. 4 is a schematic circuit diagram of the operational amplifier AMP of the present invention.
Fig. 5 is a schematic circuit diagram of the transient response enhancement module of the present invention.
Detailed Description
The invention is further described with reference to the following specific drawings and examples.
As shown in fig. 3: in order to enhance the transient response of the LDO, when the load jumps in a short time, the output of the LDO is more stable, the up-down sudden change of the output caused by the change of the load is greatly relieved, and the stability of the low dropout linear regulator is improved; the low dropout linear regulator body comprises an operational amplifier AMP, and the output end of the operational amplifier AMP is connected with the grid end of a power tube MP 1;
the transient response enhancement module is in adaptive connection with the operational amplifier AMP, and when the load current of the low dropout linear regulator body jumps from light load to heavy load or from heavy load to light load, the transient response enhancement module and the operational amplifier AMP are matched to increase the driving current Isr loaded to the gate terminal of the power tube MP1 by the operational amplifier AMP so as to reduce sudden change of the output voltage of the low dropout linear regulator body caused by load sudden change.
Specifically, the low dropout regulator may adopt a conventional circuit form, and the specific working principle and process of the low dropout regulator are well known to those skilled in the art and will not be described herein again. The low dropout regulator comprises an operational Amplifier (AMP) and a power tube (MP 1), wherein the output end of the operational Amplifier (AMP) is connected with the gate end of the power tube (MP 1), and the power tube (MP 1) is a PMOS tube.
The embodiment of the utility model provides an in, operational amplifier AMP still is connected with transient response reinforcing module, can strengthen the transient response of low dropout linear regulator body through transient response reinforcing module, jump to the heavy load or jump to the light load from the heavy load at the load current of low dropout linear regulator body promptly, can increase the drive current Isr that operational amplifier AMP loaded to power tube MP1 gate terminal through transient response reinforcing module and operational amplifier AMP cooperation, known by the background art, behind the drive current Isr of increase power tube MP 1's gate terminal, can increase the loop bandwidth, thereby can reduce the sudden change of low dropout linear regulator body output voltage, thereby can improve the stability of low dropout linear regulator.
As shown in fig. 1 and fig. 3, the low dropout regulator body further includes a reference power supply, a reference voltage Vref at an output end of the reference power supply is connected to an inverting terminal of the operational amplifier AMP, a source terminal of the power transistor MP1 and a positive power terminal of the operational amplifier AMP are connected to the voltage VDD, a drain terminal of the power transistor MP1 is connected to one end of the resistor R1, one end of the resistor R3, and one end of the load capacitor CAP, the other end of the load capacitor CAP is grounded, the other end of the resistor R3 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to a non-inverting terminal of the operational amplifier AMP, the other end of the resistor R1, and one end of the resistor R2, and the other end of the;
the transient response enhancement module simultaneously receives a reference voltage Vref loaded to the inverting terminal of the operational amplifier AMP and a feedback voltage Vfb loaded to the non-inverting terminal of the operational amplifier AMP, and the output terminal of the transient response enhancement module is connected with the operational amplifier AMP.
The embodiment of the utility model provides an in, reference power supply can adopt current commonly used circuit form, and reference power supply can produce reference voltage Vref, and the inverting terminal of operational amplifier AMP is connected with a reference power supply's output to can receive the reference voltage Vref that reference power supply produced, power VDD can provide the required voltage of operational amplifier AMP work. The specific magnitude of the reference voltage Vref is generated by a reference power supply as required, and is well known in the art and will not be described herein. The input end of the transient response enhancement module needs to receive the reference voltage Vref and the feedback voltage Vfb loaded to the non-inverting end of the operational amplifier AMP at the same time, and the output end of the transient response enhancement module is connected with the operational amplifier AMP. Specifically, the drain terminal of the power transistor MP1, the resistor R3, the resistor R1, and the load capacitor CAP are connected to each other to form the output terminal Vout of the entire low dropout linear regulator; after the resistor R1, the resistor R2, the resistor R3 and the capacitor C1 are matched and connected with the non-inverting terminal of the operational amplifier AMP, the feedback voltage Vfb loaded to the non-inverting terminal of the operational amplifier AMP can be obtained.
As shown in fig. 4, the operational amplifier AMP includes a PMOS transistor MP2 and a PMOS transistor MP3, a source terminal of the PMOS transistor MP2 and a source terminal of the PMOS transistor MP3 are connected to the voltage VDD, a gate terminal of the PMOS transistor MP2 is connected to a source terminal of the PMOS transistor MP2, a drain terminal of the NMOS transistor MN1 and a gate terminal of the PMOS transistor MP3, a gate terminal of the NMOS transistor MN1 receives the feedback voltage Vfb, a drain terminal of the PMOS transistor MP3 is connected to a drain terminal of the NMOS transistor MN2, and a gate terminal of the NMOS transistor MN2 receives the reference voltage Vref;
the source terminal of the NMOS transistor MN1, the source terminal of the NMOS transistor MN2, and the drain terminal of the NMOS transistor MN3 are connected, the gate terminal of the NMOS transistor MN3 receives the voltage Vb output by the reference power supply, the source terminal of the NMOS transistor MN3, the output terminal of the transient response enhancement module, and the drain terminal of the NMOS transistor MN4 are connected, the gate terminal of the NMOS transistor MN4, the gate terminal of the NMOS transistor MN5, and the drain terminal of the NMOS transistor MN5 are connected, the source terminal of the NMOS transistor MN5, and the source terminal of the NMOS transistor MN4 are grounded, the drain terminal of the NMOS transistor MN5 further receives the reference current Ibias generated by the reference power supply, and the drain terminal of the PMOS transistor MP3, and the drain terminal of the NMOS transistor MN2 are connected to form the output terminal vo.
The embodiment of the utility model provides an in, NMOS pipe MN3 work is in the saturation region, voltage Vb and reference current Ibias produce by reference power supply, NMOS pipe MN4 constitutes the mirror current source with NMOS pipe MN5, NMOS pipe MN 3's source end, NMOS pipe MN 4's drain end all is connected with transient response reinforcing module's output, can produce a pull-down current Ipdown through transient response reinforcing module, can realize the drive current Isr that the increase loaded power tube MP1 grid terminal through pull-down current Ipdown.
As shown in fig. 5, the transient response enhancement module includes a hysteresis comparator COMP1 and a hysteresis comparator COMP2, wherein an inverting terminal of the hysteresis comparator COMP1 receives the reference voltage Vref, and a non-inverting terminal of the hysteresis comparator COMP1 receives the feedback voltage Vfb; an inverting terminal of the hysteresis comparator CMOP2 receives a feedback voltage Vfb, a non-inverting terminal of the hysteresis comparator COMP2 receives a reference voltage Vref, a positive power terminal of the hysteresis comparator COMP1 and a positive power terminal of the hysteresis comparator COMP2 are both connected with a voltage VDD, and a negative power terminal of the hysteresis comparator COMP1 and a negative power terminal of the hysteresis comparator COMP2 are both grounded;
the output end of a hysteresis comparator COMP1 is connected with the gate end of an NMOS tube MN6, the output end of a hysteresis comparator COMP2 is connected with the gate end of the NMOS tube MN7, the source end of the NMOS tube MN6 and the source base of the NMOS tube MN7 are grounded, the drain end of the NMOS tube MN6 is connected with one end of a resistor R5, the drain end of the NMOS tube MN7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the other end of a resistor R5, and the other end of the resistor R4 is also connected with the source end of the NMOS tube MN3 and the drain end of the NMOS tube MN 4.
The embodiment of the utility model provides an in, hysteresis comparator COMP1, hysteresis comparator COMP2 all can adopt present commonly used circuit form, and hysteresis comparator COMP1, the corresponding hysteresis size of hysteresis comparator COMP2 are delta V, and the size of hysteresis voltage can be selected according to actual need, specifically is this technical field personnel known, and this is no longer repeated here. Under the normal state: output end VOUTA of hysteresis comparator COMP1 and VOUTB of hysteresis comparator COMP2 both output low level, and at this time, NMOS transistor MN6 and NMOS transistor MN7 both are in off state. The resistor R4 and the resistor R5 have the same resistance. When the load current remains steady, Vfb is generally equal to Vref.
When the load current of the low dropout linear regulator body jumps from light load to heavy load in a short time, the output voltage of the low dropout linear regulator body decreases and Vfb is smaller than Vref- Δ V, the voltage output by the output terminal VOUTA of the hysteresis comparator COMP1 changes (the output voltage of the output terminal VOUTB of the hysteresis comparator COMP2 keeps unchanged), the level output by the output terminal VOUTA of the hysteresis comparator COMP1 changes from low to high, the NMOS tube NM6 is conducted, and a pull-down current Ipdown is generated; at this time, for the operational amplifier AMP, the driving current Isr applied to the gate terminal of the power transistor MP1 is increased by Ipdown/2, thereby reducing the drop of the output voltage of the ldo regulator body.
When the load current of the low dropout linear regulator body jumps from a heavy load to a light load in a short time, the output voltage of the low dropout linear regulator body rises and Vfb is greater than Vref + Δ V, the output voltage of the output terminal VOUTB of the hysteretic comparator COMP2 changes (the output voltage of the output terminal VOUTA of the hysteretic comparator COMP1 remains unchanged), that is, the level of the output terminal VOUTB of the hysteretic comparator COMP2 changes from low to high, the NMOS tube MN7 can be driven to be turned on by the high level output by the output terminal VOUTB of the hysteretic comparator COMP2, so that a pull-down current Ipdown can be generated, and at this time, for the operational amplifier AMP, the driving current Isr loaded to the gate terminal of the power tube MP1 increases by Ipdown/2, so that the rise of the output voltage of the low dropout linear regulator body is reduced.
Claims (4)
1. A quick response type low dropout linear regulator comprises a low dropout linear regulator body; the low dropout linear regulator body comprises an operational amplifier AMP, and the output end of the operational amplifier AMP is connected with the grid end of a power tube MP 1; the method is characterized in that:
the transient response enhancement module is in adaptive connection with the operational amplifier AMP, and when the load current of the low dropout linear regulator body jumps from light load to heavy load or from heavy load to light load, the transient response enhancement module and the operational amplifier AMP are matched to increase the driving current Isr loaded to the gate terminal of the power tube MP1 by the operational amplifier AMP so as to reduce sudden change of the output voltage of the low dropout linear regulator body caused by sudden load change.
2. The fast response low dropout regulator of claim 1, wherein: the low dropout linear regulator body further comprises a reference power supply, a reference voltage Vref at the output end of the reference power supply is connected with the inverting end of the operational amplifier AMP, the source end of the power tube MP1 and the positive power end of the operational amplifier AMP are connected with a voltage VDD, the drain end of the power tube MP1 is connected with one end of a resistor R1, one end of a resistor R3 and one end of a load capacitor CAP, the other end of the load capacitor CAP is grounded, the other end of a resistor R3 is connected with one end of a capacitor C1, the other end of a capacitor C1 is connected with the inverting end of the operational amplifier AMP, the other end of a resistor R1 and one end of a resistor R2, and the other end of the resistor R36;
the transient response enhancement module simultaneously receives a reference voltage Vref loaded to the inverting terminal of the operational amplifier AMP and a feedback voltage Vfb loaded to the non-inverting terminal of the operational amplifier AMP, and the output terminal of the transient response enhancement module is connected with the operational amplifier AMP.
3. The fast response low dropout regulator of claim 2, wherein: the operational amplifier AMP comprises a PMOS tube MP2 and a PMOS tube MP3, a source terminal of the PMOS tube MP2 and a source terminal of the PMOS tube MP3 are connected with a voltage VDD, a gate terminal of the PMOS tube MP2 is connected with a source terminal of the PMOS tube MP2, a drain terminal of the NMOS tube MN1 and a gate terminal of the PMOS tube MP3, a gate terminal of the NMOS tube MN1 receives a feedback voltage Vfb, a drain terminal of the PMOS tube MP3 is connected with a drain terminal of the NMOS tube MN2, and a gate terminal of the NMOS tube MN2 receives a reference voltage Vref;
the source terminal of the NMOS transistor MN1, the source terminal of the NMOS transistor MN2, and the drain terminal of the NMOS transistor MN3 are connected, the gate terminal of the NMOS transistor MN3 receives the voltage Vb output by the reference power supply, the source terminal of the NMOS transistor MN3, the output terminal of the transient response enhancement module, and the drain terminal of the NMOS transistor MN4 are connected, the gate terminal of the NMOS transistor MN4, the gate terminal of the NMOS transistor MN5, and the drain terminal of the NMOS transistor MN5 are connected, the source terminal of the NMOS transistor MN5, and the source terminal of the NMOS transistor MN4 are grounded, the drain terminal of the NMOS transistor MN5 further receives the reference current Ibias generated by the reference power supply, and the drain terminal of the PMOS transistor MP3, and the drain terminal of the NMOS transistor MN2 are connected to form the output terminal vo.
4. The fast response low dropout regulator of claim 3, wherein: the transient response enhancement module comprises a hysteresis comparator COMP1 and a hysteresis comparator COMP2, wherein the inverting terminal of the hysteresis comparator COMP1 receives a reference voltage Vref, and the non-inverting terminal of the hysteresis comparator COMP1 receives a feedback voltage Vfb; an inverting terminal of the hysteresis comparator CMOP2 receives a feedback voltage Vfb, a non-inverting terminal of the hysteresis comparator COMP2 receives a reference voltage Vref, a positive power terminal of the hysteresis comparator COMP1 and a positive power terminal of the hysteresis comparator COMP2 are both connected with a voltage VDD, and a negative power terminal of the hysteresis comparator COMP1 and a negative power terminal of the hysteresis comparator COMP2 are both grounded;
the output end of a hysteresis comparator COMP1 is connected with the gate end of an NMOS tube MN6, the output end of a hysteresis comparator COMP2 is connected with the gate end of the NMOS tube MN7, the source end of the NMOS tube MN6 and the source base of the NMOS tube MN7 are grounded, the drain end of the NMOS tube MN6 is connected with one end of a resistor R5, the drain end of the NMOS tube MN7 is connected with one end of a resistor R4, the other end of the resistor R4 is connected with the other end of a resistor R5, and the other end of the resistor R4 is also connected with the source end of the NMOS tube MN3 and the drain end of the NMOS tube MN 4.
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| CN110231847A (en) * | 2019-07-17 | 2019-09-13 | 江苏润石科技有限公司 | Rapid response type low pressure difference linear voltage regulator |
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