CN209895383U - High-speed transmission device for digital image big data - Google Patents
High-speed transmission device for digital image big data Download PDFInfo
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- CN209895383U CN209895383U CN201921019370.4U CN201921019370U CN209895383U CN 209895383 U CN209895383 U CN 209895383U CN 201921019370 U CN201921019370 U CN 201921019370U CN 209895383 U CN209895383 U CN 209895383U
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Abstract
A high-speed transmission device for large digital image data is a computer data acquisition and transmission method, which carries out high-speed data display and data storage on image data acquired from external imaging equipment of a computer such as a digital camera, a digital scanner and the like, breaks through the bottleneck limitation of data transmission speed of a bus interface of a computer mainboard in the traditional data transmission, display and storage processes, can realize high-speed transmission, real-time display and background storage of large data, particularly large image data, and can realize real-time display and high-speed storage of large image data such as digital pathological full-slice images, 360-degree panoramic images and the like. The utility model discloses an example is based on real-time demonstration and the high-speed storage of FPGA's many image acquisition system, can carry out simultaneous data acquisition with 20 digital image sensors and upload the computer and show in real time and high-speed storage in the several seconds with 32 Gb's image big data.
Description
Technical Field
The utility model relates to a data transmission hardware circuit and data read-write control field specifically say so a high-speed transmission device of digital image big data.
Background
In the field of data transmission and read-write control of computers, high-speed data transmission technology has been the target pursued by various companies and research and development personnel worldwide. With the advance of technology, high-speed transmission protocols and interfaces are in a variety of layers, for example, a USB interface, a protocol 1.0 is born in 1 month of 1996, a transmission speed reaches 12Mbit/s, a USB2.0 protocol introduced in 2000, a transmission speed reaches 480Mbit/s, a USB3.2 protocol introduced in 9 months of 2017, and the highest transmission speed reaches 20 Gbit/s. Although the data transmission speed of the peripheral interfaces of computers such as USB is higher and higher, the actual transmission speed is still limited by the transmission speed of the internal bus of the computer, because the data transmitted from the peripheral interfaces such as USB needs to be transmitted to the bus of the computer motherboard, then to be stored in the non-volatile memory through the bus controller, the ram and the cpu, and finally to be stored in the memory bus. In this process, the actual speed of data transfer is limited by the memory bus (6 Gbit/s). Therefore, for some large data, especially for digital image large data represented by digital pathology full-slice images, the data transmission speed is limited by the memory speed, and high-speed data transmission, display and storage cannot be realized, so that the real-time performance of image processing is greatly reduced.
Disclosure of Invention
In order to solve the high-speed transmission problem of the digital image big data that uses digital pathology full-section image as the representative, effectively promote digital pathology diagnostic efficiency and digital pathology scanner's performance, the utility model provides a high-speed transmission device of new-type digital image big data realizes 252 Gbit/s's highest speed data transmission, mainly is applied to a plurality of imaging device's image simultaneous display and the digital pathology section scanning field of hypervelocity.
The utility model discloses a high-speed data transmission principle is like this:
on one hand, the utility model provides a high-speed transmission device of digital image big data, including image acquisition device, image data acquisition controller, data bus interface, random access memory, central processing unit, nonvolatile memory and display output port; the image acquisition device is connected with the image data acquisition controller through a parallel data interface, and the image data acquisition controller is used for reading digital image data transmitted by the image acquisition device; the image data acquisition controller is connected with the random access memory through a data bus interface, and transmits digital image data to the random access memory through the data bus interface; the central processing unit is connected with the random access memory, the nonvolatile memory and the display output port through a circuit bus, and is used for reading the digital image data in the random access memory, storing the digital image data into the nonvolatile memory and outputting the digital image data to the display output port for displaying the image data.
The utility model relates to a large-scale image data acquisition, transmission, demonstration, storage method towards the computer specifically is to upload digital image big data that digital image collection equipment such as many digital cameras or digital scanner transmitted to digital image processing system and show in real time and high-speed storage's method at a high speed to solve traditional data transmission method and can't realize the high-speed transmission of short time, show slow problem to digital image big data.
A high-speed transmission method of large-scale digital image data is a novel high-speed data transmission technology aiming at the high-speed transmission, display and storage of the large digital image data. Firstly, an image data acquisition controller reads data of an image data acquisition device, and sends digital image big data to a data transmission bus after preprocessing such as color adjustment, data format conversion, data compression and the like is carried out on the image data through a data processing unit integrated in the image data acquisition controller; then the control program running on the central processor switches the control right of the central processor and the bus controller to the data transmission bus, the big data read from the data transmission bus is written into the random access memory in a direct memory access mode, finally the control program returns the control right of the data transmission bus to the central processor from the bus controller, the data in the random access memory is directly written into the data display port in the data transmission bus and direct memory access mode, the background automatically writes the big image data into the nonvolatile memory in the direct memory access mode while the image data is displayed, and the high-speed image display and nonvolatile storage of the big digital image data are realized.
The utility model discloses in, when data spread into RAM into, do not pass through central processing unit, but in the RAM through data bus direct write in, consequently data transmission speed on the data bus has decided with RAM's data transmission speed's minimum the utility model discloses data transmission speed's maximum value, when data bus adopted PCI Express 3.016 channel interface, highest transmission speed was 252Gbit/s, when RAM adopted DDR4 SDRAM PC4-34100, highest transmission speed was 272.8 Gbit/s, consequently, under this kind of condition, the utility model discloses a highest transmission speed is 252Gbit/s, to the transmission of the digital pathology full section image of data volume about 32 Gbit, the shortest transmission time is about 0.13 seconds, accords with real-time data transmission's needs.
The utility model discloses in, when data spread into the display output port, central processing unit directly reads the data in the random access memory, send it into display output port, consequently random access memory's data transmission speed and display output port data transmission speed's minimum has decided the utility model discloses display output speed's maximum value, when random access memory adopted DDR4 SDRAMPC4-34100, the highest transmission speed was 272.8 Gbit/s, when display output port adopted HDMI2.1 interface protocol, the highest transmission speed was 48Gbit/s, consequently, under this kind of condition, the utility model discloses a highest display output speed is 48Gbit/s, to the transmission of the digital pathology full section image of data volume about 32 Gbit, the shortest transmission time is about 0.7 seconds, accords with the needs of high-speed data display.
In the utility model, the CPU directly reads the data in the RAM and sends the data into the display output port, and sends the data into the nonvolatile memory through the data bus, therefore, the data transmission speed of the RAM and the data transmission speed of the nonvolatile memory are the minimum value, the maximum value of the data storage speed of the utility model is determined, when the RAM adopts DDR4 SDRAM PC4-34100, the highest transmission speed is 272.8 Gbit/S, when the data transmission interface of the nonvolatile memory adopts S-ATA 3.0 protocol, the highest transmission speed is 6Gbit/S, therefore, under this condition, the highest data storage speed of the utility model is 6Gbit/S, for the storage of the digital pathology full slice image with data volume of about 32 Gbit, the shortest storage time is about 5.3 seconds, because the digital image output shows the back, the user generally needs to observe, especially in digital pathological diagnosis process, and the time of observing and diagnosing to digital pathological image needs 20 seconds (the shortest time of general pathological diagnosis) at least, consequently the utility model discloses a data storage time accords with the needs of high-speed data storage.
Further, the image capturing device is a sensor having a photoelectric conversion function and generating a digital signal, or a device having a digital image output capability.
Further, the image data acquisition controller and the central processing unit are processor chips or electronic systems with serial computation and logic processing, or processor chips or electronic systems with parallel computation and logic processing.
Further, the image data acquisition controller and the central processing unit are field programmable gate arrays or central processing units.
Further, the data bus interface is a data bus and hardware interface from the image data acquisition controller to the random access memory.
Furthermore, the data bus interface is a PCI-express bus and interface, or a USB bus and interface, or a parallel transmission bus and interface.
Further, the random access memory is a register with data buffer access.
Further, the random access memory is a pre-memory buffer, or a double data rate random access memory, or a double data rate synchronous dynamic random access memory.
Further, the non-volatile memory is a computer memory in which stored data does not disappear after the power is turned off.
Further, the nonvolatile memory is a read-only memory, or a magnetic disk memory, or a solid hard disk memory.
Further, the image data acquisition controller is used for receiving the method or the communication protocol of the image acquisition device in parallel or in series so as to acquire and process the image data.
Further, the image data acquisition controller also adopts a serial or parallel data calculation method to pre-process the image data.
Further, the serial or parallel data calculation method is a conversion calculation method of an image data format, and/or a calculation method of image data compression, and/or a calculation method of image color adjustment.
Further, the random access memory is used for writing the read bus interface data in a direct memory access manner.
Further, the central processing unit is used for reading the data stored in the random access memory, and writing the data read from the random access memory into the display output port in a direct memory access manner.
Further, the nonvolatile memory is used for reading the data stored in the random access memory, and the read data of the random access memory is written in a direct memory access mode.
On the other hand, the utility model also provides a high-speed transmission method of digital image big data, it includes following step:
step S1: the image acquisition device acquires digital image data;
step S2: the image data acquisition controller reads the digital image data transmitted by the image acquisition device and transmits the digital image data to the random access memory through the data bus interface;
step S3: the central processing unit reads the digital image data in the random access memory, stores the digital image data into the nonvolatile memory and simultaneously outputs the digital image data to the display output port for displaying the image data.
To digital image big data, especially digital pathology full-section image, the utility model relates to a high-speed transmission device of digital image big data and transmission method compare for prior art, have following difference and superiority:
in the prior art, a central processing unit firstly receives image data transmitted by an interface of external equipment such as a USB and the like, secondly writes the data into a random access memory, secondly reads the data in the random access memory and sends the data into a display output port, after the display is finished, the data stays in a display cache, and then the central processing unit transmits the data in the random access memory to a nonvolatile memory through a bus. The process is controlled by the central processing unit, which generally causes slow data transmission, generally takes more than 10 seconds, even minutes, for example, when an interrupt processing task occurs, the central processing unit needs to suspend the current data transmission task, after the interrupt processing task is finished, the central processing unit needs to reply the data transmission task, and excessive interrupt processing tasks may cause the data transmission speed to be reduced.
The utility model discloses a method, data transmission process do not have central processing unit's intervention, and control program control central processing unit switches the data bus control right to bus controller to realize that data is direct from the bus to random access memory's transmission, under this condition, data transmission belongs to end-to-end transmission, does not have the interrupt, and bus transmission speed is big, can realize fast-speed data transmission more.
Additionally, the utility model discloses a method for the data transmission of demonstration belongs to concurrent data transmission with towards nonvolatile memory's data transmission, and the two goes on simultaneously, and belongs to direct memory reading and data transmission, therefore the upper limit of data speed is restricted at display port and nonvolatile memory speed, full play data bus transmission advantage, makes data transmission speed reach the limit.
The above description is only an overview of the technical solution of the present invention, and in order to make the technical means of the present invention clearer and can be implemented according to the content of the description, the following detailed description is made with reference to the preferred embodiments of the present invention and accompanying drawings.
Drawings
FIG. 1 is a hardware implementation structure and data processing flow chart of the high-speed transmission device for digital image big data of the present invention;
fig. 2 is a hardware implementation structure diagram of the high-speed transmission device for digital image big data with a plurality of digital image sensors for parallel image acquisition, image data transmission, display and storage;
fig. 3 is a flowchart of the high-speed transmission method of the digital image big data of the present invention.
Reference numerals: 1. an image acquisition device; 2. an image data acquisition controller; 3. a data bus interface; 4. a random access memory; 5. a central processing unit; 6. a non-volatile memory; 7. an output port is displayed.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that, if directional indications (such as upper, lower, left, right, front and rear … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.
The following will describe the high-speed transmission device and the transmission method for digital image big data of the present invention in further detail, but should not limit the scope of the present invention.
An object of the utility model is to provide a high-speed transmission device of digital image big data and transmission method thereof provides an implementation scheme for the data transmission of large-scale image data, especially digital pathology full-section image.
As shown in fig. 1 and fig. 2, the high-speed transmission device for digital image big data of the present invention comprises an image acquisition device 1, an image data acquisition controller 2, a data bus interface 3, a random access memory 4, a central processing unit 5, a non-volatile memory 6 and a display output port 7; the image acquisition device 1 is connected with the image data acquisition controller 2 through a parallel data interface, and the image data acquisition controller 2 is used for reading digital image data transmitted by the image acquisition device 1; the image data acquisition controller 2 is connected with the random access memory 4 through a data bus interface, and the image data acquisition controller 2 transmits digital image data to the random access memory 4 through the data bus interface 3; the central processing unit 5 is connected with the random access memory 4, the nonvolatile memory 6 and the display output port 7 through a circuit bus, and the central processing unit 5 is used for reading the digital image data in the random access memory 4, storing the digital image data in the nonvolatile memory 6 and outputting the digital image data to the display output port 7 for displaying the image data.
The aforementioned image capturing apparatus 1 may be a sensor having photoelectric conversion and generating a digital signal, or a device having digital image output capability. Both the image data acquisition controller 2 and the central processor 5 may be processor chips or electronic systems with serial computation and logic processing, or processor chips or electronic systems with parallel computation and logic processing. Preferably, the image data acquisition controller 2 and the central processing unit 5 may be field programmable gate arrays, or central processing units. The aforementioned image data acquisition controller 2 is used for receiving the method or communication protocol of the image acquisition device in parallel or in series to perform the image data acquisition processing. The image data acquisition controller 2 also pre-processes the image data using serial or parallel data computation. The serial or parallel data calculation method may be a conversion calculation method of an image data format, and/or a calculation method of image data compression, and/or a calculation method of image color adjustment. The central processing unit 5 is used for reading the data stored in the random access memory 4 and writing the data read from the random access memory 4 into the display output port 7 in a direct memory access manner.
The data bus interface 3 may be a data bus and hardware interface from the image data acquisition controller 2 to the random access memory 4. Preferably, the data bus interface 3 is a PCI-express bus and interface, a USB bus and interface, or a parallel transmission bus and interface. The aforementioned random access memory 4 may be a register having data buffer access. Preferably, the RAM 4 is a pre-memory buffer, or a double data rate RAM or a double data rate SDRAM. The random access memory 4 is used to write the read bus interface data in a direct memory access manner.
The aforementioned nonvolatile memory 6 may be a computer memory in which stored data does not disappear after the power is turned off. Preferably, the non-volatile memory 6 is a read-only memory, or a magnetic disk memory, or a solid hard disk memory. The nonvolatile memory 6 is used for reading data stored in the random access memory 4 and writing the read random access memory data in a direct memory access manner.
As shown in fig. 3, an embodiment of the present invention further provides a high-speed transmission method for digital image big data, which includes the following steps:
step S1: the image acquisition device 1 acquires digital image data;
step S2: the image data acquisition controller 2 reads the digital image data transmitted by the image acquisition device 1 and transmits the digital image data to the random access memory 4 through the data bus interface 3;
step S3: the central processing unit 5 reads the digital image data in the random access memory 4, stores the digital image data in the nonvolatile memory 6, and simultaneously outputs the digital image data to the display output port 7 for image data display.
The digital image large data high-speed transmission device comprises 20 digital image sensors (CMOS), an image data acquisition controller (2) is a Field Programmable Gate Array (FPGA), the CMOS and the FPGA are connected by using an MIPI-CSI2 bus, the data transmission adopts an MIPI-CSI2 communication protocol, one CMOS is used for transmitting data with the size of 0.3 Gbit and the data transmission speed of 4.5Gbit/s, the total data is 240 Gbit, the data after the FPGA performs data compression processing is 32 Gbit, a Central Processing Unit (CPU) is used as a Central Processing Unit (CPU), the FPGA and the CPU are connected by a PCI Express 16 channel bus, the data transmission adopts an Express PCI 3.0 communication protocol, the data size required to be transmitted by the bus is 32 Gbit, the data transmission speed is 48Gbit/s, a random access memory 4 is DDR4 SDRAM, and the data transmission speed is 188 Gbit/s, the required transmission data size is 32 Gbit, the nonvolatile memory 6 is a solid state disk, the data transmission interface adopts an SATA M.2 specification interface and a PCI Express 3.0 communication protocol, the data transmission speed is 4 Gbit/s, the required transmission data size is 32 Gbit, the display output interface 7 adopts an HDMI2.1 interface and a display communication protocol, and the highest transmission speed is 48 Gbit/s.
The embodiment of the high-speed transmission device for the digital image big data comprises the following specific data transmission processes: firstly, the FPGA reads digital image data of 20 CMOS through an MIPI-CSI2 data interface and a communication protocol at the same time to obtain the original data of 20 digital images; secondly, the FPGA carries out format coding and data compression preprocessing on the original image data to enable the original image data to become image data readable by a computer operating system; then, the FPGA sends the preprocessed image data to a PCI Express bus, meanwhile, a driving program of an operating system controls a CPU, the control right of the PCI Express bus is switched to a PCI Express controller on a computer mainboard, the controller is operated to directly transmit the data in the corresponding PCI Express interface to DDR4 SDRAM, digital images acquired by different CMOS are stored in corresponding DDR4 SDRAM address areas, and digital pathology full-slice image caching is achieved on hardware.
The embodiment of the high-speed transmission device for the digital image big data comprises the following specific data display and storage processes: the computer operating system driver controls the PCI Express bus controller to switch the control right to the CPU, and operates the CPU to read out the cache data in the DDR4 SDRAM, then the CPU divides into two task threads, one thread outputs the data to the display port through the bus to complete the display task, and meanwhile, the other thread transmits the data to the corresponding storage address of the SSD through the bus to complete the nonvolatile data storage task.
The embodiment of the high-speed transmission device for the digital image big data has the following specific data transmission time: the time from the parallel reading of the data from the 20 CMOS chips to the FPGA through the MIPI-CSI2 interface is 0.07 second, the FPGA needs to perform image format conversion and data compression on the data after reading the data, but parallel calculation is performed inside the FPGA, and the preprocessing processes can be completed only in a few FPGA clock cycles, so that the preprocessing time is short and can be ignored. After the image format conversion and data compression are performed by the FPGA, the time for transmitting the data to the DDR4 SDRAM through the PCI Express bus is 0.7 second, so the total time from the start of data acquisition to the completion of the transmission is 0.77 second.
The embodiment of the high-speed transmission device for the large digital image data has the following specific time for performing nonvolatile data storage: 8 seconds; the specific time for simultaneous display data transmission is 0.67 seconds.
Here, it should be noted that: in the case of no conflict, a person skilled in the art may combine the related technical features in the above examples according to actual situations to achieve corresponding technical effects, and details of various combining situations are not described herein.
It is above only the utility model discloses a preferred embodiment, the utility model discloses a scope of protection does not only confine above-mentioned embodiment, the all belongs to the utility model discloses a technical scheme under the thinking all belongs to the utility model discloses a scope of protection. It should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A high-speed transmission device for digital image big data is characterized by comprising an image acquisition device, an image data acquisition controller, a data bus interface, a random access memory, a central processing unit, a nonvolatile memory and a display output port;
the image acquisition device is connected with the image data acquisition controller through a parallel data interface, and the image data acquisition controller is used for reading digital image data transmitted by the image acquisition device; the image data acquisition controller is connected with the random access memory through a data bus interface, and transmits digital image data to the random access memory through the data bus interface; the central processing unit is connected with the random access memory, the nonvolatile memory and the display output port through a circuit bus, and is used for reading the digital image data in the random access memory, storing the digital image data into the nonvolatile memory and outputting the digital image data to the display output port for displaying the image data.
2. The apparatus for high-speed transmission of digital image big data according to claim 1, wherein the image capturing device is a sensor having photoelectric conversion and generating digital signals, or a device having digital image output capability.
3. The device for high-speed transmission of digital image big data according to claim 1, wherein the image data acquisition controller and the central processing unit are processor chips or electronic systems with serial computation and logic processing, or processor chips or electronic systems with parallel computation and logic processing, or processor chips or electronic systems with both serial and parallel computation and logic processing.
4. The apparatus for high-speed transmission of big digital image data according to claim 1, wherein the data bus interface is a hardware interface and a data bus from the image data acquisition controller to the RAM.
5. The apparatus for high-speed transmission of big data of digital images according to claim 1, wherein the random access memory is a register with data buffer access; and/or the nonvolatile memory is a computer memory which can not disappear after the power supply is turned off.
6. The device for high-speed transmission of big digital image data according to claim 1, wherein the image data acquisition controller is used for parallel or serial reception of the method or communication protocol of the image acquisition device to acquire and process the image data, and adopts a serial or parallel data processing algorithm to pre-process the image data.
7. The apparatus for high-speed transmission of digital image big data according to claim 1, wherein the RAM is used for writing the read bus interface data in a direct memory access manner.
8. The apparatus for high-speed transmission of big digital image data according to claim 1, wherein the central processing unit is configured to read the data stored in the random access memory, and write the data read from the random access memory to the display output port in a direct memory access manner.
9. The device for high-speed transmission of large digital image data according to claim 1, wherein the non-volatile memory is used for reading the data stored in the random access memory, and the read random access memory data is written in a direct memory access manner.
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