CN209879490U - Integral type storage device - Google Patents

Integral type storage device Download PDF

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Publication number
CN209879490U
CN209879490U CN201920738438.8U CN201920738438U CN209879490U CN 209879490 U CN209879490 U CN 209879490U CN 201920738438 U CN201920738438 U CN 201920738438U CN 209879490 U CN209879490 U CN 209879490U
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Prior art keywords
storage device
chip
control chip
substrate
input
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CN201920738438.8U
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Chinese (zh)
Inventor
陈向兵
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Shenzhen Sandi Yixin Electronics Co ltd
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Shenzhen Three Place One Core Electronic LLC
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Abstract

The utility model discloses an integrated storage device, which comprises a substrate, wherein a circuit layer is arranged on the substrate, an insulating layer is arranged on the circuit layer, a main control chip and at least one storage chip are arranged on the insulating layer, the main control chip is electrically connected with the storage chip through the circuit layer, one side of the circuit layer is provided with a golden finger for being connected with external equipment, and the insulating layer is provided with a through hole for exposing a welding pad and the golden finger; the master control chip controls the internal gating module to select the output/input path of the corresponding IO port according to the input/output signal of the memory chip, so that the output/input signal of the master control chip adapts to the input/output signal of the memory chip, namely, the master control chip controls the output and input of the pin of the master control chip to adapt to the input and output definition of the memory chip, thereby realizing that one master control chip uses the same PCB wiring to be compatible with the memory chips with different models, improving the compatibility of the PCB, and the wiring mode of the circuit layer is simple, thereby greatly reducing the cost.

Description

Integral type storage device
Technical Field
The utility model relates to a storage technology field, in particular to integral type storage device.
Background
Among existing storage devices, UDP (USB Disk In Package, which is a latest process technology and called PIP Package, PIP is a short for english Product In Package), SD Card, EMMC (Embedded MultiMedia Card, which is a storage device that uses a unified MMC standard interface and packages high-density NAND Flash and MMC Controller In one BGA chip), EMCP (EMCP is a smart phone memory standard that combines EMMC and MCP Package), and other products mainly include a Controller chip, one (or more) storage chips (i.e., NAND Flash), and other conventional passive devices such as other resistive capacitors. UDP and SD cards generally use a double-sided PCB as a substrate, resistors, capacitors and other conventional passive components are mounted on the substrate by SMT, and a control chip and a memory chip are fixed and connected to the substrate by Die Bond (i.e., a wafer is bonded by an epoxy resin and a gold layer on the back of the wafer is mechanically pressed and welded at an instantaneous high temperature to a gold-plated surface at the center of a fixed frame) and WireBond.
Currently, products such as UDP, SD card, EMMC, etc. usually have two, four, or even more metal layers, and taking two metal layers as an example, as shown in fig. 1 and fig. 2, a PCB includes a substrate 10, an upper metal layer 20 and a lower metal layer 30 attached to both sides of the substrate, and two solder resists 40, 50 attached to the outer sides of the upper metal layer 20 and the lower metal layer 30, respectively. The substrate is a PCB insulating substrate (mainly used for attaching a metal circuit thereon and having certain hardness), the solder mask layers 40 and 50 mainly cover unnecessary parts for insulation and protection, and the metal layer is mainly used for electrifying and transmitting electric signals of electronic devices. As shown in fig. 2, when the circuit traces on the upper metal layer 20 intersect, holes are punched on the substrate 10 to the lower metal layer 30, and the two metal layers are conducted by the copper plated holes through the hole walls 31, which means that the more the types and the number of electronic devices are, the more complicated the circuit traces are, and the more metal layers are.
If the existing storage device (such as a U disk) needs to be compatible with different flashes, the main control chip and the Flash routing positions need to be reserved at a plurality of positions of a PCB, for example: a Data5 signal of a master control chip can be compatible with Data5 signals of five memory chips, when Data5 signal pins of various memory chips are at different positions, 5 routing positions of Data5 signals need to be reserved on a PCB, and the shapes of UDP, SD card, EMMC and EMCP products cannot be changed, so that the PCB wiring is very thin, and the wiring on the whole PCB is very complex. Even so, the PCB board still has the storage chip of good many models to be incompatible, so the producer still needs to be equipped with various different PCB boards to the PCB board stock is not good, walks line design or manufacturing process scheduling problem more complicacy to appear.
Meanwhile, after the routing position on the PCB is fixed, the signal definition of the chip is fixed at the same time, and if the PCB needs to be redesigned, the problems of high cost, long production period and the like are caused.
Thus, the prior art has yet to be improved and enhanced.
SUMMERY OF THE UTILITY MODEL
In view of the foregoing prior art, an object of the utility model is to provide an integral type storage device can improve the compatibility of PCB board, reduces PCB and walks the line degree of difficulty, reduces product cost.
In order to achieve the purpose, the utility model adopts the following technical proposal:
an integrated storage device comprises a substrate, wherein a circuit layer is arranged on the substrate, an insulating layer is arranged on the circuit layer, a main control chip and at least one storage chip are arranged on the insulating layer, the main control chip is electrically connected with the storage chip through the circuit layer, and a golden finger used for being connected with external equipment is arranged on one side of the circuit layer; the master control chip controls the internal gating module to select the output/input channel of the corresponding IO port according to the input/output signal of the storage chip, so that the output/input signal of the master control chip is adaptive to the input/output signal of the storage chip.
The packaging structure comprises a packaging body, a substrate, an insulating layer and an electronic device of the integrated storage device, wherein a slot for exposing a golden finger is formed in the packaging body, and the substrate, the insulating layer and the electronic device of the integrated storage device are arranged in the packaging body.
Wherein the thickness of the substrate is not more than 0.2 mm.
Wherein, the side of the base plate used for arranging the circuit layer is provided with an adhesive layer.
The circuit layer is made of a copper sheet.
The integrated storage device is at least one of UDP, SD card device, EMMC and EMCP.
The SD card device comprises an SD card, a Mini SD card or a Micro SD card.
The substrate is a transparent or semitransparent silica gel plate or a glass fiber plate.
Wherein, the substrate is a transparent or semitransparent film.
Compared with the prior art, the utility model provides an integral type storage device, control its corresponding IO mouth's output/input signal through main control chip according to storage chip's input/output signal, make main control chip's output/input signal adaptation storage chip's input/output signal, the output and the input that main control chip controlled its self pin come from adaptation storage chip are defined with the output promptly, thereby realize that a main control chip uses the same PCB to walk the storage chip of the compatible different models of line, the compatibility of PCB board has been improved, and the line mode is simple to be walked on the circuit layer, and only need the individual layer wiring, greatly reduced the cost.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a PCB board of a memory device of the related art.
Fig. 2 is a schematic partial structure diagram of a substrate and a circuit layer of a PCB board of a memory device in the prior art.
Fig. 3 is a schematic structural diagram of an embodiment of an integrated storage device according to the present invention before packaging.
Fig. 4 is a cross-sectional view of an embodiment of an integrated storage device provided by the present invention.
Fig. 5 is a schematic structural diagram of an integrated storage device according to an embodiment of the present invention after packaging.
Description of the drawings: in order to visually display the PCB panel structure of the integrated memory device, fig. 4 does not show the electronic devices such as the chip, the resistor, the capacitor, etc.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the following description of the present invention will refer to the accompanying drawings and illustrate embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
It will be understood that when an element is referred to as being "on," "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present.
It should be noted that the terms of orientation such as left, right, up and down in the embodiments of the present invention are only relative to each other or are referred to the normal use state of the product, and should not be considered as limiting.
Please refer to fig. 3 and fig. 4, wherein fig. 3 is a schematic structural diagram of an integrated storage device (e.g., a usb disk) according to an embodiment of the present invention before packaging. Fig. 4 is a cross-sectional view of an embodiment of an integrated storage device provided by the present invention.
As shown in fig. 3 and 4, the utility model discloses an integral type storage device includes base plate 1, be provided with one deck circuit layer 2 on the base plate, be provided with insulating layer 3 on the circuit layer 2, be provided with a main control chip 4 and an at least storage chip 5 on the insulating layer, main control chip 4 is connected with storage chip 5 through circuit layer 2, one side of circuit layer 2 has the golden finger 21 that is used for being connected with external equipment (if have the female equipment of USB), set up on the insulating layer 3 and supply pad 22 and/or the exposed through-hole (not numbered in the figure) of golden finger 21, main control chip 4 selects corresponding IO mouth output/input route according to the gating module (not shown in the figure) of storage chip 5's its inside input/output signal control, make main control chip 4's output/input chip adapt to storage chip 5's input/output signal.
In the embodiments shown in fig. 3 and 4, the area (e.g., the pad 22) filled with the wide-pitch oblique lines is an area where the circuit layer is exposed to be conductive, and after the electronic devices such as a chip, a resistor, a capacitor, or a diode are mounted on the pad 22 at a later stage, the electronic devices and the circuit layer are electrically conductive. In fig. 3, 23 is an end point of a metal circuit, 24 is another end point of the metal circuit, the end points 23 and 24 are different end points of the same metal circuit, and both end points are exposed for the main control chip 4 and the memory chip 5 to be attached and conductive respectively. The region filled with the narrow-pitch oblique lines in fig. 3 is the insulating layer 3, but in this embodiment, the structure of the circuit layer 2 is visually recognized, and the narrow-pitch oblique lines are not filled in the circuit layer 2.
The utility model discloses only use one deck circuit layer, control its corresponding IO mouth's output/input signal through main control chip according to memory chip's input/output signal to its inside gating module, make main control chip's output/input signal adaptation memory chip's input/output signal, the output and the input of main control chip control its self pin come from adaptation memory chip's input and output definition promptly, thereby realize that a main control chip adopts the memory chip of compatible different models under the condition that the same PCB walked the line, the compatibility of PCB board has been improved, and the circuit layer is walked the line mode simply, and only need the individual layer wiring, greatly reduced the cost.
Please refer to fig. 5, which is a schematic diagram illustrating a packaged integrated memory device according to an embodiment of the present invention. In order to further simplify the structure of style storage device, make the ultra-thin of electronic product, the utility model discloses an integral type storage device still includes packaging body 6, be provided with on packaging body 6 and supply the exerted fluting of golden finger (not reference numeral in the picture), base plate 1, insulating layer 3 and integral type storage device's electron device (such as resistance, electric capacity etc.) set up in packaging body 1, make whole integral type storage device be the slice, in addition after packaging body encapsulation, compare with traditional storage device, have characteristics waterproof, dampproofing, anti falling. In addition, the storage device does not need a shell, and the product cost is further reduced.
In this embodiment, the thickness of the substrate is not more than 0.2mm, so that the gold finger 21 can be smoothly inserted into an external device, and poor contact is avoided. Preferably, the substrate is an insulator with a thickness of less than 0.1mm, so that the memory device can be well interfaced with an interface of an external device.
In a further embodiment, one side of the substrate, which is used for arranging the circuit layer, is provided with an adhesive layer (not shown in the figure), so that the circuit layer can be well attached to the substrate, the circuit layer is not easy to shift when a PCB (printed circuit board) is manufactured, the anti-falling performance during the turnover of the production process is improved, and the reliability of a product is improved. Of course, the substrate may be directly pressed with the metal layer, as long as the metal layer can be attached to the substrate.
In a further embodiment, the circuit layer is made of a copper sheet, the copper sheet can be made of the copper sheet through laser, etching and other technologies, the width of the wiring of the circuit layer is 3-20 mil, the precision requirement on the manufacturing process of the circuit layer is greatly reduced, the circuit is not easy to break, and the rejection rate is reduced.
The ALE signal of U dish equipment is for example, the Flash ALE signal of traditional U dish must be connected to the ALE circuit that the master control corresponds through metal lines on the base plate, and the utility model discloses make the back at the circuit layer, the pad accessible routing of memory chip and main control chip is to the PCB base plate, on the one end 23 of corresponding metal lines on the base plate was earlier routed to ALE signal pad like Flash (memory chip), connect the F13 foot pad of main control chip through this metal lines, the wafer of main control chip passes through routing to the F13 foot pad of main control chip on, select the F13 foot through the inside gating module of main control chip and switch on the ALE signal and make its output ALE signal, after other signal feet of Flash all handled according to this mode, the main control chip just can normally communicate with Flash, therefore, can become current complicated UDP base plate into simple single face base plate.
In a further embodiment, the substrate is a transparent or semitransparent silica gel plate or a glass fiber plate, and holes can be conveniently formed in the substrate in a transparent or semitransparent manner, such as through holes for exposing golden fingers on the back of the substrate. Of course, the utility model discloses also can directly trompil on the insulating layer, make the golden finger expose, the utility model discloses do not do the restriction to this. Further, a transparent or translucent film such as a polyimide film or a polyester film used for FPC (flexible circuit board) may be used as the substrate as long as it has an adhesive ability to open a hole.
In specific application, the integrated storage device is at least one of UDP, SD card device, EMMC and EMCP, wherein the SD card device comprises an SD card, a Mini SD card or a Micro SD card. The number of the memory chips on the memory device can be more than one, and when more than two memory chips are adopted, the memory chips need to adopt chips with the same type, so that data interaction with the same main control chip is realized.
Taking UDP as an example, the main control chip may be an integrated chip with a model FC1179, a gating module is integrated inside the main control chip, and before attaching, a path of the gating module is set to control the input and output signal types of the pin. Of course, the present invention can also adopt other chips with gating modules inside. The flash model of the memory chip can be H27TDG8T2D, H27QEG8M3M, H27QDG8T2C, H27QEG8M2B, H27QDG8M2C, H27QEG8M2A, H25QFT8A1A, FRN1(8T23) manufactured by Toshiba and Toshidi, FRN4(9T23), FRSO (9T24), FRV8(8T24) and InterB27-11L of Korea SKHynix. The common input and output signals of the memory chip include: CEN0, CEN1, CEN2, CEN3, REN, WEN, ALE, CLE, RB, Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, DQS and the like, wherein the signals connected with the main control chip comprise: F/RB, F/ALE, F/CLE, F/DL, F/WR, F/RD, F/DH, F/CE, F/DQS signal, etc. the utility model selects the conduction path inside the main control chip to control and output F/RB, F/ALE, F/CLE, F/DL, F/DH, F/WR, etc. by the gating module, F7/RD, F16/DH0, F17/DH1, F18/DH2, F19/DH3, F20/DH4, F21/DH5, F22/DH6, F23/DH7, F0/CE0, F1/CE1, F2/CE2, F3/CE3, F25/DQS signal pins to adapt to the input and output signals of the memory chip, so that the PCB wiring on the wiring layer can be wired in sequence and can not be crossed, the difficulty of the wiring layer is simplified, the design degree of the PCB board is simplified, and the production period is greatly shortened.
Preferably, the main control chip, the memory chip, the resistor, the capacitor and other electronic devices are arranged on the same side of the substrate, the complex multi-surface substrate is converted into a single-surface substrate, the manufacturing of the storage device PCB can be completed only by one-time mounting and one-time reflow soldering, the production process is few, the production period is short, and the performance of all the electronic devices is more stable only by one-time reflow soldering.
It should be noted that the utility model discloses an one deck circuit layer, a main control chip use the mode that other chips of the same PCB board compatible are come, adapt to other compatible storage chip through main control chip equally, realize that the circuit layer reduces, and PCB walks to use in the line simplified product, realizes reducing the production degree of difficulty of PCB board or improving production efficiency, realizes even that can more support different model Flash on same base plate.
To sum up, the utility model provides an integral type storage device, the input/output signal of its corresponding IO mouth is selected to its inside gating module according to storage chip's input/output signal through main control chip, make main control chip's input/output signal adaptation storage chip, the output and the input that main control chip controlled its self pin come from adaptation storage chip's input and output definition promptly, thereby realize the Flash of a main control chip compatible different models, avoid appearing leading to the fixed problem of signal definition because of main control routing position and Flash routing position on the PCB board promptly, need not to increase the number of piles of PCB board because of the Flash of multiple model, and reduced PCB board and walked line complexity.
The utility model provides the high compatibility of PCB board uses the PCB board of a wiring to come compatible different main control chip and memory chip, need not to come the goods PCB board to the chip of every different grade type during stock, and the stock management of being convenient for, the PCB board can be in advance stock moreover, has shortened production cycle greatly.
Furthermore, the utility model discloses change the multiply wood into single layer board, the thickness of storage device that has significantly reduced satisfies the ultra-thin requirement of electronic product, need not the shell moreover, and product cost further reduces.
It should be understood that equivalent alterations and modifications can be made by those skilled in the art according to the technical solution of the present invention and the inventive concept thereof, and all such alterations and modifications should fall within the scope of the appended claims.

Claims (9)

1. The integrated storage device is characterized by comprising a substrate, wherein a circuit layer is arranged on the substrate, an insulating layer is arranged on the circuit layer, a main control chip and at least one storage chip are arranged on the insulating layer, the main control chip is electrically connected with the storage chip through the circuit layer, and a golden finger used for being connected with external equipment is arranged on one side of the circuit layer; the master control chip controls the internal gating module to select the output/input channel of the corresponding IO port according to the input/output signal of the storage chip, so that the output/input signal of the master control chip is adaptive to the input/output signal of the storage chip.
2. The integrated storage device according to claim 1, further comprising a package body, wherein the package body is provided with a slot for exposing the golden finger, and the substrate, the insulating layer and the electronic device of the integrated storage device are arranged in the package body.
3. The unitary storage device of claim 1, wherein the substrate has a thickness of no more than 0.2 mm.
4. The unitary storage device of claim 1, wherein the substrate is provided with an adhesive layer on a side thereof on which the wiring layer is provided.
5. The unitary storage device of claim 4, wherein said wiring layer is fabricated from a piece of copper sheet.
6. The unified storage device according to claim 1, wherein the unified storage device is at least one of UDP, SD card device, EMMC, EMCP.
7. The unitary storage device of claim 6, wherein the SD card means comprises an SD card, a Mini SD card, or a Micro SD card.
8. The unitary storage device of claim 1, wherein the substrate is a transparent or translucent silicone sheet, or a fiberglass sheet.
9. The unitary storage device of claim 1, wherein said substrate is a transparent or translucent film.
CN201920738438.8U 2019-05-22 2019-05-22 Integral type storage device Active CN209879490U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201920738438.8U CN209879490U (en) 2019-05-22 2019-05-22 Integral type storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201920738438.8U CN209879490U (en) 2019-05-22 2019-05-22 Integral type storage device

Publications (1)

Publication Number Publication Date
CN209879490U true CN209879490U (en) 2019-12-31

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ID=68947464

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
CN (1) CN209879490U (en)

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Address after: 518000 402-406, floor 4, building 4, Tianan Yungu Industrial Park, Gangtou community, Bantian street, Longgang District, Shenzhen, Guangdong Province

Patentee after: SHENZHEN SANDIYIXIN ELECTRONIC Co.,Ltd.

Address before: 518116 room 508, building D, Bantian International Center, No. 5 Huancheng South Road, Bantian street, Shenzhen, Guangdong Province

Patentee before: SHENZHEN SANDIYIXIN ELECTRONIC Co.,Ltd.

CP02 Change in the address of a patent holder
CP01 Change in the name or title of a patent holder

Address after: 518000 402-406, floor 4, building 4, Tianan Yungu Industrial Park, Gangtou community, Bantian street, Longgang District, Shenzhen, Guangdong Province

Patentee after: Shenzhen Sandi Yixin Electronics Co.,Ltd.

Address before: 518000 402-406, floor 4, building 4, Tianan Yungu Industrial Park, Gangtou community, Bantian street, Longgang District, Shenzhen, Guangdong Province

Patentee before: SHENZHEN SANDIYIXIN ELECTRONIC Co.,Ltd.

CP01 Change in the name or title of a patent holder