CN209784788U

CN209784788U - Data serial high-speed exchange circuit

Info

Publication number: CN209784788U
Application number: CN201920657175.8U
Authority: CN
Inventors: 郑陆君
Original assignee: SHANGHAI WEICHENG ELECTRIC EQUIPMENT CORP
Current assignee: SHANGHAI WEICHENG ELECTRIC EQUIPMENT CORP
Priority date: 2019-05-09
Filing date: 2019-05-09
Publication date: 2019-12-13
Anticipated expiration: 2029-05-09

Abstract

The utility model discloses a data serial high speed exchange circuit, its characterized in that, hardware architecture includes ARM₁Processor and ARM₂Processor, FRAM data memory, ARM₁Processor and ARM₂the processors respectively pass through I²The C data bus is connected with FRAM data memory, ARM₁Processor and ARM₂The processors are connected through INT control lines and DRDY control lines respectively. The utility model discloses a data exchange is quick, reliable between ARM treater, and hardware design is simple, reliable, low in production cost, and system debugging, maintenance, upgrading are convenient. And because the ARM processor is provided with a plurality of UART communication interfaces, the product design is convenient to change according to the user requirements, and the dual-network redundancy is designedThe communication controller is also simple, thereby improving the communication management capability of the equipment and enhancing the applicability of the equipment. The data serial high-speed exchange circuit between the two ARM processors in the communication controller is realized.

Description

Data serial high-speed exchange circuit

Technical Field

The utility model relates to a data serial high speed exchange circuit especially relates to the realization of the high speed exchange of data serial between two ARM treater in the communication controller, belongs to the industrial production control in-process, computer monitoring device and intelligent long-range IO data acquisition device's data communication field.

Background

In the industrial production control process, in order to save the cost of signal cables and engineering installation, an intelligent remote I/O data acquisition device is installed in a local mode, the data acquisition devices are connected through twisted-pair lines to form a distributed measurement system, and then measurement data are transmitted to a control room monitoring device through a field communication bus. The measurement data of the intelligent remote I/O data acquisition device is remotely transmitted in a digital quantity mode, so that the intelligent remote I/O data acquisition device has the advantages of strong anti-interference capability and low on-site installation engineering cost, and is widely applied to industrial production processes.

In order to better realize data communication between the computer monitoring device and the intelligent remote I/O data acquisition device, a communication controller is often used for relay communication service management. Because the communication controller generally adopts a double-CPU working mode, the real-time performance and the reliability of data communication are improved.

Fig. 1 is a schematic block diagram of a communication controller using a conventional technology, and a system hardware structure mainly includes two MCU microprocessors and a dual-port RAM circuit with a capacity of 8 kbytes. Wherein, the microprocessor MCU₁Data read-write with double-port RAM is performed by address bus A_0L～A_12LData bus D_0L～D_7LAnd a control line C_0L～C_4LCompleting the matching; microprocessor MCU₂Data read-write with double-port RAM is performed by address bus A_0R～A_12RData bus D_0R～D_7RAnd a control line C_0R～C_4RAnd completing the matching.

The working process is as follows:

Microprocessor MCU₁Through RS485 field bus network, the measurement data of the field intelligent remote I/O data acquisition device is requested in a master-slave communication mode and written into the dual-port RAM, and the MCU₂and according to the DCS request command of the distributed control system, taking out the data from the double-port RAM, and transmitting the data to the DCS through the corresponding RS485 field bus network.

by adopting the hardware structure, the system communication data update time is controlled by the MCU₁The measurement data decision is obtained from the intelligent remote I/O data acquisition device. Taking communication baud rate of 57600bps, 8-bit data bit, 1-bit start bit, 1-bit check bit and 1-bit stop bit in communication mode as an example, about 13 mm is needed for communicating 64 bytes of data at a timeSecond time (64 × 11/57600 ≈ 0.013 seconds), and considering the communication timeout margin, the communication time period of each device is set to 30 milliseconds, so that about 2 seconds are required for obtaining the measurement data of 64 intelligent remote I/O data acquisition devices.

Because of the MCU of the microprocessor₁A microprocessor MCU connected with the dual-port RAM via bus₁The time for writing the data obtained by communication into the dual-port RAM is negligible. But in bus connection mode, a microprocessor MCU₁MCU of microprocessor₂The number of the connecting lines with the double-port RAM with the capacity of 8 kbytes is 26 respectively, so that the design of a PCB circuit board is complex, the design size of the circuit board cannot be made very small, the hardware cost is high, and if the data storage capacity of the double-port RAM needs to be changed in application (for example, 8 kbytes are upgraded to 16 kbytes), the hardware needs to be redesigned, the research and development period and the cost of products are increased, and the maintenance of products at the later stage is difficult.

Disclosure of Invention

The to-be-solved technical problem of the utility model is: the problem of how to simplify the hardware design structure of communication controller, reduce cost, be convenient for later stage product upgrading, maintenance through changing the data interchange hardware mode between the treater is solved.

In order to solve the technical problem, the technical solution of the present invention is to provide a data serial high-speed switching circuit, which is characterized in that the hardware structure comprises an ARM machine₁Processor and ARM₂Processor, FRAM data memory, ARM₁Processor and ARM₂The processors respectively pass through I²The C data bus is connected with FRAM data memory, ARM₁processor and ARM₂the processors are connected through INT control lines and DRDY control lines respectively.

Preferably, said I²The C data bus is a serial bus formed by the data line SDA and the clock signal line SCL.

The utility model discloses an ARM₁Processor and ARM₂The processor and the FRAM data memory can be selected from small-sized devices, the connection between the devices is simple, and the capacity of the FRAM data memory is changed if the application needs to be changed (such as upgrading from 8 Kbytes to 16 Kwords)Section), the hardware design does not need to be changed, and only the model of the FRAM data memory needs to be changed. Therefore, the PCB circuit board is simple and convenient in design, the design size can be made very small, and the hardware production cost is low.

The utility model discloses a data exchange is quick, reliable between ARM treater, and hardware design is simple, reliable, low in production cost, and system debugging, maintenance, upgrading are convenient. And because the ARM processor is provided with a plurality of UART communication interfaces, the product design is convenient to change according to the user requirements, and the design of the dual-network redundant communication controller is simple, so that the communication management capability of the equipment is improved, and the applicability of the equipment is enhanced. The data serial high-speed exchange circuit between the two ARM processors in the communication controller is realized.

Drawings

FIG. 1 is a schematic block diagram of a communications controller using conventional technology;

Fig. 2 is a schematic diagram of a serial high-speed switching circuit for data.

Detailed Description

In order to make the present invention more comprehensible, preferred embodiments are described in detail below with reference to the accompanying drawings.

The utility model relates to a data serial high speed switching circuit, as shown in fig. 2, its hardware architecture mainly comprises two ARM processors, a FRAM data memory FM24CL 64. ARM₁processor and ARM₂Processor pass through I²The C data bus (SDA, SCL) is connected with FRAM data memory, ARM₁Processor and ARM₂The processors are connected by INT and DRDY control lines. Because the system does not need a complex parallel data bus, each device can be selected to be a small-size device, and the connection between the devices is simple. Therefore, the PCB circuit board is simple and convenient in design, the design size can be made very small, and the hardware production cost is low.

ARM₁Processor and ARM₂The data serial high-speed exchange process between the processors is as follows:

(1) The RS485 communication baud rate adopts 57600bps, 8-bit data bits, 1-bit start bits, 1-bit check bits and 1-bit stop bits in a communication mode are taken as examples, about 13 milliseconds are needed for communicating 64 bytes of data at a time, the communication timeout time margin is considered, and the communication time period of each device is set to be 30 milliseconds;

(2)ARM₁The processor sets INT and DRDY control lines to be in a high level;

(3)ARM₁The processor requests the measurement data of the 01# intelligent remote I/O data acquisition device through the RS485 bus network, and the measurement data passes through the I²C data buses (SDA, SCL) write data into the FRAM data memory; if I²The C bus rate is 400kHz, and 64 bytes of data are written to the FRAM in more than 1 millisecond, which is negligible in application for a device communication cycle of 30 milliseconds.

(4) Setting DRDY control line to low level, setting INT interrupt control line to low level, and triggering ARM₂An external interrupt to the processor informing it that data can be read;

(5)ARM₂The processor enters an external interrupt service program, in order to prevent false triggering interrupt, the level of a DRDY control line is judged to ensure, if the DRDY line is in a high level, the interrupt is quitted, and if the DRDY line is in a low level, the interrupt is judged through I²A C data bus (SDA, SCL) for reading data from the FRAM data memory;

(6)ARM₂And the processor transmits the command to the DCS system through the corresponding RS485 field bus network according to the DCS request command of the distributed control system.

(7)02# -64 # intelligent remote I/O data acquisition device, ARM₁Processor and ARM₂The serial high-speed switching process between processors is as described above.

Claims

1. A data serial high-speed exchange circuit is characterized in that the hardware structure comprises an ARM₁Processor and ARM₂Processor, FRAM data memory, ARM₁Processor and ARM₂The processors respectively pass through I²The C data bus is connected with FRAM data memory, ARM₁Processor and ARM₂The processors are connected through INT control lines and DRDY control lines respectively.

2. A data serial high speed switching circuit according to claim 1, wherein said I is²The C data bus is a serial bus formed by the data line SDA and the clock signal line SCL.