CN209692943U - The video encoding device of high standard definition video compatible - Google Patents
The video encoding device of high standard definition video compatible Download PDFInfo
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- CN209692943U CN209692943U CN201920982940.3U CN201920982940U CN209692943U CN 209692943 U CN209692943 U CN 209692943U CN 201920982940 U CN201920982940 U CN 201920982940U CN 209692943 U CN209692943 U CN 209692943U
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Abstract
The utility model relates to video and audio frequency technology applications fields, more particularly, to a kind of video encoding device of high standard definition video compatible, comprising: FPGA signal processing chip, video and audio serioparallel exchange chip, video encoding processing chip, IP network processing module, ASI interface chip and Remote Management of Network module；The utility model structure is simple, flows the processing of signal to TS by FPGA signal processing chip, reduces the shake of PCR, enrich coding mode, while reducing the power consumption of equipment.Quality of coded picture can be improved in the utility model, and stablizes output.The utility model can reduce power consumption, advantageously reduce chip calorific value, promote the chip service life.
Description
Technical field
The utility model relates to video and audio frequency technology applications fields, more particularly, to a kind of video encoding of high standard definition video compatible
Device.
Background technique
Video encoder may be generally divided into two kinds, and one is hard coded, so-called hard coded is exactly to pass through specialized chip
The coding of realization, this chip sole duty function is exactly to encode, and expansion is bad, cannot arbitrarily increase function, advantage be it is stable, at
This is low, and controllability is good, is delayed low.Another coding mode is exactly soft coding, and this coding mode is established on powerful CPU,
Such as the CPU of Intel, because the complicated algorithm of coding is all to need a powerful CPU to locate by software realization
Reason, this coding mode advantage is that expansion is fine, can increase and decrease encoding function by modifying software, the disadvantage is that it is at high cost, specially
CPU is expensive.In current hard coded, common coded format mainly has MPEG-2, H.264, H.265 and AVS+
Deng certain most common or MPEG-2 and H.264 both coded formats.With both coding modes to video and audio
Coding, compression efficiency and picture quality H.264 is much higher, but many terminal devices can only be supported currently on the market
MPEG-2 coding mode, it is therefore preferred that two kinds of coding modes are all supported preferably, and many video encoders only support it at present
One of coding mode, other coding modes cannot be compatible with.Furthermore an important index of encoder is exactly program reference
The shake of clock PCR (Program Clock Reference) reduces PCR shake, it is necessary to rectify to it to greatest extent
Just, more accurate PCR, what decoding end could be stable is decoded, to guarantee the quality of image.
Therefore, as follows the shortcomings that the prior art:
1), during realizing coding, existing coding mode is more single, and many schemes can only support one of volume
Code mode.
2), in the control corrected to PCR, because PCR causes PCR shake very big, to influence to solve not by processing
The decoding at code end, and then cause image unstable.
3), power problems because encoder be real-time coding, but no signal input when, whole system be also
Running, so power consumption is very big.
The information disclosed in the background technology section is intended only to deepen the understanding to the general background technology of the application, and
It is not construed as recognizing or implying in any form that the information constitutes the prior art known to those skilled in the art.
Utility model content
The purpose of this utility model is to provide a kind of video encoding devices of high standard definition video compatible, to solve existing skill
Technical problem present in art.
To achieve the goals above, the utility model uses following technical scheme:
The utility model provides a kind of video encoding device of high standard definition video compatible comprising: FPGA signal processing core
Piece, video and audio serioparallel exchange chip, video encoding processing chip, IP network processing module, ASI interface chip and telecommunication network
Management module；
Wherein, the video and audio serioparallel exchange chip is connect with video encoding processing chip, the video and audio string
And conversion chip is used to convert SDI serial signal to the vision signal and audio signal of separation, and exports vision signal and sound
Frequency signal handles chip to the video encoding；
Wherein, the video encoding processing chip is connect with the FPGA signal processing chip, the video encoding
It handles chip to be used to carry out coded treatment to the vision signal and audio signal of input, and exports TS and flow at the FPGA signal
Manage chip；
Wherein, the FPGA signal processing chip is handled with the video and audio serioparallel exchange chip, video encoding respectively
Chip, IP network processing module, ASI interface chip are connected with Remote Management of Network module, and the FPGA signal processing chip is used
In the untreated TS stream signal progress PCR correction to input, and TS stream signal gives the ASI interface core by treated
Piece, the signal of the FPGA signal processing chip also real-time detection input, when detecting that signal disconnects, output resets letter immediately
Number to the video encoding handle chip, the IP network processing module, the ASI interface chip；
Wherein, the IP network processing module through the FPGA signal processing chip treated TS stream signal for that will lead to
Network is crossed to be output to the outside；
Wherein, the ASI interface chip will be for that will flow signal parallel through the FPGA signal processing chip treated TS
Signal serialization, and 8B/10B coding is carried out, output meets the signal of DVB-ASI standard；
Wherein, the Remote Management of Network module is used to carry out data exchange with the FPGA signal processing chip, and rings
The configuring request of remote external webpage is answered to carry out human-computer interaction.
As a kind of further technical solution, the video and audio serioparallel exchange chip is video and audio serioparallel exchange chip
GS2971A。
As a kind of further technical solution, the video encoding processing chip is video encoding chip
MB86M21A。
As a kind of further technical solution, the ASI interface chip is ASI interface chip CY7B923.
By adopting the above technical scheme, the utility model has the following beneficial effects:
1), the utility model structure is simple, flows the processing of signal to TS by FPGA signal processing chip, reduces PCR
Shake, enrich coding mode, while reducing the power consumption of equipment.
2), the utility model improves quality of coded picture, and stablizes output.
3), the utility model reduces power consumption, advantageously reduces chip calorific value, promotes the chip service life.
Detailed description of the invention
It, below will be right in order to illustrate more clearly of specific embodiment of the present invention or technical solution in the prior art
Specific embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, it is described below
In attached drawing be that some embodiments of the utility model are not paying creativeness for those of ordinary skill in the art
Under the premise of labour, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the schematic diagram of the video encoding device of high standard definition video compatible provided by the embodiment of the utility model；
Fig. 2 is the process flow diagram of the correction of PCR provided by the embodiment of the utility model.
Specific embodiment
The technical solution of the utility model is clearly and completely described below in conjunction with attached drawing, it is clear that described
Embodiment is the utility model a part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, originally
Field those of ordinary skill every other embodiment obtained without making creative work belongs to practical
Novel protected range.
It is in the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", " perpendicular
Directly ", the orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, and is only
For ease of description the utility model and simplify description, rather than the device or element of indication or suggestion meaning must have it is specific
Orientation, be constructed and operated in a specific orientation, therefore should not be understood as limiting the present invention.In addition, term " the
One ", " second ", " third " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " is pacified
Dress ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or one
Connection；It can be mechanical connection, be also possible to be electrically connected；Can be directly connected, can also indirectly connected through an intermediary,
It can be the connection inside two elements.For the ordinary skill in the art, on can understanding as the case may be
State the concrete meaning of term in the present invention.
Specific embodiment of the present utility model is described in detail below in conjunction with attached drawing.It should be understood that herein
Described specific embodiment is only used for describing and explaining the present invention, and is not intended to limit the utility model.
As shown in connection with fig. 1, the present embodiment provides a kind of video encoding devices of high standard definition video compatible comprising: FPGA
Signal processing chip 6, video and audio serioparallel exchange chip 1, video encoding handle chip 2, IP network processing module 3, ASI interface
Chip 4 and Remote Management of Network module 5；
Wherein, the video and audio serioparallel exchange chip 1 is connect with video encoding processing chip 2, the video and audio
Serioparallel exchange chip 1 is used to convert SDI serial signal to the vision signal and audio signal of separation, and export vision signal and
Audio signal handles chip 2 to the video encoding；
Wherein, the video encoding processing chip 2 is connect with the FPGA signal processing chip 6, and the video and audio is compiled
Code processing chip 2 is used to carry out coded treatment to the vision signal and audio signal of input, and exports TS and flow and believe to the FPGA
Number processing chip 6；
Wherein, the FPGA signal processing chip 6 is respectively and at the video and audio serioparallel exchange chip 1, video encoding
It manages chip 2, IP network processing module 3, ASI interface chip 4 and Remote Management of Network module 5 to connect, the FPGA signal processing
Chip 6 is used to carry out PCR correction to the untreated TS stream signal of input (to carry out PCR by FPGA signal processing chip 6
Correction, reduces the shake of PCR, exports stable PCR clock), and TS stream signal gives the ASI interface chip by treated
4, the signal of the FPGA signal processing chip 6 also real-time detection input, when detecting that signal disconnects, output resets letter immediately
Number to the video encoding processing chip 2, the IP network processing module 3, the ASI interface chip 4 (pass through judgement view sound
The LOCK signal of frequency serioparallel exchange chip 1 is believed so that system works in normal mode or battery saving mode in addition, not having to LOCK
Number, but the related register by reading chip, also can decide whether signal)；
Wherein, the IP network processing module 3 will be for that will flow signal through the FPGA signal processing chip 6 treated TS
It is output to the outside by network；
Wherein, the ASI interface chip 4 is for will be through the FPGA signal processing chip 6 treated TS stream signal simultaneously
The serialization of row signal, and 8B/10B coding is carried out, output meets the signal of DVB-ASI standard；
Wherein, the Remote Management of Network module 5 is used to carry out data exchange with the FPGA signal processing chip 6, and
The configuring request of remote external webpage is responded to carry out human-computer interaction.
In the present embodiment, as a kind of further technical solution, the video and audio serioparallel exchange chip 1 is video and audio string
And conversion chip GS2971A.
In the present embodiment, as a kind of further technical solution, the video encoding processing chip 2 is video and audio volume
Code chip MB86M21A, is controlled it by FPGA signal processing chip, so that coded format H.264 can with MPEG-2
Choosing.
In the present embodiment, as a kind of further technical solution, the ASI interface chip 4 is ASI interface chip
CY7B923。
The working principle of the present embodiment is as follows:
After the sdi signal of standard is input to video and audio serioparallel exchange chip GS2971A, video and audio serioparallel exchange chip
The LOCK signal that GS2971A can generate a high level gives FPGA signal processing chip, while exporting vision signal and audio letter
Number, video encoding chip MB86M21A starts to encode upon receipt of the signals, according to host computer to the coding lattice of network management module
Formula configuration, selection is H.264 or MPEG-2 coded format, this coding chip support two kinds of coded formats.Video encoding core
After piece MB86M21A output code flow, need to handle TS stream in FPGA signal processing chip, it is during the treatment, right
Data carry out the operation such as caching, and destroy the temporal information of legacy data, so to correct to this time, can pass through
The correction of PCR obtains satisfied result.Treatment process is as shown in Fig. 2, obtain the PCR information in TS stream, it is assumed that this PCR is
PCR1, while starting local counter and being counted, it is assumed that this counter is now T1, and TS flows the In after a series of processing
When TS stream will export, stop local counter, it is assumed that this hour counter is T2, then new PCR value, it is assumed that be
PCR2, then PCR2=PCR1+ (T2-T1), is then inserted into this new PCR2 in TS stream and exports.When LOCK is low level
When, it represents no signal input or signal format input is wrong, reset signal is at this time triggered, so that system is in power saving mould
Formula, especially coding chip drop to the 0.3W of battery saving mode from the 1.2W of operating mode, and effect is particularly evident, while reducing chip
Calorific value, to extend chip service life.
To sum up, by adopting the above technical scheme, the utility model has the following beneficial effects:
1), the utility model structure is simple, flows the processing of signal to TS by FPGA signal processing chip, reduces PCR
Shake, enrich coding mode, while reducing the power consumption of equipment.
2), the utility model improves quality of coded picture, and stablizes output.
3), the utility model reduces power consumption, advantageously reduces chip calorific value, promotes the chip service life.
Finally, it should be noted that the above various embodiments is only to illustrate the technical solution of the utility model, rather than it is limited
System；Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should
Understand: it is still possible to modify the technical solutions described in the foregoing embodiments, or to some or all of
Technical characteristic is equivalently replaced；And these are modified or replaceed, it does not separate the essence of the corresponding technical solution, and this is practical new
The range of each embodiment technical solution of type.
Claims (4)
1. a kind of video encoding device of high standard definition video compatible characterized by comprising FPGA signal processing chip, view sound
Frequency serioparallel exchange chip, video encoding processing chip, IP network processing module, ASI interface chip and Remote Management of Network mould
Block；
Wherein, the video and audio serioparallel exchange chip is connect with video encoding processing chip, and the video and audio string simultaneously turns
Chip is changed for converting SDI serial signal to the vision signal and audio signal of separation, and exports vision signal and audio letter
Number to the video encoding handle chip；
Wherein, the video encoding processing chip is connect with the FPGA signal processing chip, the video encoding processing
Chip is used to carry out coded treatment to the vision signal and audio signal of input, and exports TS and flow to the FPGA signal processing core
Piece；
Wherein, the FPGA signal processing chip respectively with the video and audio serioparallel exchange chip, video encoding processing chip,
IP network processing module, ASI interface chip are connected with Remote Management of Network module, and the FPGA signal processing chip is used for defeated
The untreated TS stream signal entered carries out PCR correction, and TS stream signal gives the ASI interface chip by treated, described
The signal of FPGA signal processing chip also real-time detection input, when detecting that signal disconnects, output reset signal is to institute immediately
State video encoding processing chip, the IP network processing module, the ASI interface chip；
Wherein, the IP network processing module will be for that will pass through net through the FPGA signal processing chip treated TS stream signal
Network is output to the outside；
Wherein, the ASI interface chip will be for that will flow signal parallel signal through the FPGA signal processing chip treated TS
Serialization, and 8B/10B coding is carried out, output meets the signal of DVB-ASI standard；
Wherein, the Remote Management of Network module is used to carry out data exchange with the FPGA signal processing chip, and responds remote
The configuring request of journey external web page is to carry out human-computer interaction.
2. the video encoding device of high standard definition video compatible according to claim 1, which is characterized in that the video and audio string
And conversion chip is video and audio serioparallel exchange chip GS2971A.
3. the video encoding device of high standard definition video compatible according to claim 1, which is characterized in that the video and audio is compiled
Code processing chip is video encoding chip MB86M21A.
4. the video encoding device of high standard definition video compatible according to claim 1, which is characterized in that the ASI interface
Chip is ASI interface chip CY7B923.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920982940.3U CN209692943U (en) | 2019-06-27 | 2019-06-27 | The video encoding device of high standard definition video compatible |
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| CN201920982940.3U CN209692943U (en) | 2019-06-27 | 2019-06-27 | The video encoding device of high standard definition video compatible |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111757128A (en) * | 2020-07-16 | 2020-10-09 | 威创集团股份有限公司 | Video coding system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111757128A (en) * | 2020-07-16 | 2020-10-09 | 威创集团股份有限公司 | Video coding system |
| CN111757128B (en) * | 2020-07-16 | 2021-12-07 | 威创集团股份有限公司 | Video coding system |
| WO2022011989A1 (en) * | 2020-07-16 | 2022-01-20 | 威创集团股份有限公司 | Video coding system |
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