CN111757128A - Video coding system - Google Patents
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- CN111757128A CN111757128A CN202010685649.7A CN202010685649A CN111757128A CN 111757128 A CN111757128 A CN 111757128A CN 202010685649 A CN202010685649 A CN 202010685649A CN 111757128 A CN111757128 A CN 111757128A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
Abstract
The application discloses a video coding system, comprising: the device comprises a control module, a deserializing and image processing module, a video coding module, a first conversion protocol module and a switch module which are sequentially connected; the control module is respectively connected with the deserializing and image processing module, the video coding module and the switch module; and the local output module is connected with the deserializing and image processing module. The method and the device solve the technical problems that the existing video coding system is difficult to apply to a flexible scheduling scene, and once the existing video coding system is applied to the flexible scheduling scene, the system scale is increased, and the complexity is high.
Description
Technical Field
The present application relates to the field of video coding technology, and in particular, to a video coding system.
Background
A common method for real-time encoding and transmitting video is generally that a front-end video signal source inputs a video data processing module in a system module through a standard video interface, transmits a processed video signal stream to an h.264 encoder, and outputs an encoded video signal to an IP network through a network port. Because the input interface signals of the front end of the system module are more, the system module is not suitable for real-time flexible scheduling of the video signal source at the front end. And the H.264 encoder is not high in coding compression efficiency, relatively low in bandwidth utilization rate and difficult to support in the application of the ultrahigh-definition video above K.
In the prior art, input video streams are only suitable for standard interface video signal streams, and are difficult to realize in a front-end flexible scheduling scene such as the field of a splicing wall, and the complexity of a front-end system is increased and the reliability is reduced by simultaneous scheduling of multiple video channels. In addition, in the prior art, the audio and video are respectively encoded by splitting the audio and video encoding module, which may result in an increase in the complexity of the system. Under the scheduling and using scene of multi-picture and high bandwidth, the scale of the system is greatly increased by the existing system, so that the complexity of the whole scheme is higher.
Disclosure of Invention
The embodiment of the application provides a video coding system, and the technical problems that the conventional video coding system is difficult to apply to a flexible scheduling scene, and once the conventional video coding system is applied to the flexible scheduling scene, the system scale is increased, and the complexity is high are solved.
In view of the above, the present application provides a video encoding system, the system comprising:
the device comprises a control module, a deserializing and image processing module, a video coding module, a first conversion protocol module and a switch module which are sequentially connected;
the control module is respectively connected with the deserializing and image processing module, the video coding module and the switch module;
the local output module is connected with the deserializing and image processing module;
the control module is used for managing the starting and running states of the video coding system;
the deserializing and image processing module is used for deserializing a serial video signal input into the video coding system and recovering the deserialized video signal to original video data;
the video coding module is used for carrying out video coding on the original video data and outputting a video code stream;
the first conversion protocol module is used for carrying out protocol conversion on the video code stream and inputting data after the protocol conversion to the switch module;
the switch module is used for outputting the data after the protocol conversion to a wide area network;
the local output module is used for receiving the original video data output by the deserializing and image processing module and converting the original video data into a standard format image for output.
Optionally, the control module further includes an alarm module;
the alarm module is used for sending out an alarm signal when detecting that the running state is abnormal.
Optionally, the deserializing and image processing module includes an FPGA chip;
the device is used for deserializing a high-bandwidth serial video signal input into a video coding system and recovering original video data from the deserialized video signal under a horizontal field synchronous clock.
Optionally, the local output module includes an HDMI interface chip;
and the system is used for receiving the original video data output by the deserializing and image processing module and converting the original video data into a standard HDMI image for output.
Optionally, the local output module includes an HDMI interface chip;
and the system is used for receiving the original video data output by the deserializing and image processing module and converting the original video data into a standard HDMI image for output.
Optionally, the video encoding module includes an h.265 encoder;
and the video coding module is used for carrying out video coding on the original video data and outputting a code stream in an H.265 coding format.
Optionally, a local code stream output module connected to the video coding module;
and the video code stream is output to local equipment.
Optionally, the system further comprises a network port module connected to the switch module;
the network port module is used for connecting network equipment in a wide area network, and data output by the switch module is input into the wide area network through the network port module.
Optionally, the system further includes a second protocol conversion module connected to the switch module;
the second protocol conversion module is used for carrying out protocol conversion on the data output by the switch module and converting the data into data transmitted in an optical fiber network.
Optionally, the optical transceiver further comprises an optical port module connected to the second protocol conversion module;
the optical port module is used for connecting to an optical fiber network, the data output by the second protocol conversion module is input to the optical fiber network through the optical port module,
according to the technical scheme, the method has the following advantages:
the application provides a video coding system, which comprises a control module, a deserializing and image processing module, a video coding module, a first conversion protocol module and a switch module, wherein the deserializing and image processing module, the video coding module, the first conversion protocol module and the switch module are sequentially connected; the control module is respectively connected with the deserializing and image processing module, the video coding module and the switch module; the local output module is connected with the deserializing and image processing module; the control module is used for managing the starting and running states of the video coding system; the deserializing and image processing module is used for deserializing a serial video signal input into the video coding system and recovering the deserialized video signal to original video data; the video coding module is used for carrying out video coding on the original video data and outputting a video code stream; the first conversion protocol module is used for carrying out protocol conversion on the video code stream and inputting the data after the protocol conversion into the switch module; the switch module is used for outputting the data after the protocol conversion to a wide area network; the local output module is used for receiving the original video data output by the deserializing and image processing module and converting the original video data into a standard format image for output.
According to the method, the audio and video signals are rapidly deserialized and restored by adopting the deserializing and image processing module aiming at the audio and video input in the flexible scheduling scene, and the restored video and audio data can be respectively used for being output to the local or the wide area network; the restored original video data can be encoded through an encoder unit and used for outputting a code stream to local storage or outputting the code stream to a wide area network for use by more users; the control module is used for controlling the deserializing and image processing module, the video coding module and the switch module, so that the running state of the system can be monitored in real time, and a response can be made in real time. According to the method and the device, the deserializing and image processing module, the video coding module and the switch module are jointly scheduled through the control module, the input of multiple paths of signals can be processed in real time, and the simultaneous scheduling of multiple paths of video channels can be well controlled.
Drawings
FIG. 1 is a system architecture diagram of one embodiment of a video encoding system of the present application;
FIG. 2 is a system architecture diagram of another embodiment of a video encoding system of the present application;
FIG. 3 is a schematic diagram of a prior art configuration;
fig. 4 is a schematic structural diagram of another prior art.
Detailed Description
Fig. 3 shows a prior art structure diagram, the system includes a video interface module, an h.264 coding module, a physical layer interface chip, a gigabit switch, and a gigabit port connected in this way. The video interface module collects and analyzes the input standard video, then transmits the standard video to the H.264 coding module for compression coding, and accesses to the IP network through the kilomega switch after the physical layer protocol conversion, and outputs the video code stream. The technical scheme has the problems that the input video stream is only suitable for the video signal stream with the standard interface, the realization is difficult in the field of splicing walls under the flexible scheduling scene of the front end, the complexity of the front end system is increased by simultaneous scheduling of multiple paths of video channels, and the reliability is reduced.
As shown in fig. 4, another prior art structure diagram includes an input serial-to-parallel conversion and audio de-embedding module, a video processing module, an h.265 encoder, an audio encoding module, an audio-video multiplexing module, and an IP video stream output module. The input serial-parallel conversion and audio de-embedding module converts an input standard video signal stream into a parallel video signal, analyzes the audio signal therein, respectively transmits the video processing module and the audio coding module, the processed video data can be sent to an H.265 coder for compression coding, the coded video and audio data can be simultaneously transmitted to the audio-video multiplexing module, the audio-video multiplexing module multiplexes and combines two code streams and then outputs the two code streams to the IP video stream output module, thereby completing the real-time coding and transmission of the video.
According to the method, the audio and video signals are rapidly deserialized and restored by adopting the deserializing and image processing module aiming at the audio and video input in the flexible scheduling scene, and the restored video and audio data can be respectively used for being output to the local or the wide area network; the restored original video data can be encoded through an encoder unit and used for outputting a code stream to local storage or outputting the code stream to a wide area network for use by more users; the control module is used for controlling the deserializing and image processing module, the video coding module and the switch module, so that the running state of the system can be monitored in real time, and a response can be made in real time. According to the method and the device, the deserializing and image processing module, the video coding module and the switch module are jointly scheduled through the control module, the input of multiple paths of signals can be processed in real time, and the simultaneous scheduling of multiple paths of video channels can be well controlled. The technical scheme has the problem that the complexity of the system is improved by respectively encoding the audio and the video by adopting a mode of splitting an audio and video encoding module. Under the scheduling and using scene of multi-picture and high bandwidth, the scale of the system is greatly increased by the existing system, so that the complexity of the whole scheme is higher.
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a system architecture diagram of an embodiment of a video coding system according to the present application, as shown in fig. 1, fig. 1 includes:
a control module 101, and a deserializing and image processing module 102, a video coding module 103, a first conversion protocol module 104 and a switch module 105 which are connected in sequence;
the control module 101 is respectively connected with the deserializing and image processing module 102, the video coding module 103 and the switch module 105;
also included is a local output module 106 coupled to the deserializing and image processing module 102;
the control module 101 is used for managing the starting and running states of the video coding system;
the deserializing and image processing module 102 is configured to deserialize a serial video signal input to the video coding system and restore the deserialized video signal to original video data;
the video coding module 103 is configured to perform video coding on the original video data and output a video code stream;
the first conversion protocol module 104 is configured to perform protocol conversion on the video code stream, and input data after the protocol conversion to the switch module 105;
the switch module 105 is configured to output the data after the protocol conversion to the wide area network;
the local output module 106 is configured to receive the original video data output by the deserializing and image processing module, and convert the original video data into an image with a standard format for output.
Specifically, the input in the present application may be a multi-channel video signal with a high bandwidth as an input, that is, a multi-channel serial video signal may be received simultaneously, and simultaneously, audio data corresponding to a picture may also be input together with the video signal; the input signal firstly enters the deserializing and image processing module 102, deserializing of a plurality of paths of video signals is completed in the deserializing and image processing module 102, a plurality of deserialized video signals are restored to original video data, and operations such as image superposition and/or zooming can be carried out on the original video data; the video signal processed by the deserializing and image processing module 102 can be converted into a video with a standard format suitable for local output by the local output module 106, and is used for local output, for example, multiple paths of video data can be output on a local video wall device; the video signal processed by the deserializing and image processing module 102 can also be compressed and encoded by the video encoding module 103, and the compressed video code stream data can be stored locally or transmitted to a wide area network for other users; specifically, the video stream data transmitted to the wan may first pass through the first protocol conversion module 104, and is used to perform protocol conversion on the video stream data, so as to be able to be transmitted in the wan; the data after protocol conversion can pass through the switch module, so that the video data can interact with the wide area network. In addition, the system also comprises a control module which is connected with the image processing module 102, the video coding module 103 and the switch module 105 through control to control the processes of video de-serialization, image processing, video coding, network interaction and the like, so that the starting and running states of the video coding system are monitored, and the video stream is scheduled.
According to the method, the audio and video signals are rapidly deserialized and restored by adopting the deserializing and image processing module aiming at the audio and video input in the flexible scheduling scene, and the restored video and audio data can be respectively used for being output to the local or the wide area network; the restored original video data can be encoded through an encoder unit and used for outputting a code stream to local storage or outputting the code stream to a wide area network for use by more users; the control module is used for controlling the deserializing and image processing module, the video coding module and the switch module, so that the running state of the system can be monitored in real time, and a response can be made in real time. According to the method and the device, the deserializing and image processing module, the video coding module and the switch module are jointly scheduled through the control module, the input of multiple paths of signals can be processed in real time, and the simultaneous scheduling of multiple paths of video channels can be well controlled.
In a specific embodiment, the control module 101 further comprises an alarm module; the alarm module is used for sending out an alarm signal when detecting that the running state is abnormal.
It should be noted that, when the deserializing and image processing module, the video coding module and the switch module in the system are abnormal in operation state, the control module may monitor the abnormal signal in real time and send out an alarm signal.
In one specific embodiment, the deserializing and image processing module 102 comprises an FPGA chip; the device is used for deserializing a high-bandwidth serial video signal input into a video coding system and recovering original video data from the deserialized video signal under a horizontal field synchronous clock.
It should be noted that, in the present application, the FPGA chip can directly receive the input high-bandwidth serial video signal, deserialize the high-bandwidth serial video signal inside the FPGA, and then restore the video signal to the original video data under the horizontal-field synchronous clock; in addition, image processing including but not limited to image superposition and scaling can be completed inside the FPGA.
In a specific embodiment, the local output module comprises an HDMI interface chip; and the device is used for receiving the original video data output by the deserializing and image processing module, and converting the original video data into a standard HDMI image for output.
It should be noted that the HDMI interface chip can convert the processed video data output by the FPGA chip into a standard HDMI image for output, and output the standard HDMI image to a local playback device.
In a specific embodiment, the number of the HDMI interface chips is multiple; the plurality of HDMI interface chips are used for outputting the multi-path standard HDMI images locally.
It should be noted that, the plurality of HDMI interface chips may convert all of the plurality of video data output by the FPGA chip into a standard HDMI image for output, for example, the standard HDMI image may be output to a local mosaic wall.
In one particular embodiment, the video encoding module 103 includes an h.265 encoder; the video coding device is used for carrying out video coding on original video data and outputting a code stream in an H.265 coding format.
It should be noted that, the video data output by the FPGA chip is encoded by using the h.265 encoder, so that the video compression efficiency can be improved, and the video data can be used to play ultra-high-definition video data.
In a specific embodiment, the video coding device further comprises a local code stream output module connected to the video coding module 103; and the video code stream is output to the local equipment.
It should be noted that the local code stream output module may be configured to output the video code stream data encoded by the h.265 encoder to the local for storage.
In a specific embodiment, the network interface module further comprises a network interface module connected with the switch module 105; the network port module is used for connecting network equipment in a wide area network, and data output by the switch module 105 is input into the wide area network through the network port module.
In a specific embodiment, the system further comprises a second protocol conversion module connected to the switch module; the second protocol conversion module is used for carrying out protocol conversion on the data output by the switch module and converting the data into data transmitted in the optical fiber network.
In a specific embodiment, the system further comprises an optical interface module connected to the second protocol conversion module; the optical port module is used for being connected to an optical fiber network, and data output by the second protocol conversion module is input into the optical fiber network through the optical port module.
It should be noted that, after the video code stream data encoded by the h.265 encoder is subjected to protocol conversion, the video code stream data may flow into the wide area network through the network port through the switch module 105; or after protocol conversion, the data is converted into a protocol format suitable for transmission in the optical network, so that the data after protocol conversion can enter the optical network through the optical port for transmission.
The present application further provides a system architecture diagram of another embodiment of a video coding system, as shown in fig. 2, where fig. 2 includes:
the system comprises an FPGA module, an H.265 coding module, a physical layer chip module, a kilomega switch module and a kilomega network port module which are connected in sequence; the FPGA module is respectively connected with the two HDMI interface chips; the H.265 coding module is connected with the HDMI output interface; the kilomega switch module, the physical chip layer and the kilomega optical port are sequentially connected; and the control module is respectively connected with the FPGA module, the H.265 coding module and the gigabit switch module.
When a pair of high-speed SERDES serial video signals are input, the serial video signals are deserialized and image-processed in an FPGA module, and are output to an HDMI interface chip for locally outputting two paths of video images, the processed video data are also sent to an H.265 encoder for video compression encoding, the H.265 encoder is accessed to a local area network of a gigabit switch after protocol conversion of a physical layer chip, and the H.265 encoder accessed to the network can provide video data after compression encoding for other users after being accessed to a wide area network through a network port or an optical port selected by the users; in addition, the video coding system also comprises a control module which is used for controlling the functions of starting, state monitoring and the like of each module in the system.
In the system, an FPGA directly receives an input high-bandwidth serial video signal, deserialization is completed inside the FPGA, original video data are recovered under a horizontal field synchronous clock, and image processing including but not limited to image superposition, zooming and the like is completed inside the FPGA. The processed video image information is respectively transmitted to the HDMI interface chip and the H.265 encoder, the HDMI interface chip locally outputs standard HDMI images after receiving the video image information, the H.265 encoder realizes H.265 encoding after receiving video image data, and the H.265 encoder is connected to the Ethernet to finish the output of IP video streams. The hardware circuit is also provided with a control module for managing the starting and running states of the single board, and when the device on the single board runs abnormally, the device can monitor in real time and send out a warning.
The FPGA is used as a video input interface, so that input video data can be transmitted through a pair of high-bandwidth differential SERDES signals. Multiple pairs of SERDES signals receive multiple pictures, each pair of SERDES signals having a bandwidth of up to 6Gbps, and audio corresponding to a picture is also transmitted together in the SERDES channel. The audio and video are analyzed and processed in the FPGA, and no additional processing device is needed.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
The terms "first," "second," "third," "fourth," and the like in the description of the application and the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, e.g., a system that comprises a list of modules is not necessarily limited to the explicitly listed modules, but may include other modules not expressly listed or inherent to such modules.
It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. A video coding system, comprising: the device comprises a control module, a deserializing and image processing module, a video coding module, a first conversion protocol module and a switch module which are sequentially connected;
the control module is respectively connected with the deserializing and image processing module, the video coding module and the switch module;
the local output module is connected with the deserializing and image processing module;
the control module is used for managing the starting and running states of the video coding system;
the deserializing and image processing module is used for deserializing a serial video signal input into the video coding system and recovering the deserialized video signal to original video data;
the video coding module is used for carrying out video coding on the original video data and outputting a video code stream;
the first conversion protocol module is used for carrying out protocol conversion on the video code stream and inputting data after the protocol conversion to the switch module;
the switch module is used for outputting the data after the protocol conversion to a wide area network;
the local output module is used for receiving the original video data output by the deserializing and image processing module and converting the original video data into a standard format image for output.
2. The video coding system of claim 1, wherein the control module further comprises an alarm module;
the alarm module is used for sending out an alarm signal when detecting that the running state is abnormal.
3. The video coding system of claim 1, wherein the deserializing and image processing module comprises an FPGA chip;
the device is used for deserializing a high-bandwidth serial video signal input into a video coding system and recovering original video data from the deserialized video signal under a horizontal field synchronous clock.
4. The video encoding system of claim 1, wherein the local output module comprises an HDMI interface chip;
and the system is used for receiving the original video data output by the deserializing and image processing module and converting the original video data into a standard HDMI image for output.
5. The video coding system of claim 4, wherein the number of the HDMI interface chips is plural;
the plurality of HDMI interface chips are used for outputting the multi-path standard HDMI images locally.
6. The video coding system of claim 1, wherein the video coding module comprises an h.265 coder;
and the video coding module is used for carrying out video coding on the original video data and outputting a code stream in an H.265 coding format.
7. The video coding system of claim 1, further comprising: the local code stream output module is connected with the video coding module;
and the video code stream is output to local equipment.
8. The video coding system of claim 1, further comprising a portal module connected to the switch module;
the network port module is used for connecting network equipment in a wide area network, and data output by the switch module is input into the wide area network through the network port module.
9. The video encoding system of claim 1, further comprising a second protocol conversion module coupled to the switch module;
the second protocol conversion module is used for carrying out protocol conversion on the data output by the switch module and converting the data into data transmitted in an optical fiber network.
10. The video coding system of claim 9, further comprising an optical interface module coupled to the second protocol conversion module;
the optical port module is used for being connected to an optical fiber network, and data output by the second protocol conversion module is input to the optical fiber network through the optical port module.
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| CN115550569A (en) * | 2022-11-24 | 2022-12-30 | 基石酷联微电子技术（北京）有限公司 | Audio-video transceiver and matrix system |
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| CN114760478A (en) * | 2022-03-08 | 2022-07-15 | 江苏泽汇泓智能科技有限公司 | Low code stream high definition video processing terminal and video monitoring system |
| CN114866733A (en) * | 2022-03-22 | 2022-08-05 | 感知信息科技(浙江)有限责任公司 | Low-delay video processing method, system and device |
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