CN209659345U - A kind of TS stream IP encapsulation package reception resolution system - Google Patents

Abstract

The utility model discloses a kind of TS stream IP encapsulation packages to receive resolution system, FPGA and ethernet PHY chip including interconnection, the input terminal and gigabit network interface connection of the ethernet PHY chip, for sending received TS stream IP encapsulation package to the FPGA, the FPGA includes the MAC module successively communicated to connect, IP/UDP/RTP parsing module and TS buffer control module, FPGA further includes Clock management module and ARP module, the Clock management module is for controlling the TS cushioning control module, IP/UDP/RTP parsing module, the clock signal of MAC module and ARP module, the ARP module and MAC module communicate to connect.The utility model uses the pure hardware mode of FPGA, has the characteristics that stability is high, at low cost, transplanting is flexible.

Description

A kind of TS stream IP encapsulation package reception resolution system

Technical field

The utility model relates to IP resolve packet technical fields, are a kind of TS stream IP encapsulation package reception solutions specifically Analysis system.

Background technique

With the continuous improvement of informationization technology, full IPization transmission and reception have become the important technology that traditional TS flows business Means are able to achieve the reception to TS flow data IP encapsulation package, parsing, and the method for reverting to TS stream is just particularly important.At present Realize that the technical solution for receiving parsing to TS stream IP encapsulation package mainly has software realization mode and hardware that partial software is added to realize Mode realized using cpu chip or cpu chip+DSP (FPGA) chip, these methods be primarily present it is high to cpu performance requirement, Transplant that at high cost, implementation method is not flexible.

Utility model content

The purpose of this utility model is to provide a kind of TS stream IP encapsulation packages to receive resolution system, for solving the prior art Middle hardware adds software realization to receive at high cost, the inflexible problem of implementation method of parsing transplanting to TS stream IP encapsulation package.

The utility model is solved the above problems by following technical proposals:

A kind of TS stream IP encapsulation package receives resolution system, FPGA and ethernet PHY chip including interconnection, it is described with The too input terminal of net PHY chip and gigabit network interface connection, it is described for sending received TS stream IP encapsulation package to the FPGA FPGA includes the MAC module successively communicated to connect, IP/UDP/RTP parsing module and TS buffer control module, when FPGA further includes Clock management module and ARP module, the Clock management module is for controlling the TS cushioning control module, IP/UDP/RTP parsing The clock signal of module, MAC module and ARP module, the ARP module and MAC module communicate to connect.

Further, the Clock management module provides 25MHz or 125MHz clock output.

The utility model compared with prior art, have the following advantages that and the utility model has the advantages that

(1) the utility model uses the pure hardware mode of FPGA, has the characteristics that stability is high, at low cost, transplanting is flexible.

(2) the utility model is applicable to receive the equipment and other application scenarios of the TS flow data of IP encapsulation, is to pass TS stream IPization of uniting is transmitted and receives the key technology of parsing, and internal logic all uses VHDL hardware language, is suitable for FPGA device batch production.

Detailed description of the invention

Fig. 1 is the system block diagram of the utility model；

Fig. 2 is the functional block diagram of FPGA；

Fig. 3 is IP Packet analyzing flow diagram.

Specific embodiment

The utility model is described in further detail below with reference to embodiment, but the embodiments of the present invention is not It is limited to this.

Embodiment 1:

In conjunction with shown in attached drawing 1 and Fig. 2, a kind of TS stream IP encapsulation package receives resolution system, FPGA including interconnection and Ethernet PHY chip, the input terminal and gigabit network interface connection of the ethernet PHY chip, for encapsulating received TS stream IP It includes the MAC module successively communicated to connect, IP/UDP/RTP parsing module and TS caching control that packet, which is sent to the FPGA, the FPGA, Molding block, FPGA further include Clock management module and ARP module, and the Clock management module is for controlling the TS cushioning control The clock signal of module, IP/UDP/RTP parsing module, MAC module and ARP module, the ARP module and MAC module communication link It connects, ARP module is responsible in the MAC Address for obtaining source destination IP；MAC module carries free IP using FPGA, is responsible for receiving and send out SCN Space Cable Network data.

FPGA is received by gigabit network interface to be met the TS of TCP/IP standard and flows IP data packet, by FPGA internal mac module, Under the control of internal clocking, it is sent into IP/UDP/RTP parsing module, original TS is recovered from IP/UDP/RTP data packet Flow data is re-fed into TS buffer control module, under the control processing of TS buffer control module, exports parallel TS fluxion According to, send to subordinate equipment processing.

In conjunction with shown in attached drawing 3, IP Packet analyzing process are as follows:

Under clock signal control, Frame Buffer is received from MAC treated IP data packet, is sent into MPEG It is parsed in Frame Ana module, TS flow data is parsed from IP/UDP/RTP packet；In the control of Read Control module Under system, it is sent into TS caching, eventually by TS output module, exports parallel TS flow data.

System carries out initial configuration to module and receives external user to control data, ethernet PHY by I2C bus It is responsible for the conversion of data-signal, and provides reception/tranmitting data register to FPGA.MAC driving and ethernet PHY chip driving are by FPGA Internal logic is realized.FPGA is realized recover TS flow data from IP encapsulation package in a modular manner as hardware platform.

Further, the Clock management module provides 25MHz or 125MHz clock output.

Clock management module connects according to network and provides 25Mhz or 125Mhz clock output, and system being capable of 100M and 1G net Network is adaptive.

Although reference be made herein to the utility model is described in the explanatory embodiment of the utility model, above-described embodiment The only preferable embodiment of the utility model, the embodiments of the present invention are simultaneously not restricted to the described embodiments, it should Understand, those skilled in the art can be designed that a lot of other modification and implementations, these modifications and implementations will be fallen Within scope and spirit disclosed in the present application.

Claims (2)

1. a kind of TS stream IP encapsulation package receives resolution system, which is characterized in that FPGA and ethernet PHY core including interconnection Piece, the input terminal and gigabit network interface connection of the ethernet PHY chip, for sending received TS stream IP encapsulation package to described FPGA, the FPGA include the MAC module successively communicated to connect, IP/UDP/RTP parsing module and TS buffer control module, FPGA further includes Clock management module and ARP module, the Clock management module for control the TS cushioning control module, The clock signal of IP/UDP/RTP parsing module, MAC module and ARP module, the ARP module and MAC module communicate to connect.

2. a kind of TS stream IP encapsulation package according to claim 1 receives resolution system, which is characterized in that the Clock management Module provides 25MHz or 125MHz clock output.