CN110704027B - Satellite-borne software load software and hardware decoupling method - Google Patents

Satellite-borne software load software and hardware decoupling method Download PDF

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CN110704027B
CN110704027B CN201910809759.7A CN201910809759A CN110704027B CN 110704027 B CN110704027 B CN 110704027B CN 201910809759 A CN201910809759 A CN 201910809759A CN 110704027 B CN110704027 B CN 110704027B
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方海
杨旭
白琳
陈显舟
李聪
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Xian Institute of Space Radio Technology
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Abstract

The invention provides a software and hardware decoupling method for satellite-borne software loads, which is realized by the following steps: defining a message structure, wherein the message structure comprises a message header, a message identifier and bit message content; configuring satellite-borne software in a processor, and multiplexing a logic address transmitted by a message with a bottom communication protocol address; the satellite-borne software organizes the sending message and the analyzing receiving message according to the message structure according to the message type, and realizes the communication among the satellite-borne processors through the configured bottom layer communication protocol address; the processor comprises an FPGA processor and/or a DSP and/or a CPU.

Description

Satellite-borne software load software and hardware decoupling method
Technical Field
The invention relates to a software and hardware decoupling method for a satellite-borne software load, and belongs to the technical field of satellite-borne software loads.
Background
Corresponding programs must be developed for different hardware in the implementation process of the existing space radio system, an upper application developer has to pay attention to the implementation of the bottom hardware, and when the bottom hardware is changed, the upper application is also changed, so that the portability and reusability of the system are reduced, and the difficulty and the period of software development are increased. Therefore, in order to improve the cross-platform, portability and reusability of the system, software radio technology is rapidly developed, and software and hardware decoupling is a key problem of software radio.
In order to realize the decoupling of software and hardware, an external interface of a hardware module is abstracted, and the interaction between the hardware module and the outside is independently designed, namely, a bottom layer shielding function is realized and a transparent message transmission mechanism under the heterogeneous processor environment is provided for a waveform component.
The space communication radio system (STRS) architecture standard describes a standard for NASA space software defined radio. It provides a generic framework for developing space software defined radios in a reconfigurable and reprogrammable manner. However, the STRS architecture does not currently define the standard of waveform design in FPGA hardware, and a specific method for implementing software and hardware decoupling is not given, while the FPGA is the most common device for satellite-borne signal processing.
The traditional SCA architecture provides a method for decoupling software and hardware, and in order to realize communication of components among different computing units, the MHAL method in the SCA defines a standard message format. The method comprises IU, logical address, length and Payload, wherein IU is used for internal message flow control, logical address is used for specifying the delivery destination of the message, payload is the content of the delivered message, and Length indicates the Length of Payload. The MHAL uses a datagram routing mode to solve the interconnection problem among distributed components. However, MHAL does not specify the routing of the packets, especially the routing of the packets between components under the SCA framework. No global logical address assignment is given and the MHAL design does not take into account communication efficiency issues.
Existing software radio specifications, such as the SCA specification, require that communication between waveform components be accomplished by CORBA middleware. However, only general-purpose processors (e.g., CPUs) can operate CORBA, FPGAs, and other heterogeneous processors, and cannot operate at present.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method overcomes the defects of the prior art, provides a satellite-borne software load software and hardware decoupling method, solves the problem that the satellite load function is solidified along with hardware, and meets the satellite load software requirement.
The technical solution of the invention is as follows: a satellite-borne software load software and hardware decoupling method is realized by the following steps:
defining a message structure, wherein the message structure comprises a message header, a message identifier and bit message content;
configuring satellite-borne software in a processor, and multiplexing a logic address transmitted by a message with a bottom layer communication protocol address;
the satellite-borne software organizes the sending message and the analyzing receiving message according to the message structure according to the message type, and realizes the communication among the satellite-borne processors through the configured bottom layer communication protocol address; the processor comprises an FPGA processor and/or a DSP and/or a CPU.
Preferably, the message types are divided into three types, namely command messages, data messages and response messages, and the message types are determined by message headers.
Preferably, the first M bits in the command message are a command message header, the second N bits are a command ID, and the third P bits are a command parameter;
in the response message, the first M bits are response message heads, the second N bits are response command IDs, and the third P bits are response command parameters;
the first M bits in the data message are data message heads, the second S bits are data packet serial numbers, and the subsequent T bits are transmission data;
the command ID in the response message is consistent with the command message to which the response message is to respond;
where M, N, P, S, T are integer multiples of 8 and satisfy N > = log2 (Q) at the same time, Q is the number of commands, P > = U, where U is the number of bits with the longest command parameter field in all commands, S > =32, and the value of (T + S + M) is the maximum value that does not exceed the underlying protocol payload length.
Preferably, the bottom layer communication protocol address is an address of a multiplexing bottom layer RapidIO or an ethernet protocol.
Preferably, the configuration is realized by the following mode:
if the underlying protocol adopts a RapidIO protocol, using the device address as a logical address for message transmission; if the bottom layer protocol adopts the Ethernet protocol, the logic address of the message transmission adopts the MAC address, the message exchange adopts the bottom layer switching device, and the message is forwarded according to the destination address of the message.
Preferably, the process of organizing the message sending and the message receiving is as follows:
receiving messages sent by other processors, and removing a bottom layer communication protocol header;
judging the type of the message according to the message header after removing the bottom layer communication protocol header, if the message is a command message, analyzing and executing the command according to the command code, and if the message is a data message, extracting the data and carrying out waveform function processing; generating a response message after the command is executed, and generating a data message from data generated after the waveform function processing; and adding a bottom layer communication protocol header to the generated message, transmitting the message through a bottom layer protocol, and distributing the message to a processor corresponding to the configured logical address in preference to the data message in response to the message during transmission.
Preferably, for the FPGA processor, the message sent by the other processor is received through the transceiver IP core, and the bottom layer communication protocol header is removed; the receiving and sending IP core is realized by an Ethernet IP core or a RapidIO IP core;
and aiming at the DSP or the CPU, receiving messages sent by other processors through the plug-in protocol processing chip, and removing the bottom layer communication protocol header.
Preferably, only the input/output module of the processor is assigned with a logic address, one processor comprises or is externally hung with one or more input/output modules, each module is assigned with an address, and the input/output modules are a transceiving IP core and an externally hung protocol processing chip.
Preferably, the waveform components inside the processor are not assigned with logical addresses, the communication among the waveform components inside the processor is directly connected through an interface, and external data is transmitted and received through the input and output module.
Preferably, the waveform component must implement a command processing procedure in addition to its own function, generate a response message corresponding to the command message after the command processing, and return the response message to the sender of the command message.
Compared with the prior art, the invention has the beneficial effects that:
in the prior art, a logical address field is required in the message in order to make the message be forwarded by a correct route. The invention compounds the logic address and the bottom layer communication protocol, carries out network transmission by sharing the address field with the bottom layer communication protocol, does not independently generate the address field in the message field, utilizes the fields of the prior Ethernet and RapidIO protocols, utilizes the exchange mechanism of the bottom layer protocol, does not need to carry out address mapping again in the message forwarding process, can reduce the system delay of the prior method and improve the communication efficiency, has the characteristics of high transmission efficiency and low system complexity, and is suitable for satellite-borne application.
In the traditional method, a port for generating data of each waveform component needs to be connected to ports of other waveform components using data, and the structure has obvious defects in hardware resource occupation and data transmission efficiency and is difficult to adapt to the requirements of a satellite-borne system. The invention promotes the traditional software radio data routing between the wave-shaped component ports to the input and output modules of each processor, avoids the complex interconnection between the components, improves the efficiency of address allocation and the efficiency of data routing, reduces the data sending interaction times, reduces the time delay of data transmission between the components in the processor and also saves the hardware resources in the processor.
The method carries out bottom layer communication of the functional waveforms among the processors through a widely used standard protocol, does not need complex infrastructures such as CORBA and the like, can adapt to different and new processor models, can not consider the specific realization of bottom layer hardware in the realization of the functional waveform assembly, can be suitable for programs of various programming languages, effectively improves the development efficiency of the system waveform assembly, ensures that the functional waveform assembly has expandability, reusability and interoperability, is simple, is convenient for engineering realization, meets the requirement of satellite-borne application, and has strong practicability.
According to the satellite-borne software load software and hardware decoupling method provided by the invention, the communication function of the waveform component and the external processing unit is separated from the signal processing function of the waveform component, the coupling degree of the waveform component and a specific hardware platform is greatly reduced, the system software is decoupled from the hardware, and the function expansion, reconstruction and performance improvement of a satellite load system are flexibly realized by using a software technology, so that a satellite load waveform developer can be liberated from a fussy data exchange process, and only the design of a satellite load waveform processing algorithm needs to be paid attention to, therefore, the development cycle and development cost of a new waveform can be greatly reduced, the reusability and portability of the waveform are enhanced, the time to market of new application is helped to be shortened, and the method has obvious practicability and market competitiveness.
Drawings
FIG. 1 is a diagram of a command message structure;
FIG. 2 is a diagram of a response message structure;
FIG. 3 is a diagram of a data message structure;
FIG. 4 is a block diagram of an implementation of software and hardware decoupling for an FPGA processor.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
Defining a software-based load software and hardware decoupling message structure of satellite borne software, adopting a RapidIO or Ethernet protocol supporting message exchange at the bottom layer, and multiplexing a RapidIO device address or an MAC address of the protocol at the bottom layer by a logic address of a waveform software message receiving and sending.
The message structure comprises a message header, a message ID and bit message content, the message is divided into three types of command message, data message and response message, and the message type is determined by the message header;
the first M bits in the command message are a command message header, the second N bits are a command ID, and the third P bits are command parameters;
the first M bits in the response message are response message heads, the second N bits are response command IDs, and the third P bits are response command parameters;
the first M bits in the data message are data message heads, the second N bits are data packet IDs, the second S bits are data packet numbers, and the subsequent T bits are transmission data;
the command ID in the response message is consistent with the command message to which the response message is to respond;
where M, N, P, S, T are integer multiples of 8, and at the same time M =8, N > = log2 (Q), Q is the number of commands, P > = U, where U is the number of bits with the longest command parameter field in all commands, and S > =32, the value of (T + S + M) being the maximum value that does not exceed the underlying protocol payload length.
The satellite-borne functional software organizes the sending message and analyzes the received message according to the message format, and realizes the communication among the satellite-borne processors by multiplexing a bottom RapidIO or an Ethernet protocol.
The bottom layer multiplexing method comprises the following steps: the logic source address and the logic destination address transmitted by the functional software module multiplex the bottom communication protocol address, if the bottom protocol adopts RapidIO protocol, the device address is used, if the bottom protocol adopts Ethernet protocol, the logic source address transmitted by the message adopts MAC address, the message exchange adopts the bottom exchange device, and the message is forwarded according to the destination address of the message.
The process of organizing the sending message and analyzing the receiving message comprises the following steps:
the FPGA transceiving IP core is found by an Ethernet IP core or a RapidIO IP core and is responsible for receiving various messages and removing a bottom layer communication protocol header, judging the message type according to the header of the message after the bottom layer communication protocol header is removed, analyzing and executing the command according to the command code if the message is the command message, and extracting the data to perform waveform function processing if the message is the data message. And generating a command response message after the command is executed, generating a data message from data generated after the waveform processing, transmitting and receiving the two messages through the FPGA, adding a bottom layer protocol head to an IP core, transmitting the messages through a bottom layer protocol, and distributing the messages to a processor corresponding to an address.
Examples
(1) Defining the message structure:
in this embodiment, the bottom layer adopts an ethernet protocol, and sets M =8, N =8, P =784, S =32, and T =11960 bits.
1) The format of the command message is shown in fig. 1.
The command response message consists of 800 bits. The first 8 bits are always 0xAA, which is the header of the command message. Bits 9 to 16 are the ID of the command. The remaining bits are command parameters defined for each command.
TABLE 1 Command ID and Command parameters
Figure BDA0002184718630000061
Figure BDA0002184718630000071
2) The format of the command response message is shown in fig. 2.
The command response message consists of 800 bits. The first 8 bits are always 0xBB, which is the header of the command response message. Bits 9 to 16 are the ID of the received command. The remaining bits are the response data defined for each command.
Table 2 command response definitions
Description of the invention Wrapping head Command ID Response data
Reset response 0xBB 0x01 0x00 (8230), 0x00 (823000) was not performed at 00, and 01 was performed successfully
Start waveform 0xBB 0x02 0x00 (8230), 00 unexecuted 0x00 (8230), 01 successful execution
Stop waveform 0xBB 0x03 0x00 (8230), 00 unexecuted 0x00 (8230), 01 successful execution
Request status bit 0xBB 0x05 0x00 (8230), 00 unexecuted 0x00 (8230), 01 state indication
State telemetry 0xBB 0x06 0x00 (8230), 00 unexecuted 0x00 (8230), 01 telemetering indication
3) Format of data message
The data message consists of 12000 bits and, as shown in fig. 3, consists of three parts. The first 8 bits are always 0xCC, which is the header of the command response message. Bits 9 to 40 are packet sequence numbers and the count for each packet is incremented by 1 to ensure that no packets are lost. The remaining bits are the actual transmission data.
(2) Message processing procedure
In this embodiment, the FPGA transceiver IP core is found by the ethernet IP core, and is responsible for receiving various messages and removing the bottom layer ethernet communication protocol header, determining the message type according to the header of the message from which the bottom layer communication protocol header is removed, performing command parsing and execution according to the command code if the message is a command message, and extracting data to perform waveform function processing if the message is a data message. Generating command response information after the command is executed, generating data information by data generated after the waveform processing, transmitting and receiving the two information through the FPGA, adding a bottom layer protocol head to an IP core, transmitting the information through a bottom layer protocol, and distributing the information to a processor corresponding to the address.
(3) Satellite-borne software
In the embodiment, the satellite-borne software runs in the FPGA processor, and the module division is as shown in fig. 4. The modules include a receive-transmit IP core module for receiving and parsing data messages and command messages, a receive data processing module, a transmit data processing module, and a waveform implementation module (also referred to as a waveform component).
1) Transmit-receive IP core
The IP core for underlying communication is an ethernet communication IP core in this embodiment.
2) Data receiving and processing module
The data receiving and processing module receives the data and command information without the bottom layer protocol head from the receiving and transmitting IP core and checks whether the data packet is the command or the data information. A corresponding control or data enable signal is created depending on whether the field contained in the header of the message is 0xAA, 0xBB or 0 xCC. The module strips the message header from the message and passes the remaining data to the waveform implementation module.
3) Transmission data processing module
The device is used for creating newly formed data messages processed by the waveform realization module and response messages after commands are executed, adding corresponding message header fields and then sending the message header fields to the receiving and sending IP core.
4) Waveform realization module
The waveform implementation module comprises implementation codes of waveform functions of the waveform implementation module, command analysis and code implementation of command execution. The command parsing code implements parsing of the received command and outputs a command ID and command data from the received command. And the command execution acquires the command ID and the command data from the command analysis code and carries out the command execution to realize the operation corresponding to the command ID. The execution of each command forms a command response packet.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.

Claims (10)

1. A satellite-borne software load software and hardware decoupling method is characterized by being realized in the following way:
defining a message structure, wherein the message structure comprises a message header, a message identifier and bit message content;
configuring satellite-borne software in a processor, and multiplexing a logic address transmitted by a message with a bottom communication protocol address;
the satellite-borne software organizes the sending message and the analyzing receiving message according to the message structure according to the message type, and realizes the communication among the satellite-borne processors through the configured bottom layer communication protocol address; the processor comprises an FPGA processor and/or a DSP and/or a CPU.
2. The method of claim 1, wherein: the message types are divided into three types, namely command messages, data messages and response messages, and the message types are determined by message headers.
3. The method of claim 2, wherein: in the command message, the first M bits are command message heads, the second N bits are command IDs, and the third P bits are command parameters;
the first M bits in the response message are response message heads, the second N bits are response command IDs, and the third P bits are response command parameters;
the first M bits in the data message are data message heads, the second S bits are data packet serial numbers, and the subsequent T bits are transmission data;
the command ID in the response message is consistent with the command message to which the response message is to respond;
where M, N, P, S, T are integer multiples of 8, and N > = log2 (Q) simultaneously, Q is the number of commands, P > = U, where U is the number of bits with the longest command parameter field in all commands, S > =32, and the value of (T + S + M) is the maximum value that does not exceed the underlying protocol payload length.
4. The method of claim 1, wherein: the bottom layer communication protocol address is an address of a multiplexing bottom layer RapidIO or an Ethernet protocol.
5. The method of claim 4, wherein: the configuration is realized by the following modes:
if the bottom protocol adopts RapidIO protocol, the device address is used as the logical address of message transmission; if the bottom layer protocol adopts the Ethernet protocol, the logic address of the message transmission adopts the MAC address, the message exchange adopts the bottom layer switching device, and the message is forwarded according to the destination address of the message.
6. The method of claim 1, wherein: the process of organizing the sending message and analyzing the receiving message comprises the following steps:
receiving messages sent by other processors, and removing a bottom layer communication protocol header;
judging the type of the message according to the message header after removing the bottom layer communication protocol header, if the message is a command message, analyzing and executing the command according to the command code, and if the message is a data message, extracting the data and performing waveform function processing; generating a response message after the command is executed, and generating a data message from data generated after the waveform function processing; and adding a bottom layer communication protocol header to the generated message, transmitting the message through a bottom layer protocol, and distributing the message to a processor corresponding to the configured logical address in preference to the data message in response to the message during transmission.
7. The method of claim 6, wherein: aiming at the FPGA processor, receiving messages sent by other processors through a receiving and sending IP core, and removing a bottom layer communication protocol header; the receiving and sending IP core is realized by an Ethernet IP core or a RapidOIP core;
and aiming at the DSP or the CPU, receiving messages sent by other processors through the plug-in protocol processing chip, and removing the bottom layer communication protocol header.
8. The method of claim 7, wherein: the method only distributes logic addresses to input and output modules of the processor, one processor comprises or is externally hung with one or more input and output modules, each module distributes an address, and the input and output modules are a transceiving IP core and an externally hung protocol processing chip.
9. The method of claim 8, wherein: the waveform components in the processor are not allocated with logic addresses, the communication between the waveform components in the processor is directly connected through an interface, and external data are transmitted and received through the input and output module.
10. The method of claim 3, wherein: the waveform component must implement a command processing process in addition to its own function, generate a response message corresponding to the command message after the command processing, and return the response message to the sender of the command message.
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