CN209514616U - Electronic equipment and its FPGA applied to artificial intelligence - Google Patents
Electronic equipment and its FPGA applied to artificial intelligence Download PDFInfo
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- CN209514616U CN209514616U CN201920389386.8U CN201920389386U CN209514616U CN 209514616 U CN209514616 U CN 209514616U CN 201920389386 U CN201920389386 U CN 201920389386U CN 209514616 U CN209514616 U CN 209514616U
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Abstract
The utility model belongs to electronic technology field, provides a kind of electronic equipment and its FPGA applied to artificial intelligence.In the present invention, by the way that kernel bus and multiple artificial intelligence coprocessors are arranged in FPGA kernel, and multiple ports are provided in kernel bus, a port is connect with system bus, remaining port connects one to one with multiple artificial intelligence coprocessors, so that artificial intelligence coprocessor can be communicated by kernel bus with external equipment, and then realizes artificial intelligence control, not and the problem of not will cause routing congestion and the long line of low speed, to improve the performance of system entirety.
Description
Technical field
The utility model belongs to electronic field more particularly to a kind of electronic equipment and its FPGA applied to artificial intelligence.
Background technique
With the hair at full speed of field programmable gate array (Field-Programmable Gate Array, FPGA) technology
The emergence of exhibition and artificial intelligence, increasingly influences each other, interdependence between the two.Currently, isomery FPGA architecture is
Gradually become the mainstream for supporting artificial intelligence application.Wherein, isomery FPGA connects external equipment and FPGA kernel, with this
The system for supporting flexible artificial intelligence coprocessor is formed, artificial intelligence coprocessor in FPGA by verifying within the system
It is existing, and since traditional FPGA kernel includes Mike, memory and random logic processing module, it can be very good to support
Intelligent algorithm.
Although the connecting line construction of tradition FPGA is but however, existing FPGA kernel can support intelligent algorithm
The interconnection of artificial intelligence coprocessor and system bus is not can guarantee, i.e. the line of tradition FPGA kernel be easy to cause the long line of low speed
With routing congestion, and then the performance of system entirety is dragged down.
Therefore, it is necessary to a kind of technical solution is provided, to solve the above technical problems.
Utility model content
The purpose of this utility model is to provide a kind of electronic equipment and its applied to the FPGA of artificial intelligence, will not make
The problem of at routing congestion and low speed long line, and then improve the performance of system entirety.
The utility model is realized in this way a kind of FPGA applied to artificial intelligence, the FPGA include FPGA kernel,
Be provided with kernel bus and multiple artificial intelligence coprocessors in the FPGA kernel, the artificial intelligence coprocessor be used for into
Row artificial intelligence control is provided with multiple ports in the kernel bus, and a port is connect with system bus, remaining end
Mouth connects one to one with multiple artificial intelligence coprocessors.
The another object of the utility model is to provide a kind of electronic equipment, and the electronic equipment includes above-mentioned being applied to people
The FPGA of work intelligence.
In the present invention, by the way that kernel bus and multiple artificial intelligence coprocessors are arranged in FPGA kernel, and
And multiple ports are provided in kernel bus, a port is connect with system bus, at remaining port and multiple artificial intelligence associations
Reason device connects one to one, so that artificial intelligence coprocessor can be communicated by kernel bus with external equipment, Jin Ershi
Existing artificial intelligence control, and the problem of not will cause routing congestion and the long line of low speed, to improve the performance of system entirety.
Detailed description of the invention
Fig. 1 is a kind of modular structure signal of the FPGA applied to artificial intelligence provided by the utility model embodiment one
Figure；
Fig. 2 is a kind of modular structure signal of the FPGA applied to artificial intelligence provided by the utility model embodiment two
Figure；
Fig. 3 is a kind of modular structure signal of the FPGA applied to artificial intelligence provided by the utility model embodiment three
Figure；
Fig. 4 is a kind of modular structure signal of the FPGA applied to artificial intelligence provided by the utility model embodiment four
Figure；
Fig. 5 is the kernel bus in a kind of FPGA applied to artificial intelligence provided by the utility model embodiment five
Structural schematic diagram.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.
The realization of the utility model is described in detail below in conjunction with specific attached drawing:
Fig. 1 shows the modular structure provided by the utility model embodiment one applied to the FPGA of artificial intelligence, is
Convenient for explanation, only the parts related to this embodiment are shown, details are as follows:
As shown in Figure 1, the FPGA1 provided by the embodiment of the utility model applied to artificial intelligence includes FPGA kernel 13,
Kernel bus 131 and multiple artificial intelligence coprocessors 130 are provided in the FPGA kernel 13.Wherein, at the artificial intelligence association
Reason device 130 is provided with multiple ports 1311, and a port for carrying out artificial intelligence control in the kernel bus 131
1311 connect with system bus 14, remaining port 311 connects one to one with multiple artificial intelligence coprocessors 130；It needs
It is bright, in the utility model embodiment, in addition to being provided with artificial intelligence coprocessor 130 in the FPGA kernel 13 of FPGA1
Outside kernel bus 131, which, which further includes but be not limited to Mike, memory, user logic, etc. can support this
FPGA1 completes the equipment or circuit of intelligent algorithm control, and patrols in FPGA kernel 13 including Mike, memory, user
The connection relationship and working principle collected can refer to the prior art, and details are not described herein again.
When specific works, the artificial intelligence coprocessor 130 in the FPGA kernel 13 of FPGA1 passes through in kernel bus 131
Port 1311 communicated with system bus 14, can be by interior so that when the FPGA1 works in artificial intelligence situation
The equipment accessed in core bus 131 and system bus 14 communicates, and then passes through the artificial intelligence in the kernel 13 in equipment and FPGA1
Energy coprocessor 130 completes specific artificial intelligence scenery control and interaction jointly；It should be noted that in the utility model reality
It applies in example, artificial intelligence scene can according to need the application scenarios for being set as different, be not particularly limited herein.
Further, in the utility model embodiment, the equipment accessed on system bus 14 includes but is not limited to communicate
The equipment such as interface, memory, processor, such as the utility model high-speed interface 10 shown in Fig. 2, global memory 11 and center
Processor 12 etc..Wherein, high-speed interface 10 and global memory 11 and central processing unit 12 are all connected on system bus 14；It is high
Quick access mouth 10 is used for external equipment (not shown)；Global memory 11 is used to provide memory space for FPGA1；Central processing unit
12 for carrying out whole control to the modules in FPGA1.
Further, when it is implemented, since the FPGA1 of FPGA artificial intelligence provided by the embodiment of the utility model is main
Global memory 11 applied to artificial intelligence, therefore in the FPGA1 of the utility model embodiment can be in the course of work of the FPGA1
In, the data exchange process in terms of artificial intelligence is stored, which can be used various memories and realize, herein
It is not particularly limited；In addition, high-speed interface 10 can external various equipment, the including but not limited to electronic equipments such as remote controler, and
The interface type of the height interface 10 is simultaneously not particularly limited, and central processing unit 12 is mainly used for artificial intelligence in the FPGA1
When, the various data interactions in the artificial intelligence system 1 formed based on the FPGA1 are controlled accordingly according to specific scene
System.
In the utility model embodiment, the FPGA1 provided by the utility model applied to artificial intelligence passes through in FPGA
Kernel bus 131 is set inside kernel 13, and the kernel bus 131 is connect with system bus 14, so that this is also applied to people
The FPGA1 of work intelligence effectively shortens the distance between artificial intelligence coprocessor 130 and system bus 14, and is not routed
The drawbacks of congestion, eliminates in the prior art because of systematic entirety can be low caused by routing congestion and the long line of low speed drawback.
Further, as shown in Figure 1, since the kernel bus 131 in FPGA kernel 13 is the extension of system bus 14, because
This, internal structure is consistent with system bus 14, and its artificial intelligence coprocessor 130 connected need to abide by system
14 agreement of bus, it is therefore, provided by the embodiment of the utility model to be applied to artificial intelligence to guarantee the normal work of whole system
FPGA1 can guarantee kernel bus 131 multiport bus timing.
Further, referring to FIG. 5, it is as shown in figure 5, provided by the embodiment of the utility model applied to artificial intelligence
The specific structure of kernel bus 131 in FPGA1 is made of more parallel Hard link lines 1312, this more parallel Hard link lines
Port 1311 is provided on 1312, and the port 1311 is drawn by way of parallel Hard link line 1312.
Wherein, in the utility model embodiment, when it is implemented, the kernel bus 131 in FPGA kernel 13 is by more
The parallel hardwired of 32-bit or 64-bit forms；In addition, the kernel in FPGA kernel 13 in the utility model embodiment is total
Each port 1311 on line 131 is tri-state port, i.e., each port 1311 in the kernel bus 131 in FPGA kernel 13 can
State is read to work in data, also may operate in data write state, can more be worked in bus driver state, and every
Each of a port 1311 can dynamically change at runtime driving direction and kernel bus 131 each to
Timing, which is carved, can only a driver.
Further, as one preferred embodiment of the utility model, as shown in Figure 1, the utility model embodiment is mentioned
The kernel bus 131 of the FPGA kernel 13 in the FPGA1 applied to artificial intelligence supplied is in T shape to be arranged in FPGA kernel 13
In, and the multiple ports 1311 (being illustrated for four in figure) being arranged in kernel bus 131 are evenly distributed on T-shaped two
End.
Wherein, in the utility model embodiment, since there are three ends for T-shaped tool, in the utility model embodiment
The multiple ports 1311 being arranged in the kernel bus 131 are evenly distributed on T-shaped both ends and refer to: when the T-shaped kernel
There are four when port 1311, being then respectively set at the both ends of the T-shaped kernel bus 131, there are two ports for setting in bus 131
1311；It should be noted that being only illustrated for four in the utility model embodiment, not to T-shaped kernel bus
Port number on 131 carries out concrete restriction, in addition, the other end of T-shaped kernel bus 131 is connect with system bus 14.
Further, as one preferred embodiment of the utility model, as shown in figure 3, the utility model embodiment is mentioned
The kernel bus 131 of the FPGA kernel 13 in the FPGA1 applied to artificial intelligence supplied is arranged in cross in FPGA kernel 13
In, and the multiple ports 1311 (being illustrated for six in figure) being arranged in kernel bus 131 are evenly distributed on cross
Both ends.
Wherein, in the utility model embodiment, since there are four ends for cross tool, in the utility model embodiment
The multiple ports 1311 being arranged in the kernel bus 131 are evenly distributed on three end of cross and refer to: when in the cross
There are six when port 1311, being then respectively set at three ends of the cross kernel bus 131, there are two ends for setting in core bus 131
Mouth 1311；It should be noted that be only illustrated for six in the utility model embodiment, it is not total to cross kernel
Port number on line 131 carries out concrete restriction, in addition, the other end of cross kernel bus 131 and system bus 14 connect
It connects.
Further, as one preferred embodiment of the utility model, as shown in figure 4, the utility model embodiment is mentioned
The kernel bus 131 of the FPGA kernel 13 in the FPGA1 applied to artificial intelligence supplied is arranged in a ring in FPGA kernel 13,
And the multiple ports 1311 (being illustrated for four in figure) being arranged in kernel bus 131 are evenly distributed on the annular kernel
In bus 131.
In the utility model embodiment, by by provided by the embodiment of the utility model applied to artificial intelligence
The kernel bus 131 in FPGA kernel 13 in FPGA1 is arranged to different topological structures, such as T-shaped kernel bus, cross
Shape kernel bus and annular kernel bus, so that the distance of kernel bus 131 to artificial intelligence coprocessor 130 effectively subtracts
It is small, and then generation the problem of avoid degraded performance caused by the long line of low speed.
Further, as one preferred embodiment of the utility model, it is applied to provided by the utility model embodiment
The port number 1311 being arranged in the kernel bus 131 being arranged in FPGA kernel 13 in the FPGA1 of artificial intelligence is excellent greater than 2
The number for the port number 1311 being arranged in the kernel bus 131 of choosing is not less than the number of artificial intelligence coprocessor 130, i.e.,
The port number 1311 being arranged in kernel bus 131 is more than or equal to the number of artificial intelligence coprocessor 130, can basis
The demand of artificial intelligence application is different and different.
In the utility model embodiment, the FPGA1 provided by the embodiment of the utility model applied to artificial intelligence passes through
Multiple ports 1311 are set in the kernel bus 131 inside its FPGA kernel 13, so that should be applied to the FPGA1 of artificial intelligence
It can be applied to different artificial intelligence scenes, improve the applicability of the FPGA1 for being applied to artificial intelligence, while will not send out
The problem of raw routing congestion.
Further, the utility model additionally provides a kind of electronic equipment, which includes being applied to artificial intelligence
FPGA1.It should be noted that as provided by the utility model embodiment extremely applied to the FPGA1 and Fig. 1 of artificial intelligence
Fig. 5 the FPGA1 applied to artificial intelligence it is identical, therefore, answering in electronic equipment provided by the utility model embodiment
The concrete operating principle of FPGA1 for artificial intelligence can refer to the detailed description previously with regard to Fig. 1 to Fig. 5, no longer superfluous herein
It states.
In the present invention, by the way that kernel bus and multiple artificial intelligence coprocessors are arranged in FPGA kernel, and
And multiple ports are provided in kernel bus, a port is connect with system bus, at remaining port and multiple artificial intelligence associations
Reason device connects one to one, so that artificial intelligence coprocessor can be communicated by kernel bus with external equipment, Jin Ershi
Existing artificial intelligence control, and the problem of not will cause routing congestion and the long line of low speed, to improve the performance of system entirety.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
Made any modifications, equivalent replacements, and improvements etc., should be included in the utility model within the spirit and principle of utility model
Protection scope within.
Claims (10)
1. a kind of FPGA applied to artificial intelligence, which is characterized in that the FPGA includes FPGA kernel, in the FPGA kernel
It is provided with kernel bus and multiple artificial intelligence coprocessors, the artificial intelligence coprocessor is for carrying out artificial intelligence control
System is provided with multiple ports in the kernel bus, and a port is connect with system bus, remaining port with it is multiple described
Artificial intelligence coprocessor connects one to one.
2. FPGA according to claim 1, which is characterized in that the kernel bus is made of more parallel Hard link lines.
3. FPGA according to claim 2, which is characterized in that the port number in the kernel bus is greater than 2.
4. FPGA according to claim 3, which is characterized in that the port number being arranged in the kernel bus is not less than institute
State the number of artificial intelligence coprocessor.
5. FPGA according to any one of claims 1 to 4, which is characterized in that the port in the kernel bus is tri-state
Port.
6. FPGA according to claim 5, which is characterized in that the tri-state in tri-state port in the kernel bus includes
Data read states, data write state and bus driver state.
7. FPGA according to any one of claims 1 to 4, which is characterized in that the kernel bus is arranged in cross
In the FPGA kernel, and one end of cross kernel bus is connect with the system bus, the cross kernel bus
Its excess-three end is distributed multiple ports.
8. FPGA according to any one of claims 1 to 4, which is characterized in that the kernel bus is in T shape to be arranged in institute
The multiple ports stated in FPGA kernel, and be arranged in the kernel bus are evenly distributed on the T-shaped both ends.
9. FPGA according to any one of claims 1 to 4, which is characterized in that institute is arranged in the kernel bus in a ring
It states in FPGA kernel.
10. a kind of electronic equipment, which is characterized in that the electronic equipment includes application as described in any one of claim 1 to 9
In the FPGA of artificial intelligence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920389386.8U CN209514616U (en) | 2019-03-26 | 2019-03-26 | Electronic equipment and its FPGA applied to artificial intelligence |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920389386.8U CN209514616U (en) | 2019-03-26 | 2019-03-26 | Electronic equipment and its FPGA applied to artificial intelligence |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109871353A (en) * | 2019-03-26 | 2019-06-11 | 广东高云半导体科技股份有限公司 | Electronic equipment and its FPGA applied to artificial intelligence |
| US20210081770A1 (en) * | 2019-09-17 | 2021-03-18 | GOWN Semiconductor Corporation | System architecture based on soc fpga for edge artificial intelligence computing |
-
2019
- 2019-03-26 CN CN201920389386.8U patent/CN209514616U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109871353A (en) * | 2019-03-26 | 2019-06-11 | 广东高云半导体科技股份有限公司 | Electronic equipment and its FPGA applied to artificial intelligence |
| US20210081770A1 (en) * | 2019-09-17 | 2021-03-18 | GOWN Semiconductor Corporation | System architecture based on soc fpga for edge artificial intelligence computing |
| US11544544B2 (en) * | 2019-09-17 | 2023-01-03 | Gowin Semiconductor Corporation | System architecture based on SoC FPGA for edge artificial intelligence computing |
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