CN109871353A - Electronic equipment and its FPGA applied to artificial intelligence - Google Patents
Electronic equipment and its FPGA applied to artificial intelligence Download PDFInfo
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- CN109871353A CN109871353A CN201910230300.1A CN201910230300A CN109871353A CN 109871353 A CN109871353 A CN 109871353A CN 201910230300 A CN201910230300 A CN 201910230300A CN 109871353 A CN109871353 A CN 109871353A
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Abstract
The invention belongs to electronic technology fields, provide a kind of electronic equipment and its FPGA applied to artificial intelligence.In the present invention, by the way that kernel bus and multiple artificial intelligence coprocessors are arranged in FPGA kernel, and multiple ports are provided in kernel bus, a port is connect with system bus, remaining port connects one to one with multiple artificial intelligence coprocessors, so that artificial intelligence coprocessor can be communicated by kernel bus with external equipment, and then realizes artificial intelligence control, not and the problem of not will cause routing congestion and the long line of low speed, to improve the performance of system entirety.
Description
Technical field
The invention belongs to electronic field more particularly to a kind of electronic equipment and its applied to the FPGA of artificial intelligence.
Background technique
With the hair at full speed of field programmable gate array (Field-Programmable Gate Array, FPGA) technology
The emergence of exhibition and artificial intelligence, increasingly influences each other, interdependence between the two.Currently, isomery FPGA architecture is
Gradually become the mainstream for supporting artificial intelligence application.Wherein, isomery FPGA connects external equipment and FPGA kernel, with this
The system for supporting flexible artificial intelligence coprocessor is formed, artificial intelligence coprocessor in FPGA by verifying within the system
It is existing, and since traditional FPGA kernel includes Mike, memory and random logic processing module, it can be very good to support
Intelligent algorithm.
Although the connecting line construction of tradition FPGA is but however, existing FPGA kernel can support intelligent algorithm
The interconnection of artificial intelligence coprocessor and system bus is not can guarantee, i.e. the line of tradition FPGA kernel be easy to cause the long line of low speed
With routing congestion, and then the performance of system entirety is dragged down.
Therefore, it is necessary to a kind of technical solution is provided, to solve the above technical problems.
Summary of the invention
The purpose of the present invention is to provide a kind of electronic equipment and its applied to the FPGA of artificial intelligence, cloth not will cause
The problem of line congestion and low speed long line, and then improve the performance of system entirety.
The invention is realized in this way a kind of FPGA applied to artificial intelligence, the FPGA include FPGA kernel, it is described
Kernel bus and multiple artificial intelligence coprocessors are provided in FPGA kernel, the artificial intelligence coprocessor is for carrying out people
Work intelligent control is provided with multiple ports in the kernel bus, and a port is connect with system bus, remaining port with
Multiple artificial intelligence coprocessors connect one to one.
Another object of the present invention is to provide a kind of electronic equipment, the electronic equipment includes above-mentioned applied to artificial intelligence
The FPGA of energy.
In the present invention, by the way that kernel bus and multiple artificial intelligence coprocessors are arranged in FPGA kernel, and it is interior
Multiple ports are provided in core bus, a port is connect with system bus, remaining port and multiple artificial intelligence coprocessors
It connects one to one, so that artificial intelligence coprocessor can be communicated by kernel bus with external equipment, and then realizes people
Work intelligent control, and the problem of not will cause routing congestion and the long line of low speed, to improve the performance of system entirety.
Detailed description of the invention
Fig. 1 is a kind of modular structure schematic diagram of the FPGA applied to artificial intelligence provided by the embodiment of the present invention one；
Fig. 2 is a kind of modular structure schematic diagram of the FPGA applied to artificial intelligence provided by the embodiment of the present invention two；
Fig. 3 is a kind of modular structure schematic diagram of the FPGA applied to artificial intelligence provided by the embodiment of the present invention three；
Fig. 4 is a kind of modular structure schematic diagram of the FPGA applied to artificial intelligence provided by the embodiment of the present invention four；
Fig. 5 is the structure of the kernel bus in a kind of FPGA applied to artificial intelligence provided by the embodiment of the present invention five
Schematic diagram.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Realization of the invention is described in detail below in conjunction with specific attached drawing:
Fig. 1 shows the modular structure provided by the embodiment of the present invention one applied to the FPGA of artificial intelligence, in order to just
In explanation, only the parts related to this embodiment are shown, and details are as follows:
As shown in Figure 1, the FPGA1 provided in an embodiment of the present invention applied to artificial intelligence includes FPGA kernel 13, it should
Kernel bus 131 and multiple artificial intelligence coprocessors 130 are provided in FPGA kernel 13.Wherein, which is handled
Device 130 is provided with multiple ports 1311, and a port 1311 for carrying out artificial intelligence control in the kernel bus 131
It is connect with system bus 14, remaining port 311 connects one to one with multiple artificial intelligence coprocessors 130；It needs to illustrate
It is, it is in embodiments of the present invention, total in addition to being provided with artificial intelligence coprocessor 130 and kernel in the FPGA kernel 13 of FPGA1
Outside line 131, which, which further includes but be not limited to Mike, memory, user logic, etc. can support the FPGA1 to complete people
The equipment or circuit of work intelligent algorithm control, and include the connection relationship of Mike, memory, user logic in FPGA kernel 13
It can refer to the prior art with working principle, details are not described herein again.
When specific works, the artificial intelligence coprocessor 130 in the FPGA kernel 13 of FPGA1 passes through in kernel bus 131
Port 1311 communicated with system bus 14, can be by interior so that when the FPGA1 works in artificial intelligence situation
The equipment accessed in core bus 131 and system bus 14 communicates, and then passes through the artificial intelligence in the kernel 13 in equipment and FPGA1
Energy coprocessor 130 completes specific artificial intelligence scenery control and interaction jointly；It should be noted that in the embodiment of the present invention
In, artificial intelligence scene can according to need the application scenarios for being set as different, be not particularly limited herein.
Further, in embodiments of the present invention, the equipment accessed on system bus 14 include but is not limited to communication interface,
The equipment such as memory, processor, such as high-speed interface shown in Fig. 2 10 of the invention, global memory 11 and central processing unit 12
Deng.Wherein, high-speed interface 10 and global memory 11 and central processing unit 12 are all connected on system bus 14；High-speed interface 10
For external equipment (not shown)；Global memory 11 is used to provide memory space for FPGA1；Central processing unit 12 for pair
Modules in FPGA1 carry out whole control.
Further, when it is implemented, since the FPGA1 of FPGA artificial intelligence provided in an embodiment of the present invention is mainly applied
Global memory 11 in artificial intelligence, therefore in the FPGA1 of the embodiment of the present invention can be in the course of work of the FPGA1, by people
The data exchange process of work intelligence aspect is stored, which can be used various memories and realize, does not do and has herein
Body limitation；In addition, high-speed interface 10 can external various equipment, the including but not limited to electronic equipments such as remote controler, and this height
The interface type of interface 10 is simultaneously not particularly limited, and central processing unit 12 mainly the FPGA1 be used for artificial intelligence when, to base
Various data interactions in the artificial intelligence system 1 that the FPGA1 is formed are controlled accordingly according to specific scene.
In embodiments of the present invention, the FPGA1 provided by the invention applied to artificial intelligence passes through in FPGA kernel 13
Kernel bus 131 is arranged in portion, and the kernel bus 131 is connect with system bus 14, so that this is also applied to artificial intelligence
FPGA1 effectively shortens the distance between artificial intelligence coprocessor 130 and system bus 14, and the not disadvantage of routing congestion
End eliminates in the prior art because of systematic entirety can be low caused by routing congestion and the long line of low speed drawback.
Further, as shown in Figure 1, since the kernel bus 131 in FPGA kernel 13 is the extension of system bus 14, because
This, internal structure is consistent with system bus 14, and its artificial intelligence coprocessor 130 connected need to abide by system
14 agreement of bus, it is therefore, provided in an embodiment of the present invention applied to artificial intelligence to guarantee the normal work of whole system
FPGA1 can guarantee the timing of the multiport bus of kernel bus 131.
Further, referring to FIG. 5, as shown in figure 5, the FPGA1 provided in an embodiment of the present invention applied to artificial intelligence
In the specific structure of kernel bus 131 be made of more parallel Hard link lines 1312, on this more parallel Hard link lines 1312
It is provided with port 1311, and the port 1311 is drawn by way of parallel Hard link line 1312.
Wherein, in embodiments of the present invention, when it is implemented, the kernel bus 131 in FPGA kernel 13 is by more 32-
The parallel hardwired of bit or 64-bit forms；In addition, in kernel bus 131 in FPGA kernel 13 in the embodiment of the present invention
Each port 1311 be tri-state port, i.e. each port 1311 in kernel bus 131 in FPGA kernel 13 can work
State is read in data, also may operate in data write state, can more be worked in bus driver state, and each port
Each of 1311 can dynamically change at runtime driving direction and kernel bus 131 each in given time
There can only be a driver.
Further, as a preferred embodiment of the invention, as shown in Figure 1, application provided by the embodiment of the present invention
The kernel bus 131 of FPGA kernel 13 in the FPGA1 of artificial intelligence is in T shape to be arranged in FPGA kernel 13, and kernel
The multiple ports 1311 (being illustrated for four in figure) being arranged in bus 131 are evenly distributed on T-shaped both ends.
Wherein, in embodiments of the present invention, interior described in the embodiment of the present invention since T-shaped tool is there are three end
The multiple ports 1311 being arranged in core bus 131 are evenly distributed on T-shaped both ends and refer to: when in the T-shaped kernel bus 131
There are four when port 1311, being then respectively set at the both ends of the T-shaped kernel bus 131, there are two ports 1311 for setting；It needs
Illustrate, be only illustrated for four in the embodiment of the present invention, not to the port number in T-shaped kernel bus 131
Amount carries out concrete restriction, in addition, the other end of T-shaped kernel bus 131 is connect with system bus 14.
Further, as a preferred embodiment of the invention, as shown in figure 3, application provided by the embodiment of the present invention
The kernel bus 131 of FPGA kernel 13 in the FPGA1 of artificial intelligence is arranged in FPGA kernel 13 in cross, and kernel
The multiple ports 1311 (being illustrated for six in figure) being arranged in bus 131 are evenly distributed on cross both ends.
Wherein, in embodiments of the present invention, interior described in the embodiment of the present invention since cross tool is there are four end
The multiple ports 1311 being arranged in core bus 131 are evenly distributed on three end of cross and refer to: when the cross kernel bus 131
There are six when port 1311, being then respectively set at three ends of the cross kernel bus 131, there are two ports 1311 for upper setting；It needs
It is noted that being only illustrated for six in the embodiment of the present invention, not to the port in cross kernel bus 131
Quantity carries out concrete restriction, in addition, the other end of cross kernel bus 131 is connect with system bus 14.
Further, as a preferred embodiment of the invention, as shown in figure 4, application provided by the embodiment of the present invention
The kernel bus 131 of FPGA kernel 13 in the FPGA1 of artificial intelligence is arranged in a ring in FPGA kernel 13, and kernel is total
The multiple ports 1311 (being illustrated for four in figure) being arranged on line 131 are evenly distributed on the annular kernel bus 131
On.
In embodiments of the present invention, by will be in the FPGA1 provided in an embodiment of the present invention applied to artificial intelligence
Kernel bus 131 in FPGA kernel 13 is arranged to different topological structures, such as T-shaped kernel bus, cross kernel are total
Line and annular kernel bus, so that the distance of kernel bus 131 to artificial intelligence coprocessor 130 effectively reduces, and then keep away
The problem of having exempted from degraded performance caused by the long line of low speed generation.
Further, as a preferred embodiment of the invention, the embodiment of the present invention is provided to be applied to artificial intelligence
FPGA1 in FPGA kernel 13 in the kernel bus 131 that is arranged the port number 1311 that is arranged be greater than 2, it is preferred that this is interior
The number for the port number 1311 being arranged in core bus 131 is not less than the number of artificial intelligence coprocessor 130, i.e. kernel bus
The port number 1311 being arranged on 131 is more than or equal to the number of artificial intelligence coprocessor 130, can be according to artificial intelligence
The demand of application is different and different.
In embodiments of the present invention, the FPGA1 provided in an embodiment of the present invention applied to artificial intelligence passes through in its FPGA
Multiple ports 1311 are set in the kernel bus 131 inside kernel 13, which is applied
In different artificial intelligence scenes, the applicability of the FPGA1 for being applied to artificial intelligence is improved, while wiring will not occur and gather around
The problem of plug.
Further, the present invention also provides a kind of electronic equipment, which includes being applied to artificial intelligence
FPGA1.It should be noted that by FPGA1 and Fig. 1 to Fig. 5 institute for being applied to artificial intelligence provided by the embodiment of the present invention
The FPGA1 applied to artificial intelligence it is identical, therefore, in electronic equipment provided by the embodiment of the present invention be applied to artificial intelligence
The concrete operating principle of the FPGA1 of energy, can refer to the detailed description previously with regard to Fig. 1 to Fig. 5, details are not described herein again.
In the present invention, by the way that kernel bus and multiple artificial intelligence coprocessors are arranged in FPGA kernel, and it is interior
Multiple ports are provided in core bus, a port is connect with system bus, remaining port and multiple artificial intelligence coprocessors
It connects one to one, so that artificial intelligence coprocessor can be communicated by kernel bus with external equipment, and then realizes people
Work intelligent control, and the problem of not will cause routing congestion and the long line of low speed, to improve the performance of system entirety.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (10)
1. a kind of FPGA applied to artificial intelligence, which is characterized in that the FPGA includes FPGA kernel, in the FPGA kernel
It is provided with kernel bus and multiple artificial intelligence coprocessors, the artificial intelligence coprocessor is for carrying out artificial intelligence control
System is provided with multiple ports in the kernel bus, and a port is connect with system bus, remaining port with it is multiple described
Artificial intelligence coprocessor connects one to one.
2. FPGA according to claim 1, which is characterized in that the kernel bus is made of more parallel Hard link lines.
3. FPGA according to claim 2, which is characterized in that the port number in the kernel bus is greater than 2.
4. FPGA according to claim 3, which is characterized in that the port number being arranged in the kernel bus is not less than institute
State the number of artificial intelligence coprocessor.
5. FPGA according to any one of claims 1 to 4, which is characterized in that the port in the kernel bus is tri-state
Port.
6. FPGA according to claim 5, which is characterized in that the tri-state in tri-state port in the kernel bus includes
Data read states, data write state and bus driver state.
7. FPGA according to any one of claims 1 to 4, which is characterized in that the kernel bus is arranged in cross
In the FPGA kernel, and one end of cross kernel bus is connect with the system bus, the cross kernel bus
Its excess-three end is distributed multiple ports.
8. FPGA according to any one of claims 1 to 4, which is characterized in that the kernel bus is in T shape to be arranged in institute
The multiple ports stated in FPGA kernel, and be arranged in the kernel bus are evenly distributed on the T-shaped both ends.
9. FPGA according to any one of claims 1 to 4, which is characterized in that institute is arranged in the kernel bus in a ring
It states in FPGA kernel.
10. a kind of electronic equipment, which is characterized in that the electronic equipment includes application as described in any one of claim 1 to 9
In the FPGA of artificial intelligence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910230300.1A CN109871353A (en) | 2019-03-26 | 2019-03-26 | Electronic equipment and its FPGA applied to artificial intelligence |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910230300.1A CN109871353A (en) | 2019-03-26 | 2019-03-26 | Electronic equipment and its FPGA applied to artificial intelligence |
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| CN201910230300.1A Pending CN109871353A (en) | 2019-03-26 | 2019-03-26 | Electronic equipment and its FPGA applied to artificial intelligence |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210081770A1 (en) * | 2019-09-17 | 2021-03-18 | GOWN Semiconductor Corporation | System architecture based on soc fpga for edge artificial intelligence computing |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210081770A1 (en) * | 2019-09-17 | 2021-03-18 | GOWN Semiconductor Corporation | System architecture based on soc fpga for edge artificial intelligence computing |
| US11544544B2 (en) * | 2019-09-17 | 2023-01-03 | Gowin Semiconductor Corporation | System architecture based on SoC FPGA for edge artificial intelligence computing |
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