CN104698941A - FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system - Google Patents
FPGA-based (field programmable gate array-based) embedded dual-core relay protecting system Download PDFInfo
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- CN104698941A CN104698941A CN201510107412.XA CN201510107412A CN104698941A CN 104698941 A CN104698941 A CN 104698941A CN 201510107412 A CN201510107412 A CN 201510107412A CN 104698941 A CN104698941 A CN 104698941A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02B90/20—Smart grids as enabling technology in buildings sector
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
Abstract
The invention provides an FPGA-based embedded dual-core relay protecting system. The FPGA-based embedded dual-core relay protecting system comprises a first NIOS II soft-core processor, a second NIOS II soft-core processor, an Avalon bus module and a mailbox module. The mailbox module is connected with the first NIOS II soft-core processor, the second NIOS II soft-core processor and the Avalon bus module. The FPGA-based embedded dual-core relay protecting system integrates the digital system onto one chip and accordingly is high in function density, small in size, low in power consumption and high in reliability; compared with a special ASIC (application specific integrated circuit), FPGA is low in cost and flexible in design and is the development tendency of integrated circuit design of future microcomputer relay protecting products; the FPGA-based embedded dual-core relay protecting system comprises data collection, logic processing and a variety of peripheral systems and can meet the requirements of hardware interfaces on diversification and customization.
Description
Technical field
The present invention relates to mesolow microcomputer protective relay technical field, particularly relate to a kind of embedded dual core relay protection system based on FPGA.
Background technology
In current electric system mesolow automatic device product Platform Designing, the product of 90% uses the special asic chip such as single-chip microcomputer, ARM or DSP, relatively large peripheral circuit is employed during product platform design, and due to the line time delay in PCB plate between IC chip, and the restriction of the factor such as volume and weight of itself, the performance of machine system receives very large restriction, the product MTBF(mean free error time) numerical value is lower.Along with the continuous proposition of complicated algorithm various in electric system and development and mechanics of communication new development, challenge is proposed to the performance of conventional dedicated asic chip processor, simple dependence improves clock frequency, the indexs such as data throughout can not well satisfy the demands, and these special asic chips due to hardware resource mouth less, cannot realize or can only be simulated by GPIO or extend out CPU and respond new demand change, this makes system designer mostly can take into account the structure of plate level multiprocessor, as MCU-CPLD combination, MCU-DSP-CPLD combination and FPGA-DSP combination, although these assembled schemes meet demand, also bring design complicated simultaneously, design cycle is long, scaling difficulty, more high deficiency is required to developer.
Along with integrated circuit development, SOPC technology has become the developing direction of future semiconductor industry, and its technical implementation way has three kinds: (1) is based on the SOPC system of HardCopy technology; (2) embed stone IP(Intellectural Property based on FPGA) SOPC system; (3) the SOPC system of soft core IP is embedded based on FPGA.Wherein: the SOPC system based on HardCopy technology only uses in product volume production and when shaping, and the SOPC system utilizing embedded stone to realize remains in some defects: cost is higher; Structure, function are fixed, more difficult in same a slice FPGA integrated multiple processor, and for microcomputer protective relay and automatic device product, its data acquisition computing and relay protective scheme realize still more difficult purely with hardware based FPGA.
Summary of the invention
The technical problem to be solved in the present invention is: for current existing mesolow microcomputer protective relay and automation equipment product platform device is many, integrated level is not high, cannot flexible adaptation new demand and customized demand, use the problem such as chip stopping production risk, the invention provides a kind of embedded dual core relay protection system based on FPGA and solve the problems referred to above.
The technical solution adopted for the present invention to solve the technical problems is: a kind of embedded dual core relay protection system based on FPGA, comprise NIOS II soft-core processor, 2nd NIOS II soft-core processor, Avalon bus module and mailbox module, described mailbox model calling to be connected with the 2nd NIOS II soft-core processor at described NIOS II soft-core processor and to be connected with described Avalon bus module, described Avalon bus module connection is also connected with acquisition module, control module, human-computer interaction module and communication module, described NIOS II soft-core processor is for the data that obtain acquisition module and collect and carry out relay protection logic process, then result is fed back to described control module, described 2nd NIOS II soft-core processor is responsible for the external communication of communication module and human-computer interaction module.
As preferably, described acquisition module comprises the ADC converter for gathering analog quantity and opens inbound port, described ADC converter with open the tri-state bridge interface of inbound port by PIO kernel and be connected with described Avalon bus module, described tri-state bridge interface is also connected with SRAM.
Concrete, described control module comprises outputs port and LED, and described Avalon bus module outputs port by the universaling I/O port of PIO kernel with described and LED is connected.
As preferably, described communication module comprises debug port, two external PORT COM, PORT COM for subsequent use and two ethernet controllers, described debug port, two external PORT COM are all connected with described Avalon bus module by UART kernel with PORT COM for subsequent use, described two ethernet controllers are connected with described Avalon bus module respectively by an ethernet controller interface, described NIOS II soft-core processor carries out internal debugging by debug port, described 2nd NIOS II soft-core processor is responsible for the external communication of two external PORT COM and individual ethernet controller and is carried out communication or externally communication between plate by PORT COM for subsequent use.
As preferably, described human-computer interaction module comprises charactron, LCD display and button, and described Avalon bus module is connected with described charactron, LCD display and button by the universaling I/O port of PIO kernel.
Concrete, also comprise SDRAM, EPCS64 configurator, RTC and EEPROM, described SDRAM is connected with described Avalon bus module by sdram controller, described EPCS64 configurator is connected with described Avalon bus module by EPCS controller, and described RTC with EEPROM is connected with described Avalon bus module by I2C controller.
As preferably, described NIOS II soft-core processor is connected with the reset pin of described NIOS II soft-core processor by PIO kernel.
The invention has the beneficial effects as follows; this embedded dual core relay protection system based on FPGA is on a single die integrated for whole digital display circuit; functional density is high, volume is little, low in energy consumption, reliability is high; and compare with special ASIC; FPGA is with low cost, flexible design; be the development trend of following microcomputer protective relay product integrated circuit (IC) design, it contains data acquisition, logical process and a lot of peripheral system, can meet hardware interface variation and customization demand.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is the structural representation of the optimum embodiment of the embedded dual core relay protection system based on FPGA of the present invention.
Fig. 2 is the software architecture figure of the embedded dual core relay protection system based on FPGA of the present invention.
Fig. 3 is the double-core mailbox Principle of Communication figure of the embedded dual core relay protection system based on FPGA of the present invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.On the contrary, embodiments of the invention comprise fall into attached claims spirit and intension within the scope of all changes, amendment and equivalent.
In describing the invention, it is to be appreciated that term " first ", " second " etc. are only for describing object, and instruction or hint relative importance can not be interpreted as.In describing the invention, it should be noted that, unless otherwise clearly defined and limited, term " is connected ", " connection " should be interpreted broadly, such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary.For the ordinary skill in the art, concrete condition above-mentioned term concrete meaning in the present invention can be understood.In addition, in describing the invention, except as otherwise noted, the implication of " multiple " is two or more.
Describe and can be understood in process flow diagram or in this any process otherwise described or method, represent and comprise one or more for realizing the module of the code of the executable instruction of the step of specific logical function or process, fragment or part, and the scope of the preferred embodiment of the present invention comprises other realization, wherein can not according to order that is shown or that discuss, comprise according to involved function by the mode while of basic or by contrary order, carry out n-back test, this should understand by embodiments of the invention person of ordinary skill in the field.
As shown in Figure 1, the invention provides a kind of embedded dual core relay protection system based on FPGA, comprise NIOS II soft-core processor, 2nd NIOS II soft-core processor, Avalon bus module and mailbox module, mailbox model calling is connected at NIOS II soft-core processor with the 2nd NIOS II soft-core processor and is connected with Avalon bus module, one NIOS II soft-core processor is connected with the reset pin of NIOS II soft-core processor by PIO kernel, after NIOS II soft-core processor starts, the 2nd NIOS II soft-core processor is started by a NIOS II soft-core processor controllable type, , the connection of Avalon bus module is also connected with acquisition module, control module, human-computer interaction module and communication module, two NIOS II soft-core processors are all configured to quick core, use μ C/OS II embedded real-time operating system, one NIOS II soft-core processor is for the data that obtain acquisition module and collect and carry out relay protection logic process, then result is fed back to control module, it with the addition of floating-point operation, the hardware user instruction of 32 bit stream line structure cordic algorithms, can the computing of supportive protection floating-point arithmetic, simplify and adopt fixed-point number computing to require high shortcoming to developer, acquisition module comprises the ADC converter for gathering analog quantity and opens inbound port, ADC converter with open the tri-state bridge interface of inbound port by PIO kernel and be connected with Avalon bus module, tri-state bridge interface is also connected with SRAM, ADC converter is 3 parallel AD, maximumly support 24 road analog quantity channel parallel acquisitions, by sheet selected control system, 96 road analog acquisitions can be supported, open inbound port simultaneously and support 8 groups, Mei Zu 16 tunnel, totally 128 tunnels are opened into collection, can meet the overwhelming majority and open into application demand, control module comprises outputs port and LED, Avalon bus module by the universaling I/O port of PIO kernel with output port and LED is connected, output port and support at most 16 tunnels, LED supports 12 to large, 2nd NIOS II soft-core processor is responsible for the external communication of communication module and human-computer interaction module, communication module comprises debug port, two external PORT COM, PORT COM for subsequent use and two ethernet controllers, debug port, two external PORT COM are all connected with Avalon bus module by UART kernel with PORT COM for subsequent use, two ethernet controllers are connected with Avalon bus module respectively by an ethernet controller interface, and two external PORT COM support RS232/RS485, debug port is used for communicating with PC debugging acid, one NIOS II soft-core processor carries out internal debugging by debug port, 2nd NIOS II soft-core processor is responsible for the external communication of two external PORT COM and individual ethernet controller and is carried out communication or externally communication between plate by PORT COM for subsequent use, communication module also reserved I/O interface can be used for increasing communication IP function flexibly, strengthens the extensibility of communication aspect, 2nd NIOS II soft-core processor with the addition of floating-point operation equally, the hardware user instruction of 32 bit stream line structure cordic algorithms, can the computing of supportive protection floating-point arithmetic, transplant LwIP Ethernet protocol stack simultaneously, to support ethernet communication function, human-computer interaction module comprises charactron, LCD display and button, and Avalon bus module is connected with charactron, LCD display and button by the universaling I/O port of PIO kernel,
This embedded dual core relay protection system based on FPGA also comprises SDRAM, EPCS64 configurator, RTC and EEPROM, SDRAM is connected with Avalon bus module by sdram controller, EPCS64 configurator is connected with Avalon bus module by EPCS controller, RTC with EEPROM is connected with Avalon bus module by I2C controller; The data-line width of SDRAM is 32, program running space and memory headroom, the power down storage space of data-line width to be the SRAM of 16 be NIOS II soft-core processor, EPCS64 configurator is used for storing the program image of the configuration file of FPGA, the program image of NIOS II soft-core processor and the 2nd NIOS II soft-core processor; The bootloader of the one NIOS II soft-core processor to leave on sheet in ROM EPCS Controller.
As shown in Figure 2, the software architecture of NIOS II soft-core processor comprises:
Self-inspection task: for self-checking system related peripherals such as ADC, EEPROM, protection definite value and each task abnormity function for monitoring;
Dual-Core Communication task: for double-core information interaction;
Quick calculation task: be used for as analog quantity sampling, open into collection, output control and relay protective scheme calculating fast, this task run is at interrupt levels, most effective;
Calculation task at a slow speed: logic operation in task level, for the relay protective scheme at a slow speed such as survey calculation;
The software architecture of the 2nd NIOS II soft-core processor comprises:
Dual-Core Communication task: for double-core information interaction;
Self-inspection task: for each task abnormity function for monitoring of system;
Serial communication task: for the function such as debugging acid, externally communication;
Network communication task: for Ethernet TCP/IP communication;
Man-machine interface task: the mutual and display for man-machine interface.
As shown in Figure 3, NIOS II soft-core processor and the 2nd NIOS II soft-core processor are by the communication of mailbox module memory, and support full duplex communication, communication efficiency is higher.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of described term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
With above-mentioned according to desirable embodiment of the present invention for enlightenment, by above-mentioned description, relevant staff in the scope not departing from this invention technological thought, can carry out various change and amendment completely.The technical scope of this invention is not limited to the content on instructions, must determine its technical scope according to right.
Claims (7)
1. the embedded dual core relay protection system based on FPGA, it is characterized in that: comprise NIOS II soft-core processor, 2nd NIOS II soft-core processor, Avalon bus module and mailbox module, described mailbox model calling to be connected with the 2nd NIOS II soft-core processor at described NIOS II soft-core processor and to be connected with described Avalon bus module, described Avalon bus module connection is also connected with acquisition module, control module, human-computer interaction module and communication module, described NIOS II soft-core processor is for the data that obtain acquisition module and collect and carry out relay protection logic process, then result is fed back to described control module, described 2nd NIOS II soft-core processor is responsible for the external communication of communication module and human-computer interaction module.
2. as claimed in claim 1 based on the embedded dual core relay protection system of FPGA; it is characterized in that: described acquisition module comprises the ADC converter for gathering analog quantity and opens inbound port; described ADC converter with open the tri-state bridge interface of inbound port by PIO kernel and be connected with described Avalon bus module, described tri-state bridge interface is also connected with SRAM.
3. as claimed in claim 1 based on the embedded dual core relay protection system of FPGA; it is characterized in that: described control module comprises outputs port and LED, described Avalon bus module outputs port by the universaling I/O port of PIO kernel with described and LED is connected.
4. as claimed in claim 1 based on the embedded dual core relay protection system of FPGA, it is characterized in that: described communication module comprises debug port, two external PORT COM, PORT COM for subsequent use and two ethernet controllers, described debug port, two external PORT COM are all connected with described Avalon bus module by UART kernel with PORT COM for subsequent use, described two ethernet controllers are connected with described Avalon bus module respectively by an ethernet controller interface, described NIOS II soft-core processor carries out internal debugging by debug port, described 2nd NIOS II soft-core processor is responsible for the external communication of two external PORT COM and individual ethernet controller and is carried out communication or externally communication between plate by PORT COM for subsequent use.
5. as claimed in claim 1 based on the embedded dual core relay protection system of FPGA; it is characterized in that: described human-computer interaction module comprises charactron, LCD display and button, described Avalon bus module is connected with described charactron, LCD display and button by the universaling I/O port of PIO kernel.
6. the embedded dual core relay protection system based on FPGA as described in any one of claim 1 ~ 5; it is characterized in that: also comprise SDRAM, EPCS64 configurator, RTC and EEPROM; described SDRAM is connected with described Avalon bus module by sdram controller; described EPCS64 configurator is connected with described Avalon bus module by EPCS controller, and described RTC with EEPROM is connected with described Avalon bus module by I2C controller.
7. as claimed in claim 6 based on the embedded dual core relay protection system of FPGA, it is characterized in that: described NIOS II soft-core processor is connected with the reset pin of described NIOS II soft-core processor by PIO kernel.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105653384A (en) * | 2015-12-30 | 2016-06-08 | 惠州市伟乐科技股份有限公司 | Soft-core CPU resetting method and master-slave type system |
| CN106020021A (en) * | 2016-05-20 | 2016-10-12 | 中车青岛四方车辆研究所有限公司 | High performance signal processing board |
| CN108095757A (en) * | 2017-12-22 | 2018-06-01 | 上海迈动医疗器械股份有限公司 | A kind of hand-held bladder surveys capacitance device and bladder is surveyed and holds implementation method |
| CN108155619A (en) * | 2017-12-31 | 2018-06-12 | 长园深瑞继保自动化有限公司 | Protective relaying device multi-core CPU embedded system handles method and platform |
| CN109871353A (en) * | 2019-03-26 | 2019-06-11 | 广东高云半导体科技股份有限公司 | Electronic equipment and its FPGA applied to artificial intelligence |
| CN110209626A (en) * | 2019-05-27 | 2019-09-06 | 哈尔滨工程大学 | A kind of Ethernet data Transmission system and method based on AVALON bus |
| CN111400986A (en) * | 2020-02-19 | 2020-07-10 | 西安智多晶微电子有限公司 | Integrated circuit computing device and computing processing system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0924588A1 (en) * | 1997-10-16 | 1999-06-23 | Varma, Dhruv | Electronic thermostat control unit and its use in multipoint temperature controller for refrigeration and heating systems |
| CN102853831A (en) * | 2012-09-07 | 2013-01-02 | 中南大学 | Legged robot state sensing system based on dual core processing technology |
| CN203233156U (en) * | 2013-04-23 | 2013-10-09 | 陕西天利自动化设备有限公司 | Relay protection device based on dual core processor |
| CN104363373A (en) * | 2014-11-06 | 2015-02-18 | 中国航空工业集团公司洛阳电光设备研究所 | NiosII based automatic infrared-image focusing system and method thereof |
-
2015
- 2015-03-11 CN CN201510107412.XA patent/CN104698941A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0924588A1 (en) * | 1997-10-16 | 1999-06-23 | Varma, Dhruv | Electronic thermostat control unit and its use in multipoint temperature controller for refrigeration and heating systems |
| CN102853831A (en) * | 2012-09-07 | 2013-01-02 | 中南大学 | Legged robot state sensing system based on dual core processing technology |
| CN203233156U (en) * | 2013-04-23 | 2013-10-09 | 陕西天利自动化设备有限公司 | Relay protection device based on dual core processor |
| CN104363373A (en) * | 2014-11-06 | 2015-02-18 | 中国航空工业集团公司洛阳电光设备研究所 | NiosII based automatic infrared-image focusing system and method thereof |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105653384A (en) * | 2015-12-30 | 2016-06-08 | 惠州市伟乐科技股份有限公司 | Soft-core CPU resetting method and master-slave type system |
| CN106020021A (en) * | 2016-05-20 | 2016-10-12 | 中车青岛四方车辆研究所有限公司 | High performance signal processing board |
| CN106020021B (en) * | 2016-05-20 | 2019-02-12 | 中车青岛四方车辆研究所有限公司 | High performance signal processing board |
| CN108095757A (en) * | 2017-12-22 | 2018-06-01 | 上海迈动医疗器械股份有限公司 | A kind of hand-held bladder surveys capacitance device and bladder is surveyed and holds implementation method |
| CN108155619A (en) * | 2017-12-31 | 2018-06-12 | 长园深瑞继保自动化有限公司 | Protective relaying device multi-core CPU embedded system handles method and platform |
| CN109871353A (en) * | 2019-03-26 | 2019-06-11 | 广东高云半导体科技股份有限公司 | Electronic equipment and its FPGA applied to artificial intelligence |
| CN110209626A (en) * | 2019-05-27 | 2019-09-06 | 哈尔滨工程大学 | A kind of Ethernet data Transmission system and method based on AVALON bus |
| CN110209626B (en) * | 2019-05-27 | 2023-02-10 | 哈尔滨工程大学 | AVALON bus-based Ethernet data transmission system and method |
| CN111400986A (en) * | 2020-02-19 | 2020-07-10 | 西安智多晶微电子有限公司 | Integrated circuit computing device and computing processing system |
| CN111400986B (en) * | 2020-02-19 | 2024-03-19 | 西安智多晶微电子有限公司 | Integrated circuit computing equipment and computing processing system |
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