CN209496816U - A kind of silicon carbide power device chip bonding structure - Google Patents

A kind of silicon carbide power device chip bonding structure Download PDF

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Publication number
CN209496816U
CN209496816U CN201920473209.8U CN201920473209U CN209496816U CN 209496816 U CN209496816 U CN 209496816U CN 201920473209 U CN201920473209 U CN 201920473209U CN 209496816 U CN209496816 U CN 209496816U
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China
Prior art keywords
layer
silicon carbide
power device
device chip
carbide power
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Expired - Fee Related
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CN201920473209.8U
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Chinese (zh)
Inventor
夏国峰
尤显平
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Chongqing Three Gorges University
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Chongqing Three Gorges University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body

Abstract

The utility model discloses a kind of silicon carbide power device chip bonding structures, belong to microelectronic packaging technology field.In the silicon carbide power device chip bonding structure of the utility model, silicon carbide power device chip is connected on substrate by the first silver medal sinter layer and the bonding of the second silver medal sinter layer；First silver medal sinter layer is connect with the second silver medal sinter layer silver by thermocompression bonding；The first barrier layer and the first adhesive layer are configured in order between silicon carbide power device chip and the first silver medal sinter layer；The second adhesive layer and the second barrier layer are configured in order between second silver medal sinter layer and substrate.

Description

A kind of silicon carbide power device chip bonding structure
Technical field
The utility model relates to microelectronic packaging technology especially silicon carbide power device chip encapsulation technologies.
Background technique
The rapid development of aerospace, electric car and new energy power generation technology is so that the performance to power electronic system refers to Mark requires increasingly to improve, and high power device chip of the development and application in the extreme environments such as high temperature is current power electronic technique neck The emphasis direction of domain development.Due to based on first generation Semiconducting Silicon Materials (Si) and second generation semiconductor material (GaAs) Power device chip can not continue working under 200 DEG C or more of hot environment, and grow up later with silicon carbide (SiC) Material be representative third generation wide band gap semiconductor device chip the limit of working temperature can reach 500 DEG C or so it is even higher Temperature is more able to satisfy the demand for development of future electrical energy electronic technology.However, under this hot environment, existing chip bonding material Material-lead-free solder (Pb-free), which can melt, leads to Joint failure, can not be suitable for broad stopbands device chips such as silicon carbide (SiC) Bonding packaging.In recent years using be sintered nano silver technology as the low-temperature bonding technology of representative be current power device chip towards high temperature, The main trend of high reliability application development, the basic principle is that utilizing the high surface energy of the silver metal particles of nanoscale, low Melting point property is bonded to realize that chip is sintered with the low-pressure low-temperature of substrate.The silver-colored sinter layer of formation has excellent electricity, hot property, Fusing point is high, can bear 710 DEG C of maximum operating temperature, is the ideal structure for realizing silicon carbide power device chip bonding.
Silver sintering natural bed has apparent porous character, and bore hole size is located at sub-micron to micron range.In agglomerant Skill process needs to apply pressure to form the sinter layer that porosity is low, relatively compact, this causes sintering silver thickness to be difficult to standard Really control, and silver-colored sinter layer thickness is confined between several microns to tens microns.It is excessively thin to be sintered silver thickness, in hot environment Under will generate excessive shear strain and stress since the thermal expansion coefficient (CTE) of encapsulating structure material is different and concentrate, cause to burn Tie the reliability degradation of silver layer.At the same time, the growth of crystal grain and hole can occur under high temperature environment for silver-colored sinter layer, lead Micro-structure roughening is caused, this structure of silver-colored sinter layer is caused to be degenerated, is easier to that fatigue rupture occurs.In addition, if the chip size of bonding Excessive, when sintering, will hinder the volatilization of organic solvent in silver paste, form large area gas hole defect in sinter layer, cause to tie It closes intensity to be remarkably decreased, it is difficult to realize high quality and the sintering of high yield.
Therefore, in order to solve the above-mentioned reliability and yield issues that the sintering silver bonding of silicon carbide power device chip faces, Urgent need proposes a kind of reasonable chip bonding structure and preparation method thereof, silicon carbide power device chip sintering silver is effectively reduced The complexity and difficulty of bonding technology, while promoting reliability, yield and the yield of silicon carbide power device chip bonding.
Summary of the invention
The utility model is encapsulated for power device chip, and especially silicon carbide power device encapsulates, and provides a kind of letter List, high reliability, high yield, high yield chip bonding structure.
To reach above-mentioned purpose, the utility model provides a kind of silicon carbide power device chip bonding structure, in the reality With in novel silicon carbide power device chip structure, silicon carbide power device chip is burnt by the first silver medal sinter layer and the second silver medal Knot layer bonding is connected on substrate；First silver medal sinter layer is connect with the second silver medal sinter layer silver by thermocompression bonding；Silicon carbide power The first barrier layer and the first adhesive layer are configured in order between device chip and the first silver medal sinter layer；Second silver medal sinter layer and substrate Between be configured in order the second adhesive layer and the second barrier layer.
Embodiment according to the present utility model, the substrate panel use ceramic base copper-clad plate, organic substrate or copper base.
Embodiment according to the present utility model, first barrier layer and the second barrier layer can choose titanium (Ti), tantalum (Ta) or the metal materials such as tungsten (W).
Embodiment according to the present utility model, first adhesive layer and the second adhesive layer can choose silver (Ag), nickel (Ni) and the metal materials such as golden (Au).
The thickness range on embodiment according to the present utility model, first barrier layer and the second barrier layer is 0.05 micro- - 1.0 microns of rice.
The thickness range of embodiment according to the present utility model, first adhesive layer and the second adhesive layer be 0.1 micron- 5.0 micron.
The thickness range of embodiment according to the present utility model, the first silver medal sinter layer and the second silver medal sinter layer is 10 micro- - 40 microns of rice.
A kind of production method of silicon carbide power device chip structure disclosed by the utility model mainly includes following step It is rapid:
Step 1: configuring in order barrier layer and adhesive layer in the inactive face of silicon carbide power device wafer.On substrate panel Configure in order barrier layer and adhesive layer.The configuration method can be but be not limited to sputtering, vacuum evaporation and chemical plating method, It is preferable over sputtering method.The substrate panel can be but to be not limited to ceramic base copper-clad plate, organic substrate and copper base excellent, excellent Select ceramic base copper-clad plate.The barrier layer can be but be not limited to the metal materials such as titanium (Ti), tantalum (Ta) and tungsten (W), preferably Titanium (Ti).The adhesive layer can be but be not limited to the metal materials such as silver (Ag), nickel (Ni) and gold (Au), preferably silver (Ag). The thickness range on the barrier layer is 0.05 micron -1.0 microns, preferably 0.1 micron.The thickness range of the adhesive layer is 0.1 - 5.0 microns, preferably 1.0 microns of micron.
Step 2: nano mattisolda is printed on the adhesive layer of silicon carbide power device wafer with uniform thickness.By nanometer Silver paste is printed on the adhesive layer of substrate panel with uniform thickness.The silicon carbide power device wafer and substrate that will be completed for printing Panel, which is placed on warm table, be pressureless sintered to type, forms silver-colored sinter layer.Heating platen temperature range is set as 250 DEG C -350 DEG C, preferably 260 DEG C.Sintering time scope is set as -60 minutes 15 minutes, preferably 30 minutes.After the completion of sintering, the silver sintering The thickness range of layer is 15 microns -50 microns, preferably 25 microns.
Step 3: oxidation processes are carried out to the silver-colored sinter layer on silicon carbide power device wafer.Silver on substrate panel is burnt It ties layer and carries out oxidation processes.The oxidation treatment method can be but be not limited to steam oxidation and impregnate moisture absorption oxidation, excellent Select steam oxidation.
Step 4: the silver-colored sinter layer on silicon carbide power device wafer is processed by shot blasting.Silver on substrate panel is burnt Knot layer is processed by shot blasting.The polishing treatment method can be but be not limited to chemical mechanical polishing.It is described after polishing treatment The thickness range of silver-colored sinter layer is 10 microns -40 microns, preferably 20 microns.
Step 5: cutting silicon carbide power device wafer forms single silicon carbide power device chip of separation.Cut base Plate face plate forms the single substrate of separation.The cutting method can be but be not limited to blade cutting, laser cutting and water knife Cutting method.
Step 6: the silver-colored sinter layer on silicon carbide power device chip is configured at by base using surface mount mode face-to-face On silver-colored sinter layer on plate, configured silicon carbide power device chip and substrate are placed in together on warm table and carry out hot pressing The connection of silicon carbide power device chip bonding is realized in bonding.Heating platen temperature range is set as 250 DEG C -350 DEG C, preferably 300 ℃.Bonding time range is set as -90 minutes 15 minutes, preferably 45 minutes.Bonding pressure range is set as 0.1MPa-10MPa, It is preferred that 1MPa.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section according to the silicon carbide power device chip bonding result of the utility model embodiment.
Fig. 2A-Fig. 2 E be according to a kind of production method of silicon carbide power device chip structure disclosed by the utility model, Manufacturing process schematic diagram for the silicon carbide power device chip bonding embodiment shown in Fig. 1.
In above-mentioned figure, 1 it is silicon carbide power device chip die, 2 is substrate panel, 3 is the first barrier layer, 4 is second Barrier layer, 5 be the first adhesive layer, 6 be the second adhesive layer, 7 be the first silver medal sinter layer, 8 be the second silver medal sinter layer, 9 be silicon carbide Power device chip, 10 are substrate.
Specific embodiment
To keep the purpose of this utility model, technical solution and advantage clearer, with reference to the accompanying drawing to the utility model Specific embodiment be described in further detail.
The silicon carbide power device chip bonding structure is referring to FIG. 1, according to dimensional orientation from top to bottom in structure Successively are as follows: silicon carbide power device chip 9, the first barrier layer 3, the first adhesive layer 5, the first silver medal sinter layer 7, the second silver medal sinter layer 8, the second barrier layer 4, the second adhesive layer 6 and substrate 10.The substrate panel 2 can be but be not limited to ceramic base copper-clad plate, Organic substrate and copper base, preferably ceramic base copper-clad plate.First barrier layer 3 and the second barrier layer 4 can be but not limit to In the metal materials such as titanium (Ti), tantalum (Ta) and tungsten (W), preferably titanium (Ti).First adhesive layer 5 and the second adhesive layer 6 can be with For but be not limited to the metal materials, preferably silver (Ag) such as silver-colored (Ag), nickel (Ni) and golden (Au).First barrier layer 3 and second The thickness range on barrier layer 4 is 0.05 micron -1.0 microns, preferably 0.1 micron.First adhesive layer 5 and the second adhesive layer 6 Thickness range be 0.1 micron -5.0 microns, preferably 1.0 microns.The thickness of the first silver medal sinter layer 7 and the second silver medal sinter layer 8 Spending range is 10 microns -40 microns, preferably 20 microns.
The silicon carbide power device die bonding method the following steps are included:
Step 1: as shown in Figure 2 A, configuring in order the first barrier layer 3 and the in the inactive face of silicon carbide power device wafer 1 One adhesive layer 5.The second barrier layer 4 and the second adhesive layer 6 are configured in order on substrate panel 2.The configuration method can be but It is not limited to sputtering, vacuum evaporation and chemical plating method, is preferable over sputtering method.The substrate panel 2 can be but not limit to In ceramic base copper-clad plate, organic substrate and copper base, preferably ceramic base copper-clad plate.First barrier layer 3 and the second barrier layer 4 It can be but be not limited to the metal materials such as titanium (Ti), tantalum (Ta) and tungsten (W), preferably titanium (Ti).First adhesive layer 5 and Two adhesive layers 6 can be but be not limited to the metal materials such as silver (Ag), nickel (Ni) and gold (Au), preferably silver (Ag).Described first The thickness range on barrier layer 3 and the second barrier layer 4 is 0.05 micron -1.0 microns, preferably 0.1 micron.First adhesive layer 5 Thickness range with the second adhesive layer 6 is 0.1 micron -5.0 microns, preferably 1.0 microns.
Step 2: as shown in Figure 2 B, nano mattisolda being printed on the of silicon carbide power device wafer 1 with uniform thickness On one adhesive layer 5.Nano mattisolda is printed on the second adhesive layer 6 of substrate panel 2 with uniform thickness.By what is be completed for printing Silicon carbide power device wafer 1 and substrate panel 2, which are respectively placed in, to carry out being pressureless sintered to type in warm table (not shown), is formed First silver medal sinter layer 7 and the second silver medal sinter layer 8.Heating platen temperature range is set as 250 DEG C -350 DEG C, preferably 260 DEG C.When sintering Between range be set as -60 minutes 15 minutes, preferably 30 minutes.The first silver medal sinter layer 7 and the sintering of the second silver medal after the completion of sintering The thickness range of layer 8 is 15 microns -50 microns, preferably 25 microns.After the completion of sintering, the first silver medal sinter layer 7 and the second silver medal The thickness range of sinter layer 8 is 15 microns -50 microns, preferably 25 microns.
Step 3: oxidation processes are carried out to the first silver medal sinter layer 7 on silicon carbide power device wafer 1.To substrate panel 2 On the second silver medal sinter layer 8 carry out oxidation processes.The oxidation treatment method can be but be not limited to steam oxidation and leaching Steep moisture absorption oxidation, preferably steam oxidation.By oxidation processes, in 8 inner void of the first silver medal sinter layer 7 and the second silver medal sinter layer Surface Creation silver oxide film, it is inhibited to micro-structure roughening, it can keep under high temperature environment stable.
Step 4: as shown in Figure 2 C, after oxidation processes, to the first silver medal sinter layer 7 on silicon carbide power device wafer 1 into Row polishing treatment is processed by shot blasting the second silver medal sinter layer 8 on substrate panel 2.The polishing treatment method can be but It is not limited to chemical mechanical polishing.The thickness range of the first silver medal sinter layer 7 and the second silver medal sinter layer 8 is 10 after polishing treatment - 40 microns, preferably 20 microns of micron.Purpose to the first silver medal sinter layer 7 and the second silver medal sinter layer polishing treatment is to be formed Fine and close, flat and smooth surface promotes subsequent hot pressing bonding quality.
Step 5: as shown in Figure 2 D, cutting silicon carbide power device wafer 1, form single silicon carbide power device of separation Chip 9.Cutting substrate panel 2 forms the single substrate 10 of separation.The cutting method can be but be not limited to blade and cut It cuts, be cut by laser and high pressure waterjet method.
Step 6: as shown in Figure 2 E, being sintered the first silver medal on silicon carbide power device chip 9 using surface mount mode Layer 7 is configured on the second silver medal sinter layer 8 on substrate 10 face-to-face, by configured silicon carbide power device chip 9 and substrate 10 are placed in warm table (not shown) together and carry out thermocompression bonding, realize bonding connection.Heating platen temperature range is set as 250 DEG C -350 DEG C, preferably 300 DEG C.Bonding time range is set as -90 minutes 15 minutes, preferably 45 minutes.Bonding pressure range is set It is set to 0.1MPa-10MPa, preferably 1MPa.The purpose of thermocompression bonding be by the first silver medal sinter layer 7 and the second silver medal sinter layer 8 it Between atom diffusion realize bonding connection.
The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all practical at this Within novel spirit and principle, any modification, equivalent replacement, improvement and so on should be included in the guarantor of the utility model Within the scope of shield.

Claims (7)

1. a kind of silicon carbide power device chip bonding structure, which is characterized in that the structure includes:
Silicon carbide power device chip is connected on substrate by the first silver medal sinter layer and the bonding of the second silver medal sinter layer；First silver medal is burnt Knot layer is connect with the second silver medal sinter layer silver by thermocompression bonding；Between silicon carbide power device chip and the first silver medal sinter layer successively Configured with the first barrier layer and the first adhesive layer；The second adhesive layer and second are configured in order between second silver medal sinter layer and substrate Barrier layer.
2. a kind of silicon carbide power device chip bonding structure according to claim 1, which is characterized in that substrate panel is adopted With ceramic base copper-clad plate, organic substrate or copper base.
3. a kind of silicon carbide power device chip bonding structure according to claim 1, which is characterized in that first resistance Barrier and the second barrier layer can choose the metal materials such as titanium (Ti), tantalum (Ta) or tungsten (W).
4. a kind of silicon carbide power device chip bonding structure according to claim 1, which is characterized in that described first is viscous It connects layer and the second adhesive layer can choose the metal materials such as silver (Ag), nickel (Ni) and gold (Au).
5. a kind of silicon carbide power device chip bonding structure according to claim 1, which is characterized in that first resistance The thickness range on barrier and the second barrier layer is 0.05 micron -1.0 microns.
6. a kind of silicon carbide power device chip bonding structure according to claim 1, which is characterized in that described first is viscous The thickness range for connecing layer and the second adhesive layer is 0.1 micron -5.0 microns.
7. a kind of silicon carbide power device chip bonding structure according to claim 1, which is characterized in that first silver medal The thickness range of sinter layer and the second silver medal sinter layer is 10 microns -40 microns.
CN201920473209.8U 2019-04-10 2019-04-10 A kind of silicon carbide power device chip bonding structure Expired - Fee Related CN209496816U (en)

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Granted publication date: 20191015

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