CN209496815U - A kind of power device chip encapsulating structure - Google Patents
A kind of power device chip encapsulating structure Download PDFInfo
- Publication number
- CN209496815U CN209496815U CN201920472148.3U CN201920472148U CN209496815U CN 209496815 U CN209496815 U CN 209496815U CN 201920472148 U CN201920472148 U CN 201920472148U CN 209496815 U CN209496815 U CN 209496815U
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- China
- Prior art keywords
- layer
- power device
- device chip
- encapsulating structure
- microns
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Abstract
The utility model discloses a kind of power device chip encapsulating structures, belong to microelectronic packaging technology field.In the power device chip encapsulating structure of the utility model, power device chip is connected on substrate by pressureless sintering the first nano silver solder layer and the bonding of the second nano silver solder layer, and thermal sheet is configured between the first nano silver solder layer and the second nano silver solder layer.Encapsulating structure is formed using epoxy molding compound cladding sealing.
Description
Technical field
The utility model relates to microelectronic packaging technology especially power device chip encapsulation technologies.
Background technique
The rapid development of aerospace, electric car and new energy power generation technology is so that the performance to power electronic system refers to
Mark requires increasingly to improve, and high power device chip of the development and application in the extreme environments such as high temperature is current power electronic technique neck
The emphasis direction of domain development.For example, using silicon carbide (SiC) material as the pole of the third generation wide band gap semiconductor device chip of representative
Limit operating temperature can reach 500 DEG C or so even more high temperature, more be able to satisfy the demand for development of future electrical energy electronic technology.However,
Under this hot environment, existing chip encapsulation material-lead-free solder (Pb-free), which can melt, leads to Joint failure, can not
Suitable for the requirement of high power device chip package.It is in recent years current to be sintered nano silver technology as the low-temperature bonding technology of representative
Power device chip towards high temperature, high reliability application development main trend, the basic principle is that utilize nanoscale silver gold
High surface energy, the eutectic dot characteristics of metal particles are bonded to realize that chip is sintered with the low-pressure low-temperature of substrate.The silver-colored sinter layer of formation
With excellent electricity, hot property, fusing point is high, can bear 710 DEG C of maximum operating temperature, is to realize power device chip encapsulation
Ideal structure.
Silver-colored sinter layer has apparent porous character, and bore hole size is located at sub-micron to micron range.In sintering process mistake
Journey needs to apply pressure to form the sinter layer that porosity is low, relatively compact, this causes sintering silver thickness to be difficult to accurately control
System, and silver-colored sinter layer thickness is confined between several microns to tens microns.Be sintered silver thickness it is excessively thin, under high temperature environment by
Excessive shear strain and stress will be generated in thermal expansion coefficient (CTE) difference of encapsulating structure material to concentrate, and lead to sintering silver
The reliability degradation of layer.At the same time, the growth of crystal grain and hole can occur under high temperature environment for silver-colored sinter layer, cause micro-
Structure roughening, causes this structure of silver-colored sinter layer to be degenerated, and is easier to that fatigue rupture occurs.In addition, if the chip size of bonding is excessive,
The volatilization that organic solvent in silver paste will be hindered when sintering forms large area gas hole defect in sinter layer, causes to combine strong
Degree is remarkably decreased, it is difficult to realize high quality and the sintering of high yield.
Therefore, in order to solve the above-mentioned reliability and yield issues that power device chip encapsulation technology faces, it is badly in need of proposing
A kind of reasonable chip encapsulation technology and preparation method thereof, the complexity and difficulty of power device chip packaging technology is effectively reduced
Degree, while reliability, yield and the yield of hoisting power device chip encapsulation.
Summary of the invention
The utility model is encapsulated for power device chip, provides a kind of simple, high reliability, high yield, high yield
Chip-packaging structure.
To reach above-mentioned purpose, the utility model provides a kind of power device chip encapsulating structure, comprising: power device core
Piece is substrate, the first barrier layer, the first adhesive layer, the second barrier layer, the second adhesive layer, the first nano mattisolda layer, thermally conductive thin
Piece, the second nano mattisolda layer, epoxy molding compound.The power device chip passes through the first nano silver described in pressureless sintering
Solder layer and the bonding of the second nano silver solder layer are connected on the substrate.The first nano silver solder layer and the second nano silver
The thermal sheet is configured between solder layer.Successively match between the power device chip and the second nano silver solder layer
It is equipped with first barrier layer and the first adhesive layer.It is configured in order between the substrate and the firstth nano silver solder layer
Second barrier layer and the second adhesive layer.The epoxy molding compound cladding sealing forms encapsulating structure.
Embodiment according to the present utility model, the substrate use ceramic base copper-clad plate, organic substrate or copper base.
Embodiment according to the present utility model, first barrier layer and the second barrier layer can choose titanium (Ti), tantalum
(Ta) or the metal materials such as tungsten (W).
Embodiment according to the present utility model, first adhesive layer and the second adhesive layer can choose silver (Ag), nickel
(Ni) and the metal materials such as golden (Au).
The thickness range on embodiment according to the present utility model, first barrier layer and the second barrier layer is 0.05 micro-
- 1.0 microns of rice.
The thickness range of embodiment according to the present utility model, first adhesive layer and the second adhesive layer be 0.1 micron-
5.0 micron.
Embodiment according to the present utility model, the thickness model of the first nano mattisolda layer and the second nano mattisolda layer
Enclose is 10 microns -50 microns.
Embodiment according to the present utility model, the thickness range of the thermal sheet are 20 microns -200 microns.
Embodiment according to the present utility model, the thermal sheet is using metal materials such as nonmetallic materials or copper such as ceramics
Material.
A kind of production method of power device chip encapsulating structure disclosed by the utility model, mainly comprises the steps that
Step 1: configuring in order the first barrier layer and the first adhesive layer in the inactive face of power device chip.On substrate according to
The second barrier layer of secondary configuration and the second adhesive layer.The configuration method can be but be not limited to sputtering, vacuum evaporation and chemistry
Electroplating method is preferable over sputtering method.The substrate can be but be not limited to ceramic base copper-clad plate, organic substrate and copper base
It is excellent, preferred copper base.First barrier layer and the second barrier layer can be but be not limited to titanium (Ti), tantalum (Ta) and tungsten (W)
Equal metal materials, preferably titanium (Ti).First adhesive layer and the second adhesive layer can be but be not limited to silver (Ag), nickel (Ni)
With the metal materials such as golden (Au), preferably silver-colored (Ag).The thickness range on first barrier layer and the second barrier layer be 0.05 micron-
1.0 microns, preferably 0.1 micron.The thickness range of first adhesive layer and the second adhesive layer is 0.1 micron -5.0 microns, excellent
Select 1.0 microns.
Step 2: the first nano mattisolda layer is printed on the second adhesive layer of substrate with uniform thickness.
Step 3: thermal sheet is mounted on the first nano mattisolda layer.The thermal sheet is using ceramics
(ceramic) metal materials such as nonmetallic materials or copper (Cu) such as；The thickness range of the thermal sheet is 20 micron -200
Micron, preferential 80 microns.
Step 4: the second nano mattisolda layer of uniform thickness is printed on thermal sheet.
Step 5: power device chip is mounted on the second nano mattisolda layer.
Step 6: pressureless sintering molding being carried out to the first nano mattisolda layer and the second nano mattisolda layer, completes power device
Part chip is bonded connection with substrate.The power device chip being completed for printing and substrate are placed in and carry out burning without pressure on warm table
Form type, forms silver-colored sinter layer.The temperature range of the sintering is set as 250 DEG C -350 DEG C；Sintering time scope is set as 15
- 60 minutes minutes；The thickness range of the first nano mattisolda layer and the second nano mattisolda layer is after the completion of sinter molding
10 microns -50 microns, preferential 20 microns.
Step 7: the first nano mattisolda layer and the second nano mattisolda layer to sinter molding carry out oxidation processes.It is described
Oxidation treatment method is using steam oxidation or impregnates moisture absorption method for oxidation.
Step 8: wire bonding is bonded using plain conductor, realizes the electrical of power device chip and external environment
Connection.
Step 9: plastic packaging molding carries out plastic packaging using epoxy molding compound, completes power device chip encapsulation.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section according to the power device chip encapsulated result of the utility model embodiment.
Fig. 2A-Fig. 2 F is according to a kind of production method of power device chip structure disclosed by the utility model, with Fig. 1 institute
Show the manufacturing process schematic diagram for power device chip encapsulation embodiment.
In above-mentioned figure, 1 it is power device chip, 2 is substrate, 3 is the first barrier layer, 4 is the second barrier layer, 5 is first
Adhesive layer, 6 be the second adhesive layer, 7 be the first nano mattisolda layer, 8 be thermal sheet, 9 be the second nano mattisolda layer, 10 be
Epoxy molding compound.
Specific embodiment
To keep the purpose of this utility model, technical solution and advantage clearer, with reference to the accompanying drawing to the utility model
Specific embodiment be described in further detail.
The power device chip encapsulating structure is referring to FIG. 1, in structure successively according to dimensional orientation from bottom to up are as follows:
Substrate 2, the second barrier layer 4, the second adhesive layer 6, the first nano mattisolda layer 7, thermal sheet 8, the second nano mattisolda layer 9,
First adhesive layer 5, the first barrier layer 3, power device chip 1, the cladding sealing above structure of epoxy molding compound 10.The base
Plate 2 can be but be not limited to ceramic base copper-clad plate, organic substrate and copper base, preferably ceramic base copper-clad plate.First resistance
Barrier 3 and the second barrier layer 4 can be but be not limited to the metal materials such as titanium (Ti), tantalum (Ta) and tungsten (W), preferably titanium (Ti).
First adhesive layer 5 and the second adhesive layer 6 can be but be not limited to the metal materials such as silver-colored (Ag), nickel (Ni) and gold (Au),
It is preferred that silver-colored (Ag).The thickness range on first barrier layer 3 and the second barrier layer 4 is 0.05 micron -1.0 microns, and preferably 0.1 is micro-
Rice.The thickness range of first adhesive layer 5 and the second adhesive layer 6 is 0.1 micron -5.0 microns, preferably 1.0 microns.It sinters into
The thickness range of the first nano mattisolda layer and the second nano mattisolda layer is 10 microns -50 microns after the completion of type, preferably
20 microns.The thermal sheet is using metal materials such as nonmetallic materials or copper (Cu) such as ceramic (ceramic)；It is described thermally conductive
The thickness range of thin slice is 20 microns -200 microns, preferential 80 microns.
The power device chip packaging method the following steps are included:
Step 1: as shown in Figure 2 A, configuring in order the first barrier layer 3 and the first bonding in the inactive face of power device chip 1
Layer 5.The second barrier layer 4 and the second adhesive layer 6 are configured in order on a substrate 2.The configuration method can be but be not limited to splash
It penetrates, vacuum evaporation and chemical plating method, is preferable over sputtering method.The substrate 2 can be but be not limited to ceramic base copper-clad plate,
Organic substrate and copper base, preferably ceramic base copper-clad plate.First barrier layer 3 and the second barrier layer 4 can be but not limit to
In the metal materials such as titanium (Ti), tantalum (Ta) and tungsten (W), preferably titanium (Ti).First adhesive layer 5 and the second adhesive layer 6 can be with
For but be not limited to the metal materials, preferably silver (Ag) such as silver-colored (Ag), nickel (Ni) and golden (Au).First barrier layer 3 and second
The thickness range on barrier layer 4 is 0.05 micron -1.0 microns, preferably 0.1 micron.First adhesive layer 5 and the second adhesive layer 6
Thickness range be 0.1 micron -5.0 microns, preferably 1.0 microns.
Step 2: as shown in Figure 2 B, the first nano mattisolda layer 7 being printed on to the second adhesive layer of substrate 2 with uniform thickness
On 6.
Step 3: as shown in Figure 2 C, thermal sheet 8 being mounted on the first nano mattisolda layer 7.The thermal sheet 8 is adopted
With metal materials such as nonmetallic materials or copper (Cu) such as ceramic (ceramic)；The thickness range of the thermal sheet 8 is 20 micro-
- 200 microns, preferential 80 microns of rice.
Step 4: as shown in Figure 2 D, the second nano mattisolda layer 9 of uniform thickness is printed on thermal sheet 8.
Step 5: as shown in Figure 2 E, power device chip 1 being mounted on the second nano mattisolda layer 9.
Step 6: pressureless sintering molding being carried out to the first nano mattisolda layer 7 and the second nano mattisolda layer 9, completes power
Device chip 1 is bonded connection with substrate 2.The temperature range of the sintering is set as 250 DEG C -350 DEG C；Sintering time scope is set
It is set to -60 minutes 15 minutes；The thickness of the first nano mattisolda layer and the second nano mattisolda layer after the completion of sinter molding
Range is 10 microns -50 microns, preferential 20 microns.
Step 7: the first nano mattisolda layer 7 and the second nano mattisolda layer 9 to sinter molding carry out oxidation processes.Institute
Oxidation treatment method is stated using steam oxidation or impregnates moisture absorption method for oxidation.
Step 8: wire bonding is bonded using plain conductor (not shown), realizes power device chip 1 and external rings
The electrical connection in border.
Step 9: as shown in Figure 2 F, plastic packaging molding carries out plastic packaging cladding sealing using epoxy molding compound 10, completes function
The encapsulation of rate device chip.
The above is only the preferred embodiment of the present invention, is not intended to limit the utility model, all practical at this
Within novel spirit and principle, any modification, equivalent replacement, improvement and so on should be included in the guarantor of the utility model
Within the scope of shield.
Claims (9)
1. a kind of power device chip encapsulating structure, which is characterized in that the encapsulating structure includes:
Power device chip, substrate, the first barrier layer, the first adhesive layer, the second barrier layer, the second adhesive layer, the first nano silver
Layer of solder paste, thermal sheet, the second nano mattisolda layer, epoxy molding compound；The power device chip passes through pressureless sintering
The first nano silver solder layer and the bonding of the second nano silver solder layer are connected on the substrate；First nanometer of silver solder
The thermal sheet is configured between layer and the second nano silver solder layer；The power device chip and second nanometer of silver soldering
First barrier layer and the first adhesive layer are configured in order between the bed of material；The substrate and the first nano silver solder layer it
Between be configured in order second barrier layer and the second adhesive layer；The epoxy molding compound cladding sealing forms encapsulation knot
Structure.
2. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that the substrate is using ceramics
Base copper-clad plate, organic substrate or copper base.
3. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that first barrier layer and
Second barrier layer can choose the metal materials such as titanium (Ti), tantalum (Ta) or tungsten (W).
4. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that first adhesive layer and
Second adhesive layer can choose the metal materials such as silver (Ag), nickel (Ni) and gold (Au).
5. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that first barrier layer and
The thickness range on the second barrier layer is 0.05 micron -1.0 microns.
6. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that first adhesive layer and
The thickness range of second adhesive layer is 0.1 micron -5.0 microns.
7. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that first nanometer of silver soldering
The thickness range of layer of paste and the second nano mattisolda layer is 10 microns -50 microns.
8. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that the thickness of the thermal sheet
Spending range is 20 microns -200 microns.
9. a kind of power device chip encapsulating structure according to claim 1, which is characterized in that the thermal sheet uses
The metal materials such as the nonmetallic materials such as ceramics or copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920472148.3U CN209496815U (en) | 2019-04-09 | 2019-04-09 | A kind of power device chip encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920472148.3U CN209496815U (en) | 2019-04-09 | 2019-04-09 | A kind of power device chip encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209496815U true CN209496815U (en) | 2019-10-15 |
Family
ID=68157593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920472148.3U Expired - Fee Related CN209496815U (en) | 2019-04-09 | 2019-04-09 | A kind of power device chip encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209496815U (en) |
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2019
- 2019-04-09 CN CN201920472148.3U patent/CN209496815U/en not_active Expired - Fee Related
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191015 Termination date: 20200409 |
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| CF01 | Termination of patent right due to non-payment of annual fee |