CN209487516U - Semiconductor device structure - Google Patents
Semiconductor device structure Download PDFInfo
- Publication number
- CN209487516U CN209487516U CN201821811099.3U CN201821811099U CN209487516U CN 209487516 U CN209487516 U CN 209487516U CN 201821811099 U CN201821811099 U CN 201821811099U CN 209487516 U CN209487516 U CN 209487516U
- Authority
- CN
- China
- Prior art keywords
- doping type
- semiconductor device
- device structure
- source electrode
- well region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The utility model provides a kind of semiconductor device structure, comprising: the substrate of the first doping type, the first well region of the second doping type, the first drain electrode, the second well region of the first source electrode, the first gate oxide, polysilicon gate, the second gate oxide, the substrate material layer of the second doping type, the second doping type, second drain electrode, the second source electrode and the first doping type body area.The semiconductor device structure of the utility model can be effectively reduced under the premise of obtaining high voltage than conducting resistance, break the existing silicon limit.
Description
Technical field
The utility model belongs to technical field of semiconductors, more particularly to a kind of semiconductor device structure.
Background technique
LDMOS (Lateral Diffused MOSFET, the horizontal proliferation of traditional RESURF (reducing surface field) technology
Metal-oxide semiconductor (MOS)) main element be respectively positioned in body silicon substrate, generally pass through the drift region (example in the first doping type
Such as N-type drift region) buried layer (for example p type buried layer) of corresponding second doping type of injection, improves and partly leads by exhausting mutually
The pressure resistance of body device architecture；However, improve pressure resistance and reduction than conducting resistance (conducting resistance × area) be it is contradictory, low ratio is led
The drift region of logical higher first doping type of resistance requirement concentration, and if the drift region of these the first doping types cannot be by
The region depletion of second doping type, then pressure resistance can be greatly reduced.Therefore, to realize that the ratio conducting resistance in arable land is just needed in depth
The first doping type trap in introduce the buried layer of more deeper second doping types to exhaust concentration higher deep first
The trap of doping type, however, the buried layer of the second doping type introduced is more, technique is more difficult to realize.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of junction of semiconductor device
Structure, for solving the above-mentioned problems in the prior art.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor device structure, and described half
Conductor device structure includes:
The substrate of first doping type；
First well region of the second doping type, in the substrate of first doping type；
First drain electrode, in the first well region of second doping type；
First source electrode, in the substrate of first doping type；
First gate oxide, positioned at the upper surface of substrate of first doping type；
Polysilicon gate, positioned at the upper surface of part first gate oxide；
Second gate oxide, positioned at the upper table of the upper surface of the polysilicon gate and part first gate oxide
Face；
The substrate material layer of second doping type, positioned at the upper surface of second gate oxide；
Second well region of the second doping type, in the substrate material layer of second doping type；
Second drain electrode in the substrate material layer of second doping type, and is located at second doping type
The side of second well region；Second drain electrode is shorted with first drain electrode；
Second source electrode in the substrate material layer of second doping type, and is located at second doping type
Second well region is away from the side of second drain electrode；Second source electrode with described first source electrode are shorted；
The body area of first doping type in the substrate material layer of second doping type, and is located at described second
Between source electrode and the second well region of second doping type.
A kind of preferred embodiment of semiconductor device structure as the utility model, the semiconductor device structure further include
Field oxide positioned at the substrate surface of first doping type, and is located at the substrate and described the of first doping type
Between one gate oxide.
A kind of preferred embodiment of semiconductor device structure as the utility model, the semiconductor device structure also wrap
It includes:
The well region of first doping type, in the substrate of first doping type；First source electrode is located at described
In the well region of first doping type；
The heavily doped region of first doping type, in the well region of first doping type, and with first source
Pole is mutually shorted.
A kind of preferred embodiment of semiconductor device structure as the utility model, the semiconductor device structure also wrap
It includes；
Dielectric layer, upper surface and the exposed field oxide positioned at the substrate material layer of second doping type
Upper surface；
Drain electrode, in the dielectric layer and the upper surface of the dielectric layer, the drain electrode is by described first
Drain electrode is shorted with second drain electrode；
Source electrode, in the dielectric layer and the upper surface of the dielectric layer, the source electrode is by described first
Source electrode with described second source electrode are shorted.
A kind of preferred embodiment of semiconductor device structure as the utility model, second drain electrode are the second doping class
The drain electrode of type；Second source electrode includes the doped region and of several the first doping types being arranged alternately along its length
The doped region of two doping types.
A kind of preferred embodiment of semiconductor device structure as the utility model, the field oxide with a thickness of 1000
Angstrom~20000 angstroms；First gate oxide with a thickness of 100 angstroms~2000 angstroms；Second gate oxide with a thickness of 100
Angstrom~2000 angstroms；The substrate material layer of second doping type with a thickness of 0.1 μm~10 μm.
A kind of preferred embodiment of semiconductor device structure as the utility model, the semiconductor device structure further include
The buried layer of the buried layer of first doping type, first doping type is located in the first well region of second doping type, and
Between first source electrode and first drain electrode.
A kind of preferred embodiment of semiconductor device structure as the utility model, the semiconductor device structure include N
The buried layer of layer first doping type, the first trap of the buried layer of N layers of first doping type along second doping type
The depth direction parallel interval in area is arranged；The dosage of Doped ions in first well region of second doping type is described the
N+1 times of the dosage of Doped ions in the buried layer of one doping type, wherein N is the integer more than or equal to 2.
A kind of preferred embodiment of semiconductor device structure as the utility model, the first doping type described in neighboring layers
Buried layer between spacing it is equal.
A kind of preferred embodiment of semiconductor device structure as the utility model, the first doping type described in neighboring layers
Buried layer between spacing differ.
A kind of preferred embodiment of semiconductor device structure as the utility model, in the buried layer of first doping type
The dosage of the second Doped ions in first well region of the dosage of the first Doped ions and second doping type and described the
The dosage of the second doping type ion is identical in second well region of two doping types.
As a kind of preferred embodiment of the utility model, the buried layer of first doping type along from first source electrode extremely
The direction of first drain electrode is divided into the sub- buried layer of multistage, has spacing between adjacent two sections of sub- buried layers.
As described above, the semiconductor device structure of the utility model, has the advantages that by polysilicon gate
The upper substrate material layer for forming the second doping type, and in the substrate of the first doping type and the substrate material of the second doping type
Form the device architecture of parallel relationship in layer, device architecture in the first doping type substrate be located at the second doping type
Substrate material layer in device architecture share polysilicon gate, be equivalent to compared to traditional semiconductor devices introduce it is additional
Conductive channel can be effectively reduced under the premise of obtaining high voltage than conducting resistance, to break existing silicon pole
Limit.
Detailed description of the invention
Fig. 1 to Fig. 4 is shown as cutting for the exemplary semiconductor device structure of difference provided in the utility model embodiment one
Face structural schematic diagram.
Fig. 5 is shown as the flow chart of the preparation method of the semiconductor device structure provided in the utility model embodiment two.
Fig. 6 is shown as step 1) institute in the preparation method of the semiconductor device structure provided in the utility model embodiment two
Obtain the cross section structure schematic diagram of structure.
Fig. 7 is shown as step 2) institute in the preparation method of the semiconductor device structure provided in the utility model embodiment two
Obtain the cross section structure schematic diagram of structure.
Fig. 8 to Figure 13 is shown as walking in the preparation method of the semiconductor device structure provided in the utility model embodiment two
The cross section structure schematic diagram of rapid 3) resulting structures.
Figure 14 is shown as step 4) in the preparation method of the semiconductor device structure provided in the utility model embodiment two
The cross section structure schematic diagram of resulting structures.
Figure 15 is shown as step 5) in the preparation method of the semiconductor device structure provided in the utility model embodiment two
The cross section structure schematic diagram of resulting structures.
Figure 16 is shown as step 6) in the preparation method of the semiconductor device structure provided in the utility model embodiment two
The cross section structure schematic diagram of resulting structures.
Figure 17 is shown as step 7) in the preparation method of the semiconductor device structure provided in the utility model embodiment two
The cross section structure schematic diagram of resulting structures.
Figure 18 is shown as step 8) in the preparation method of the semiconductor device structure provided in the utility model embodiment two
The cross section structure schematic diagram of resulting structures.
Figure 19 is shown as the overlooking structure diagram of Figure 18.
Figure 20 to Figure 22 is shown as in the preparation method of the semiconductor device structure provided in the utility model embodiment two
The cross section structure schematic diagram of step 9) resulting structures.
Component label instructions
The substrate of 10 first doping types
First well region of 11 second doping types
12 first gate oxides
13 polysilicon gates
14 second gate oxides
The substrate material layer of 15 second doping types
Second well region of 16 second doping types
17 first drain electrodes
18 second drain electrodes
19 first source electrodes
20 second source electrodes
The doped region of 201 first doping types
The doped region of 202 second doping types
The body area of 21 first doping types
22 field oxides
The well region of 23 first doping types
The heavily doped region of 24 first doping types
25 dielectric layers
251 openings
26 drain electrodes
27 source electrodes
The buried layer of 28 first doping types
281 sub- buried layers
S1~S9 step
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Fig. 1 to Figure 22 is please referred to it should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the utility model provides a kind of semiconductor device structure, the semiconductor device structure includes:
The substrate 10 of one doping type；First well region 11 of the first well region 11 of the second doping type, second doping type is located at
In the substrate 10 of first doping type；First drain electrode 17, first drain electrode 17 are located at the of second doping type
In one well region 11；First source electrode 19, first source electrode 19 are located in the substrate 10 of first doping type；First gate oxidation
Layer 12, first gate oxide 12 is located at the upper surface of the substrate 10 of first doping type；Polysilicon gate 13, it is described
Polysilicon gate 13 is located at the upper surface of part first gate oxide 12；Second gate oxide 14, second gate oxidation
Layer 14 is located at the upper surface of upper surface and part first gate oxide 12 of the polysilicon gate 13；Second doping type
Substrate material layer 15, the substrate material layer 15 of second doping type is located at the upper surface of second gate oxide 14；
Second well region 16 of the second doping type, the second well region 16 of second doping type are located at the lining of second doping type
In bottom material layer 15；Second drain electrode 18, second drain electrode 18 are located in the substrate material layer 15 of second doping type, and
Positioned at the side of the second well region 16 of second doping type；Second drain electrode 18 is shorted with first drain electrode 17；The
Two source electrodes 20, second source electrode 20 are located in the substrate material layer 15 of second doping type, and are located at described second and mix
Second well region 16 of miscellany type is away from the side of second drain electrode 18；Second source electrode 20 and first source electrode 19 are short
It connects；The body area 21 of first doping type, the body area 21 of first doping type are located at the substrate material of second doping type
In the bed of material 15, and between second source electrode 20 and the second well region 16 of second doping type.
As an example, first doping type can be p-type, then second doping type can be N-type.
As an example, first doping type may be N-type, then second doping type can be p-type.
As an example, the substrate 10 of first doping type may include but be not limited only to silicon substrate.
As an example, the first well region 11 of second doping type can pass through ion implanting and high temperature knot technique shape
At the ion implantation dosage in the first well region 11 of second doping type can be 1 × 1012/cm2~8 × 1012/cm2,
The junction depth of first well region 11 of second doping type can be 1 micron~20 microns.
As an example, the thickness of first gate oxide 12 and second gate oxide 14 can be according to actual needs
It is set, the thickness of first gate oxide 12 and second gate oxide 14 is too thin to will lead to the semiconductor devices
Not enough, and the thickness of first gate oxide 12 and second gate oxide 14 is too thick will lead to threshold value for the pressure resistance of structure
Voltage Vth is too high；Preferably, in the present embodiment, the thickness of first gate oxide 12 can be 100 angstroms~2000 angstroms；Institute
The thickness for stating the second gate oxide 14 can be 100 angstroms~2000 angstroms.
As an example, the material of the substrate material layer 15 of second doping type can with for but be not limited only to carry out
Monocrystalline silicon or polysilicon after two doping type ion dopings.
As an example, the thickness of the substrate material layer 15 of second doping type can be 0.1 micron~10 microns.
It should be noted that not illustrating the label of the substrate material layer 15 of second doping type, Fig. 1 in Fig. 1
Described in the first well region 16 of the second doping type, the body area 21 of first doping type, second drain electrode 18 and described
Region where second source electrode 20 collectively forms the corresponding region of substrate material layer 15 of second doping type.Described first
The body area 21 of doping type, second drain electrode 18 and second source electrode 20 are to pass through the substrate in second doping type
Ion implanting is carried out again in material layer 15 and is formed.
As an example, the doping concentration of the second well region 16 of second doping type can be set according to actual needs
It is fixed, it is preferable that in the present embodiment, the doping concentration of the second well region 16 of second doping type can be 1 × 1014/cm3It arrives
1×1016/cm3。
As an example, please referring to Figure 19, second drain electrode 18 is the drain electrode of the second doping type；Second source electrode 20
The doped region of doped region 201 including several the first doping types being arranged alternately and the second doping type along its length
Domain 202.
As an example, the semiconductor device structure further includes field oxide 22, the field oxide 22 is located at described the
10 surface of substrate of one doping type, and be located at first doping type substrate 10 and first gate oxide 12 it
Between.
As an example, the semiconductor device structure further includes the well region 23 and the first doping type of the first doping type
Heavily doped region 24, wherein the well region 23 of first doping type, in the substrate 10 of first doping type；Institute
The first source electrode 19 is stated to be located in the well region 23 of first doping type；The heavily doped region 24 of first doping type is located at
In the well region 23 of first doping type, and it is shorted with 19 phase of the first source electrode；Specifically, first doping type
Heavily doped region 24 is located at 11 side of the first well region that first source electrode 19 deviates from first doping type.
As an example, the thickness of the field oxide 22 can be set according to actual needs, the field oxide 22
The too thick growth time that will lead to of thickness it is too long, the thickness of increased costs, the field oxide 22 is too thin, does not have field oxidation
The buffer action of layer；Preferably, in the present embodiment, the thickness of the field oxide 22 can be 1000 angstroms~20000 angstroms.
As an example, substrate material layer of the second well region 16 of second doping type as second doping type
15 drift region, the backgate substrate of the well region 23 of first doping type as the substrate 10 of first doping type, institute
State the backgate substrate of the body area 21 of the first doping type as the substrate material layer 15 of second doping type.
As an example, first drain electrode 17, first source electrode 19, second drain electrode 18, second source electrode 20
And the heavily doped region 24 of first doping type all can be heavily doped region, it is described first drain electrode 17, first source
Pole 19, second drain electrode 18, second source electrode 20 and first doping type heavily doped region 24 dopant dose
It can be 1 × 1015/cm2To 1 × 1016/cm2。
As an example, the semiconductor device structure further includes；Dielectric layer 25, drain electrode 26 and source electrode 27,
In, the dielectric layer 25 be located at the substrate material layer of second doping type upper surface and the exposed field oxide
Upper surface, the drain electrode 26 is located in the dielectric layer 25 and the upper surface of the dielectric layer 25, the drain electrode 26
First drain electrode 17 and second drain electrode 18 are shorted, i.e., described first drain electrode 17 is with second drain electrode 18 via described
Drain electrode 26 is connected；The source electrode 27 is located in the dielectric layer 25 and the upper surface of the dielectric layer 25, described
First source electrode 19 and second source electrode 20 are shorted by source electrode 27, i.e., described first source electrode 19 and second source electrode
20 are connected via the source electrode 27.
In another example, as shown in Fig. 2, the semiconductor device structure can also include the buried layer of the first doping type
28, the buried layer 28 of first doping type is located in the first well region 11 of second doping type, and is located at described first
Between source electrode 19 and first drain electrode 17.It is mixed by the way that described first is arranged in the second well region 23 of second doping type
The buried layer 28 of miscellany type, can be improved the doping concentration of the second well region 23 of second doping type, to reduce than conducting
Resistance (Ronsp).
In another example, as shown in figure 3, the semiconductor device structure further includes the buried layer of one layer of first doping type
28, the buried layer 28 of first doping type is divided into multistage along from first source electrode 19 to the direction of first drain electrode 17
Sub- buried layer 281 has spacing between adjacent two sections of sub- buried layers 281.By the way that the buried layer 28 of first doping type is divided
It is placed in the first well region 11 of second doping type to section, so that the semiconductor device structure obtains multi-peak surface electricity
Field distribution, and gather around there are two conductive channel；Compared with traditional semiconductor device structure, the junction of semiconductor device of the utility model
Structure possesses shorter drift region length and higher drift region concentration under the premise of obtaining identical pressure resistance, to have lower
Ratio conducting resistance.
In another example, described in the example as shown in figure 4, compared to semiconductor device structure described in Fig. 3
Semiconductor device structure includes the buried layer 28 of N layers of first doping type, and the buried layer 28 of N layers of first doping type is along institute
State the depth direction parallel interval arrangement of the first well region 11 of the second doping type；First well region 11 of second doping type
The dosage of interior doping type ion is N+1 times of the dosage of Doped ions in the buried layer 28 of first doping type, wherein
N is the integer more than or equal to 2.By the way that the buried layer 28 of N layers of first doping type is arranged, described second can be further improved
The doping concentration of second well region 23 of doping type, compares conducting resistance to further decrease.
As an example, the spacing between the buried layer 28 of the first doping type described in neighboring layers is equal, described in neighboring layers
Spacing between the buried layer 28 of first doping type can not also wait.
As an example, the doping concentration of each section of sub- buried layer 281 can in the buried layer 28 of the first doping type of above layers
With identical, can also be different, it is preferable that in the present embodiment, the doping concentration of each section of sub- buried layer 281 is not exactly the same；Tool
Body, from left to right (i.e. from first drain electrode 17 to first source electrode 19), the doping concentration of each section of sub- buried layer 281
Can also can alternately it be changed with change of gradient, it can be with random variation.
As an example, each section of sub- buried layer 281 being divided into the buried layer 28 of the first doping type described in above layers
Width may be the same or different；Preferably, each section of institute being divided into the buried layer 28 of this layer of first doping type
State the of different size of sub- buried layer 281；It is further preferable that in the present embodiment, from first drain electrode 17 to first source electrode 19,
The width of each section of sub- buried layer 281 is gradually reduced in the buried layer 28 of each layer first doping type.Certainly, in other examples
In, from first drain electrode 17 to first source electrode 19, each section of son in the buried layer 28 of each layer first doping type
The width of buried layer 281 can also be gradually increased.
" the width of each section of sub- buried layer 281 in the buried layer 28 of first doping type it should be noted that so-called
Degree " refers to along the size from first drain electrode 17 to 19 direction of the first source electrode.
As an example, sub- 281 number of segment of buried layer that the buried layer 28 of each layer first doping type is divided can basis
Actual needs is set, it is preferable that in the present embodiment, the buried layer 28 of each layer first doping type is leaked along from described first
The direction of pole 17 to first source electrode 19 is divided into 2~10 sections.
As an example, in the buried layer 28 of each layer first doping type, between the adjacent each section of sub- buried layer 281 between
Away from can be equal, can not also wait.In the buried layer 28 of each layer first doping type, the adjacent each section of sub- buried layer 281 it
Between spacing can be set according to actual needs, it is preferable that in the present embodiment, the buried layer of each layer first doping type
In 28, the spacing between the adjacent each section of sub- buried layer 281 is less than or equal to 3 μm.
It certainly, in other examples, can also be on the basis of semiconductor device structure as shown in Figure 2 by described first
The number of plies of the buried layer 28 of doping type is set as N layers by one layer.
As an example, the accumulated dose of the first Doped ions and second doping in the buried layer 28 of first doping type
Second mixes in the dosage of the second Doped ions in first well region 11 of type and the second well region 16 of second doping type
The dosage of miscellaneous types of ion is identical.
The semiconductor device structure of the utility model is suitable for the application of 20V~1500V, by the length for changing drift region
Different pressure-resistant demands may be implemented in Ldrift, and the length Ldrift's of drift region may range from 1 micron~200 microns.
The utility model by forming the substrate material layer 15 of second doping type on the polysilicon gate 13,
And in formation parallel relationship in the substrate material layer 15 of the substrate 10 of first doping type and second doping type
Device architecture, the device architecture in the first doping type substrate 10 and the substrate material positioned at second doping type
Device architecture in the bed of material 15 shares the polysilicon gate 13, is equivalent to and is introduced additionally compared to traditional semiconductor devices
Conductive channel can be effectively reduced under the premise of obtaining high voltage than conducting resistance, to break existing silicon pole
Limit.
Embodiment two
Referring to Fig. 5, the utility model also provides a kind of production method of semiconductor device structure, the semiconductor devices
The preparation method of structure includes the following steps:
1) substrate of the first doping type is provided；
2) the first well region of the second doping type is formed in the substrate of the first doping type of Yu Suoshu；
3) the first gate oxide is formed on the substrate surface of the first doping type of Yu Suoshu；
4) polysilicon gate is formed in the upper surface of part first gate oxide；
5) upper surface of Yu Suoshu polysilicon gate and the upper surface of barish first gate oxide form the
Two gate oxides, second gate oxide cover the polysilicon gate；
6) upper surface of the second gate oxide of Yu Suoshu forms the substrate material layer of the second doping type；
7) the body area of the first doping type is formed in the substrate material layer of the second doping type of Yu Suoshu；
8) the first drain electrode, the substrate of the first doping type of Yu Suoshu are formed in the first well region of the second doping type of Yu Suoshu
The first source electrode of interior formation, and in the second drain electrode of formation and the second source electrode in the substrate material layer of second doping type, wherein
Second source electrode and first source electrode are respectively positioned on the same side in the body area of first doping type, second drain electrode with
The body area that first drain electrode is respectively positioned on first doping type deviates from the side of second source electrode, and second drain electrode
There is spacing between the body area of first doping type, in the body area of second drain electrode and first doping type
Between form the second well region of the second doping type；
9) first drain electrode and second drain electrode are shorted, and first source electrode and second source electrode is short
It connects.
In step 1), S1 step and Fig. 6 in Fig. 5 are please referred to, the substrate 10 of the first doping type is provided.
As an example, providing a substrate first, the first doping is then injected in the substrate by ion implantation technology
The ion of type is to form the substrate 10 of first doping type.
As an example, the substrate 10 of first doping type may include but be not limited only to silicon substrate.
As an example, first doping type can be p-type, or N-type.It should be noted that described first
When doping type is p-type, subsequent the second doping type mentioned is N-type；It is subsequent to mention when first doping type is N-type
The second doping type be p-type.
In step 2), S2 step and Fig. 7 in Fig. 5 are please referred to, is formed in the substrate 10 of the first doping type of Yu Suoshu
First well region 11 of the second doping type.
As an example, in the first well region 11 for forming second doping type in the substrate 10 of first doping type
Include the following steps:
2-1) using ion implantation technology injected in the substrate 10 of first doping type the second doping type from
Son, the dosage of ion implanting are 1 × 1012/cm2~8 × 1012/cm2；
The first well region 11 of second doping type, the second doping class of formation 2-2) are formed by high temperature knot
The junction depth of first well region 11 of type is 1 μm -20 μm.
The is formed as an example, can also be included in after the step 2) in the first well region 11 of second doping type
The step of buried layer 28 of one doping type.Specifically, can (the patterned mask layer schedules according to patterned mask layer
The shape of the buried layer 28 of first doping type and position out) using ion implantation technology the of second doping type
The buried layer 28 of first doping type is formed in one well region 11, the dosage of ion implanting can be 1 × 1012/cm2To 8 ×
1012/cm2.It, can be with by the way that the buried layer 28 of first doping type is arranged in the first well region 11 of second doping type
The doping concentration of the second well region 23 of second doping type is improved, to reduce than conducting resistance (Ronsp).
In one example, the buried layer 28 of first doping type of formation can be one layer, and the first doping class
The buried layer 28 of type is uninterrupted continuous structure, as shown in Figure 8.
In another example, the buried layer 28 of first doping type of formation can be one layer, and first doping
The buried layer 27 of type is divided into the sub- buried layer 271 of multistage along from the source electrode 26 to the direction of the drain electrode 27, described in adjacent two sections
There is spacing, as shown in Figure 9 between sub- buried layer 271.It crosses and 28 piecewise of buried layer of first doping type is placed in described
In first well region 11 of two doping types, so that the semiconductor device structure obtains multi-peak surface electric field distribution, and possess
Two conductive channels；Compared with traditional semiconductor device structure, the semiconductor device structure of the utility model is identical in acquisition
Under the premise of pressure resistance, possess shorter drift region length and higher drift region concentration, to compare conducting resistance with lower.
In another example, the buried layer 28 of first doping type of formation can be N layers, N layers of first doping
The buried layer 28 of type along the first well region 11 of second doping type depth direction parallel interval arrange, wherein N be greater than
Integer equal to 2.In the example, the buried layer 28 of each layer first doping type can be uninterrupted continuous structure, can also be with
It is divided into the structure of the sub- buried layer 271 of multistage to the direction of the drain electrode 27 from the source electrode 26 for edge, as shown in Figure 10.Described half
When conductor device structure includes the buried layer 28 of N layers of first doping type, in the first well region 11 of second doping type
The dosage of doping type ion be N+1 times of dosage of Doped ions in the buried layer 28 of first doping type, wherein N
For the integer more than or equal to 2.By the way that the buried layer 28 of N layers of first doping type is arranged, described second can be further improved
The doping concentration of first well region 11 of doping type, compares conducting resistance to further decrease.
As an example, the first doping type described in neighboring layers buries when the buried layer 28 of first doping type is N layers
Spacing between layer 28 is equal, and the spacing between the buried layer 28 of the first doping type described in neighboring layers can not also wait.
As an example, the doping concentration of each section of sub- buried layer 281 can in the buried layer 28 of the first doping type of above layers
With identical, can also be different, it is preferable that in the present embodiment, the doping concentration of each section of sub- buried layer 281 is not exactly the same；Tool
Body, from left to right (i.e. from first drain electrode 17 being subsequently formed to first source electrode 19), each section of sub- buried layer 281
Doping concentration can with change of gradient, can also alternately change, can be with random variation.
As an example, each section of sub- buried layer 281 being divided into the buried layer 28 of the first doping type described in above layers
Width may be the same or different；Preferably, each section of institute being divided into the buried layer 28 of this layer of first doping type
State the of different size of sub- buried layer 281；It is further preferable that in the present embodiment, first drain electrode 17 that is subsequently formed certainly is to described
First source electrode 19, the width of each section of sub- buried layer 281 is gradually reduced in the buried layer 28 of each layer first doping type.When
So, in other examples, first drain electrode 17 being subsequently formed certainly to first source electrode 19, each layer described first adulterates class
The width of each section of sub- buried layer 281 can also be gradually increased in the buried layer 28 of type.
" the width of each section of sub- buried layer 281 in the buried layer 28 of first doping type it should be noted that so-called
Degree " refers to along the size from first drain electrode 17 being subsequently formed to 19 direction of the first source electrode.
As an example, sub- 281 number of segment of buried layer that the buried layer 28 of each layer first doping type is divided can basis
Actual needs set, it is preferable that in the present embodiment, the buried layer 28 of each layer first doping type along being subsequently formed certainly
First drain electrode 17 to the direction of first source electrode 19 is divided into 2~10 sections.
As an example, in the buried layer 28 of each layer first doping type, between the adjacent each section of sub- buried layer 281 between
Away from can be equal, can not also wait.In the buried layer 28 of each layer first doping type, the adjacent each section of sub- buried layer 281 it
Between spacing can be set according to actual needs, it is preferable that in the present embodiment, the buried layer of each layer first doping type
In 28, the spacing between the adjacent each section of sub- buried layer 281 is less than or equal to 3 μm.
As an example, further including forming field oxide 22 on 10 surface of substrate of first doping type after step 2)
The step of, as shown in figure 11.Specifically, can be using thermal oxidation method, physical vaporous deposition or chemical vapour deposition technique in institute
10 surface of substrate for stating the first doping type forms the field oxide 22, it is preferable that in the present embodiment, is existed using thermal oxidation method
10 surface of substrate of first doping type forms the field oxide 22.
As an example, the thickness of the field oxide 22 can be set according to actual needs, it is preferable that the present embodiment
In, the thickness of the field oxide 22 can be 1000 angstroms~20000 angstroms.
It should be noted that the field oxide 22 can after the buried layer 28 for forming first doping type shape
At can also be formed before the buried layer 28 for forming first doping type.
As an example, further including being formed in the substrate 10 of first doping type after forming the field oxide 22
The step of well region 23 of first doping type, as shown in figure 12.
In step 3), S3 step and Figure 13 in Fig. 5 are please referred to, on 10 surface of substrate of the first doping type of Yu Suoshu
Form the first gate oxide 12.
As an example, institute can be formed using thermal oxidation technology, physical gas-phase deposition or chemical vapor deposition process
State the first gate oxide 12.
As an example, the thickness of first gate oxide 12 can be set according to actual needs, it is preferable that this reality
It applies in example, the thickness of the gate oxide 13 can be 100 angstroms~2000 angstroms.
In step 4), S4 step and Figure 14 in Fig. 5 are please referred to, in the upper surface of part first gate oxide 12
Form polysilicon gate 13.
As an example, can be first using physical gas-phase deposition or chemical vapor deposition process in first gate oxidation
The upper surface of layer 12 deposits one layer of polysilicon layer, then uses lithographic etch process to etch the polysilicon layer described more to be formed
Polysilicon gate 13.
In step 5), S5 step and Figure 15 in Fig. 5, the upper surface and part of Yu Suoshu polysilicon gate 13 are please referred to
The upper surface of exposed first gate oxide 12 forms the second gate oxide 14, and second gate oxide 14 covers described
Polysilicon gate 13.
As an example, institute can be formed using thermal oxidation technology, physical gas-phase deposition or chemical vapor deposition process
State the second gate oxide 14.
As an example, the thickness of second gate oxide 14 can be set according to actual needs, it is preferable that this reality
It applies in example, the thickness of second gate oxide 14 can be 100 angstroms~3000 angstroms.
In step 6), S6 step and Figure 16 in Fig. 5 are please referred to, the upper surface of the second gate oxide of Yu Suoshu 14 is formed
The substrate material layer 15 of second doping type.
As an example, the material of the substrate material layer 15 of second doping type can be but be not limited only to carry out second
Monocrystalline silicon or polysilicon after doping type ion doping.
As an example, the thickness of the substrate material layer 15 of second doping type can be 0.1 micron~10 microns.
As an example, one layer of intrinsic substrate material layer can be formed prior to the upper surface of second gate oxide 14, so
Ion implantation technology is used to carry out ion implanting to the intrinsic substrate material layer to form the lining of second doping type afterwards
Bottom material layer 15.
As an example, in the present embodiment, in the substrate material layer 15 of second doping type the second doping type from
The doping concentration of son can be 1 × 1014/cm3To 1 × 1016/cm3。
In step 7), S7 step and Figure 17 in Fig. 5, the substrate material layer 15 of the second doping type of Yu Suoshu are please referred to
The interior body area 21 for forming the first doping type.
As an example, being mixed using ion implantation technology in injection first in the substrate material layer 15 of second doping type
The ion of miscellany type is to form the body area 21 of first doping type.
In step 8), S8 step and Figure 18 in Fig. 5 are please referred to, in the first well region 11 of the second doping type of Yu Suoshu
It is formed in the substrate 10 of first drain electrode the first doping type of 17, Yu Suoshu and forms the first source electrode 19, specifically, being mixed in described first
Form first source electrode 19 in the well region 23 of miscellany type, and in forming the in the substrate material layer 15 of second doping type
Two drain electrodes 18 and the second source electrode 20；Wherein, second source electrode 20 is respectively positioned on the first doping class with first source electrode 19
The same side in the area Xing Ti 21, second drain electrode 18 are respectively positioned on the body area of first doping type with first drain electrode 17
21 deviate from the side of second source electrode 20, and have between second drain electrode 18 and the body area 21 of first doping type
Spacing, to form the second trap of the second doping type between second drain electrode 18 and the body area 21 of first doping type
Area 16.
As an example, forming first drain electrode 17, second drain electrode 18, first source electrode using self-registered technology
19 and second source electrode.
Drift of second well region 16 of second doping type as the substrate material layer 15 of second doping type
Area.
As an example, further including in the first doping of formation class in the well region 23 of first doping type in step 8)
The step of heavily doped region 24 of type, the heavily doped region 24 of first doping type are shorted with 19 phase of the first source electrode,
And the heavily doped region 24 of first doping type is located at first that first source electrode 19 deviates from second doping type
The side of well region 11.
As an example, first drain electrode 17, first source electrode 19, second drain electrode 18, second source electrode 20
And the heavily doped region 24 of first doping type all can be heavily doped region, it is described first drain electrode 17, first source
Pole 19, second drain electrode 18, second source electrode 20 and first doping type heavily doped region 24 dopant dose
It can be 1 × 1015/cm2To 1 × 1016/cm2。
As an example, second drain electrode 18 is the drain electrode of the second doping type such as Figure 19；Second source electrode 20 is along length
Spending direction includes the doped region 201 of several the first doping types being arranged alternately and the doped region of the second doping type
202。
In step 9), the S9 step and Figure 20 to Figure 22 in Fig. 5 are please referred to, by first drain electrode 17 and described second
Drain electrode 18 is shorted, and first source electrode 19 and second source electrode 20 are shorted.
As an example, step 9) includes the following steps:
9-1) upper surface of the substrate material layer 15 of the second doping type of Yu Suoshu and the upper surface of the field oxide 22
Dielectric layer 25 is formed, as shown in figure 20；Specifically, can be formed using physical gas-phase deposition or chemical vapor deposition process
The dielectric layer 25；
9-2) be respectively formed in Yu Suoshu dielectric layer 25 with part it is described first drain electrode 17, part it is described second drain electrode 18,
The opening 251 that part first source electrode 19 and part second source electrode 20 are connected；
9-3) in correspond to it is described first drain electrode 17 and it is described second drain electrode 18 the opening 251 in and the dielectric layer
25 upper surface forms drain electrode 26, and first drain electrode 17 and second drain electrode 18 are shorted by the drain electrode 26；
In in the opening 251 for corresponding to first source electrode 19 and second source electrode 20 and the upper surface shape of the dielectric layer 25
At source electrode 27, first source electrode 19 and second source electrode 20 are shorted by the source electrode 27, as shown in figure 22；Tool
Body, it can be using physical vaporous deposition or chemical vapour deposition technique in corresponding to first drain electrode 17 and second leakage
In the opening 251 of pole 18, corresponding in the opening 251 of first source electrode 19 and second source electrode 20, it is described
The upper surface deposition of electrode material layer of dielectric layer 25 forms the drain electrode 26 and source electrode electricity by lithographic etch process
Pole 27.
In conclusion the utility model provides a kind of semiconductor device structure, the semiconductor device structure includes: first
The substrate of doping type；First well region of the second doping type, in the substrate of first doping type；First drain electrode,
In the first well region of second doping type；First source electrode, in the substrate of first doping type；The first grid
Oxide layer, positioned at the upper surface of substrate of first doping type；Polysilicon gate, positioned at part first gate oxide
Upper surface；Second gate oxide, positioned at the upper surface of the upper surface of the polysilicon gate and part first gate oxide；
The substrate material layer of second doping type, positioned at the upper surface of second gate oxide；Second well region of the second doping type,
In the substrate material layer of second doping type；Second drain electrode, positioned at the substrate material layer of second doping type
It is interior, and it is located at the side of the second well region of second doping type；Second drain electrode is shorted with first drain electrode；Second
Source electrode, in the substrate material layer of second doping type, and the second well region for being located at second doping type deviates from
The side of second drain electrode；Second source electrode with described first source electrode are shorted；The body area of first doping type is located at described
In the substrate material layer of second doping type, and be located at second source electrode and second doping type the second well region it
Between.The utility model on polysilicon gate by forming the substrate material layer of the second doping type, and in the first doping type
Substrate and the second doping type substrate material layer in formed parallel relationship device architecture, be located at the first doping type substrate
Interior device architecture shares polysilicon gate with the device architecture in the substrate material layer for being located at the second doping type, compared to biography
The semiconductor devices of system, which is equivalent to, introduces additional conductive channel, and under the premise of obtaining high voltage, ratio can be effectively reduced
Conducting resistance, to break the existing silicon limit.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (12)
1. a kind of semiconductor device structure, which is characterized in that the semiconductor device structure includes:
The substrate of first doping type；
First well region of the second doping type, in the substrate of first doping type；
First drain electrode, in the first well region of second doping type；
First source electrode, in the substrate of first doping type；
First gate oxide, positioned at the upper surface of substrate of first doping type；
Polysilicon gate, positioned at the upper surface of part first gate oxide；
Second gate oxide, positioned at the upper surface of the upper surface of the polysilicon gate and part first gate oxide；
The substrate material layer of second doping type, positioned at the upper surface of second gate oxide；
Second well region of the second doping type, in the substrate material layer of second doping type；
Second drain electrode in the substrate material layer of second doping type, and is located at the second of second doping type
The side of well region；Second drain electrode is shorted with first drain electrode；
Second source electrode in the substrate material layer of second doping type, and is located at the second of second doping type
Well region is away from the side of second drain electrode；Second source electrode with described first source electrode are shorted；
The body area of first doping type in the substrate material layer of second doping type, and is located at second source electrode
Between the second well region of second doping type.
2. semiconductor device structure according to claim 1, it is characterised in that: the semiconductor device structure further includes field
Oxide layer positioned at the substrate surface of first doping type, and is located at the substrate and described first of first doping type
Between gate oxide.
3. semiconductor device structure according to claim 2, it is characterised in that: the semiconductor device structure further include:
The well region of first doping type, in the substrate of first doping type；First source electrode is located at described first
In the well region of doping type；
The heavily doped region of first doping type, in the well region of first doping type, and with the first source electrode phase
It is shorted.
4. semiconductor device structure according to claim 2, it is characterised in that: the semiconductor device structure further includes；
Dielectric layer, positioned at the upper surface of the substrate material layer of second doping type and the upper table of the exposed field oxide
Face；
Drain electrode, in the dielectric layer and the upper surface of the dielectric layer, the drain electrode drain described first
It is shorted with second drain electrode；
Source electrode, in the dielectric layer and the upper surface of the dielectric layer, the source electrode is by first source electrode
Source electrode are shorted with described second.
5. semiconductor device structure according to claim 1, it is characterised in that: second drain electrode is the second doping type
Drain electrode；Second source electrode includes the doped region and second of several the first doping types being arranged alternately along its length
The doped region of doping type.
6. semiconductor device structure according to claim 2, it is characterised in that: the field oxide with a thickness of 1000 angstroms
~20000 angstroms；First gate oxide with a thickness of 100 angstroms~2000 angstroms；Second gate oxide with a thickness of 100 angstroms
~2000 angstroms；The substrate material layer of second doping type with a thickness of 0.1 μm~10 μm.
7. semiconductor device structure according to claim 1, it is characterised in that: the semiconductor device structure further includes
The buried layer of the buried layer of one doping type, first doping type is located in the first well region of second doping type, and position
Between first source electrode and first drain electrode.
8. semiconductor device structure according to claim 7, it is characterised in that: the semiconductor device structure includes N layers
The buried layer of first doping type, the first well region of the buried layer of N layers of first doping type along second doping type
Depth direction parallel interval arrangement；The dosage of Doped ions in first well region of second doping type is described first
N+1 times of the dosage of Doped ions in the buried layer of doping type, wherein N is the integer more than or equal to 2.
9. semiconductor device structure according to claim 8, it is characterised in that: the first doping type described in neighboring layers
Spacing between buried layer is equal.
10. semiconductor device structure according to claim 8, it is characterised in that: the first doping type described in neighboring layers
Buried layer between spacing differ.
11. semiconductor device structure according to claim 7, it is characterised in that: in the buried layer of first doping type
The dosage of the second Doped ions in first well region of the dosage of the first Doped ions and second doping type and described the
The dosage of the second doping type ion is identical in second well region of two doping types.
12. semiconductor device structure according to any one of claims 7 to 11, it is characterised in that: first doping
The buried layer of type is divided into the sub- buried layer of multistage, adjacent two sections of sons along from first source electrode to the direction of first drain electrode
There is spacing between buried layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821811099.3U CN209487516U (en) | 2018-11-05 | 2018-11-05 | Semiconductor device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821811099.3U CN209487516U (en) | 2018-11-05 | 2018-11-05 | Semiconductor device structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209487516U true CN209487516U (en) | 2019-10-11 |
Family
ID=68114889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821811099.3U Active CN209487516U (en) | 2018-11-05 | 2018-11-05 | Semiconductor device structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209487516U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146287A (en) * | 2018-11-05 | 2020-05-12 | 上海晶丰明源半导体股份有限公司 | Semiconductor device structure and preparation method thereof |
-
2018
- 2018-11-05 CN CN201821811099.3U patent/CN209487516U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111146287A (en) * | 2018-11-05 | 2020-05-12 | 上海晶丰明源半导体股份有限公司 | Semiconductor device structure and preparation method thereof |
| CN111146287B (en) * | 2018-11-05 | 2024-08-23 | 上海晶丰明源半导体股份有限公司 | Semiconductor device structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104992977B (en) | NLDMOS device and its manufacturing method | |
| CN104332494B (en) | A kind of igbt and its manufacturing method | |
| CN104051540B (en) | Super-junction device and its manufacturing method | |
| CN103681848B (en) | Metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| CN105070759A (en) | Nldmos device and manufacturing method thereof | |
| CN107482061A (en) | Superjunction devices and its manufacture method | |
| CN102610641B (en) | High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof | |
| CN107425046A (en) | A kind of LDMOS device and preparation method thereof | |
| CN102543738A (en) | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same | |
| CN106409883A (en) | High voltage LDMOS device and the manufacturing method thereof | |
| CN105914231B (en) | Charge storage type IGBT and its manufacturing method | |
| CN102709190B (en) | LDMOS (Laterally Diffused Metal Oxide Semiconductor) field effect transistor and manufacturing method thereof | |
| CN209487516U (en) | Semiconductor device structure | |
| CN105977308B (en) | Super barrier rectifier device and preparation method thereof | |
| CN116759439A (en) | Super-junction VDMOS device, preparation method thereof and electronic equipment | |
| CN106409675A (en) | Production method for depletion mode power transistor | |
| CN208904024U (en) | Semiconductor device structure | |
| CN207896095U (en) | A kind of binary channels varying doping LDMOS device | |
| CN104037206B (en) | Super-junction device and manufacturing method thereof | |
| CN102891088A (en) | Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device | |
| CN110212015A (en) | Super junction device structure and preparation method thereof | |
| CN111146287B (en) | Semiconductor device structure and preparation method thereof | |
| CN109698228A (en) | A kind of super-junction device and manufacturing method | |
| CN104617147B (en) | A kind of trench MOSFET structure and preparation method thereof | |
| CN103199110B (en) | A kind of NLDMOS device and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |