CN209487505U - A kind of optical integrated device structure based on strain - Google Patents

Abstract

The optical integrated device structure based on strain that the utility model relates to a kind of.The structure includes: silicon substrate (001)；LED (10), waveguide (20), detector (30), NMOS device (40) and PMOS device (50), are successively horizontally installed on the silicon substrate (001)；Two first grooves (0021), be arranged on the silicon substrate (001), and be located at the LED (10), waveguide (20), detector (30) two sides；First groove (0022) is arranged in the centre of the NMOS device (40) and the PMOS device (50)；Two third grooves (016) are arranged in the two sides of the waveguide (20)；Stress silicon nitride film is arranged in the waveguide (20), the detector (30), the NMOS device (40) and the PMOS device (50).

Description

A kind of optical integrated device structure based on strain

Technical field

The utility model relates to technical field of integrated circuits, in particular to a kind of optical integrated device structure based on strain.

Background technique

Photodetector is a kind of light-detecting device made of the photoconductive effect using semiconductor material.Photodetector There is extensive use in military and national economy every field.It is mainly used for radionetric survey and spy in visible light or near infrared band Survey, industry automatic control, Photometric Measurement etc.；It is mainly used for the side such as missile guidance, infrared thermal imaging, infrared remote sensing in infrared band Face.

With the development of large scale integrated circuit technology, device feature size constantly reduces, and collects increasing on a large scale, letter Breath processing capacity constantly enhances, and how to realize being integrated into for photoelectric detector i.e. optical device and MOS device on a single chip For urgent problem to be solved.

Utility model content

Therefore, it to solve technological deficiency and deficiency of the existing technology, is based on answering the utility model proposes a kind of The optical integrated device structure of change.

Specifically, a kind of optical integrated device structure based on strain that the utility model one embodiment proposes, comprising:

Silicon substrate 001；

LED10, waveguide 20, detector 30, NMOS device 40 and PMOS device 50 are successively horizontally installed on the silicon lining On bottom 001；

Two first grooves 0021 are arranged on the silicon substrate 001, and are located at the LED10, waveguide 20, detector 30 two sides；

The centre of the NMOS device 40 and the PMOS device 50 is arranged in second groove 0022；

The two sides of the waveguide 20 are arranged in two third grooves 016；

Stress silicon nitride film is arranged in the waveguide 20, the detector 30, the NMOS device 40 and the PMOS On device 50.

In one embodiment of the utility model, the LED10 includes the third epitaxial layer 008, first set gradually Ge layer 009 and first step part 10¹⁶cm^-(。

In one embodiment of the utility model, the first step part include set gradually it is first Ge layers intrinsic 010, intrinsic GeSn alloy layer 011, the second intrinsic Ge layer 012, the 2nd Ge layer 013, N-shaped Si layer 014 and the second oxide layer 015.

In one embodiment of the utility model, the detector 30 includes the third epitaxial layer set gradually 008, the first Ge layer 009 and second step part.

In one embodiment of the utility model, the second step part include set gradually it is described first intrinsic Ge layer 010, the intrinsic GeSn alloy layer 011, the second intrinsic Ge layer 012, the 2nd Ge layer 013, the N-shaped Si Layer 014 and second oxide layer 015.

The beneficial effects of the utility model are as follows:

LED, waveguide, detector, NMOS device and PMOS device are integrated on one piece of substrate by the utility model, are passed through Stress silicon nitride film introduces stress, on the basis of improving device performance, device architecture novelty good compatibility, device integration Height, process costs are low.

Through the following detailed description with reference to the accompanying drawings, the other aspects and feature of the utility model become obvious.But it answers When knowing, which is only the purpose design explained, not as the restriction of the scope of the utility model, this is because its It should refer to appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they are only Try hard to conceptually illustrate structure and process described herein.

Detailed description of the invention

Below in conjunction with attached drawing, specific embodiment of the present utility model is described in detail.

Fig. 1 is a kind of optical integrated device structural schematic diagram based on strain provided by the embodiment of the utility model；

Fig. 2 is another optical integrated device structural schematic diagram based on strain provided by the embodiment of the utility model；

Fig. 3 a~Fig. 3 u is a kind of preparation process of the optical integrated device based on strain provided by the embodiment of the utility model Schematic diagram；

Fig. 4 a is the optical integrated device preparation process shape based on strain shown in Fig. 3 n provided by the embodiment of the utility model At device top view；

Fig. 4 b is the optical integrated device preparation process shape based on strain shown in Fig. 3 o provided by the embodiment of the utility model At device top view；

Fig. 4 c is the optical integrated device preparation process shape based on strain shown in Fig. 3 p provided by the embodiment of the utility model At device top view；

Fig. 4 d is the optical integrated device preparation process shape based on strain shown in Fig. 3 q provided by the embodiment of the utility model At device top view；

Fig. 4 e is the optical integrated device preparation process shape based on strain shown in Fig. 3 r provided by the embodiment of the utility model At device top view；

Fig. 4 f is the optical integrated device preparation process shape based on strain shown in Fig. 3 s provided by the embodiment of the utility model At device top view；

Fig. 4 g is the optical integrated device preparation process shape based on strain shown in Fig. 3 t provided by the embodiment of the utility model At device top view；

Fig. 4 h is the optical integrated device preparation process shape based on strain shown in Fig. 3 u provided by the embodiment of the utility model At device top view；

Fig. 5 a~5c is the schematic top plan view of three kinds of tapered transmission lines provided by the embodiment of the utility model；

Fig. 6 is under the different wave length of three kinds of linear type provided by the embodiment of the utility model, convex, concave tapered transmission lines Transmission schematic diagram；

Fig. 7 is different waves of the tapered transmission line provided by the embodiment of the utility model under 5 μm, 10 μm, 15 μm of three kinds of length Long transmission schematic diagram；

Fig. 8 is transmission schematic diagram of the separation layer provided by the embodiment of the utility model under different-thickness；

Fig. 9 is the transmission schematic diagram of coating provided by the embodiment of the utility model at different wavelengths.

Specific embodiment

To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, with reference to the accompanying drawing to this The specific embodiment of utility model is described in detail.

Embodiment one

Referring to Figure 1, Fig. 1 is a kind of optical integrated device structural representation based on strain provided by the embodiment of the utility model Figure.The device architecture includes: silicon substrate 001；LED10, waveguide 20, detector 30, NMOS device 40 and PMOS device 50, It is successively horizontally installed on the silicon substrate 001；Two first grooves 0021 are arranged on the silicon substrate 001, and are located at institute State the two sides of LED10, waveguide 20, detector 30；Second groove 0022 is arranged in the NMOS device 40 and the PMOS device The centre of part 50；The two sides of the waveguide 20 are arranged in two third grooves 016；Stress silicon nitride film is arranged in the waveguide 20, in the detector 30, the NMOS device 40 and the PMOS device 50.

LED, waveguide, detector, NMOS device and PMOS device are integrated on one piece of substrate by the present embodiment, and introducing is answered Production forms the optical integrated device based on strain after power, on the basis of improving device performance, device architecture novelty good compatibility, Device integration is high, process costs are low.

Embodiment two

Fig. 2 is referred to, Fig. 2 is that another optical integrated device structure based on strain provided by the embodiment of the utility model is shown It is intended to.On the basis of the above embodiments, the present embodiment by the utility model proposes the optical integrated device knot based on strain Structure describes in detail.

The LED10 includes the third epitaxial layer 008 set gradually, the first Ge layer 009 and first step part 10¹⁶cm^-(。

The first step part includes the first intrinsic Ge layer 010, the intrinsic GeSn alloy layer 011, second set gradually Intrinsic Ge layer 012, the 2nd Ge layer 013, N-shaped Si layer 014 and the second oxide layer 015.

The detector 30 includes the third epitaxial layer 008 set gradually, the first Ge layer 009 and second Exponent part.

The second step part includes the described first intrinsic Ge layer 010, the intrinsic GeSn alloy layer set gradually 011, the described second intrinsic Ge layer 012, the 2nd Ge layer 013, the N-shaped Si layer 014 and second oxide layer 015.

The waveguide 20 includes the described first intrinsic Ge layer 010, the intrinsic GeSn alloy layer 011 and coating 017.

The first intrinsic Ge layer 010 with a thickness of 40~50nm, the intrinsic GeSn alloy layer 011 with a thickness of 250nm, Sn component content are 8%, and the second intrinsic Ge layer 012 is with a thickness of 40~50nm, 013 thickness of the 2nd Ge layer For 100nm, doping concentration 3*10¹⁹cm^-(, the N-shaped Si layer 014 is with a thickness of 100nm, doping concentration 10²⁰cm^-(, described Dioxide layer 015 is with a thickness of 10nm.

The NMOS device 40 includes the first extension sub-regions 0024A, the second source region 007A, the second drain region 007B, the Two polysilicon gate 018B and second electrode 019B.

PMOS device 50 includes n trap 005, the first source region 006A, the first drain region 006B, the first polysilicon gate 018A and first Electrode 019A.

Stress silicon nitride film includes: compression silicon nitride film 020, is arranged in the waveguide 20 and PMOS device 50；? Stress silicon nitride film 021 is arranged on the detector 30 and the NMOS device.

Embodiment three

Referring to Fig. 3 a~Fig. 3 u, Fig. 3 a~Fig. 3 u is a kind of light collection based on strain provided by the embodiment of the utility model At the preparation process schematic diagram of device, on the basis of the above embodiments, the present embodiment will be in more detail to the utility model The preparation process of the optical integrated device based on strain proposed describes in detail.This method comprises:

S101, as shown in Figure 3a, chooses silicon substrate 001, p-type Si epitaxial layer 002 is grown on silicon substrate 001, outside p-type Si The doping concentration for prolonging layer 002 is 10¹⁶cm^-(；

S102, as shown in Figure 3b, using dry etch process etch silicon epitaxy layer 002, formed first groove 0021 and Second groove 0022, wherein silicon epitaxy layer 002 is isolated into outside the first epitaxial layer region 0023 and second by first groove 0021 Prolong layer region 0024, further, the second epitaxial layer region 0024 is isolated into the first extension sub-regions by second groove 0022 0024A and the second extension sub-regions 0024B.At a temperature of 250~450 DEG C, enhance chemical gas using low temperature plasma Mutually deposit (LPCVD) technique is in first groove 0021, the first epitaxial layer region 0023, the first extension sub-regions 0024A, second The first oxide layer 003 is deposited in extension sub-regions 0024B and second groove 0022, further, which can be SiO₂Layer.Wherein, the first oxide layer 003 with a thickness of 10~20nm, i.e., first groove 0021, the first epitaxial layer region 0023, First extension sub-regions 0024A, the second extension sub-regions 0024B and and 0022 surface of second groove first oxidation Layer 003 with a thickness of 10~20nm.

S103, as shown in Figure 3c, in first groove 0021, second groove 0022, the first epitaxial layer region 0023 and the One layer of first photoresist 004A is coated in first oxide layer 003 of the one extension sub-regions surface 0024A.First photoresist 004A Material protection below can be got up, from ion implanting, the region high energy foreign ion that is not covered by photoresist can be with The upper surface of penetrable material is doped.

At cryogenic temperatures, temperature can be chosen for 200~300 DEG C, to the second extension sub-regions 0024B carry out P from Son injection, forms with a thickness of 400nm, concentration 10^#6cm^-(N trap 005.

S104, as shown in Figure 3d, 003 middle section of the first oxide layer painting on the second extension sub-regions surface 0024B The second photoresist 004B is covered, at a temperature of 200~300 DEG C, B ion implanting twice is carried out to n trap 005, it is equal to form doping concentration It is 10²⁰cm^-(The first source region 006A and the first drain region 006B；

S105, as shown in Figure 3 e, in the first oxide layer 003 on the first source region 006A and the first drain region 006B respectively Coat one layer of third photoresist 004C and the 4th photoresist 004D.The first extension sub-regions are etched using etching technics The first photoresist 004A in the first oxide layer 003 on 0024A retains the first oxygen on the first extension sub-regions 0024A Change middle section the first photoresist 004A on layer 003.At a temperature of 200~300 DEG C, to the first extension sub-regions 0024A It carries out P ion twice to inject, forming doping concentration is 10²⁰cm^-3The second source region 007A and the second drain region 007B.Then It anneals in short annealing (RTP) device.Quick annealing device can be rapidly reached 1000 DEG C or so of high temperature and in setting temperature Degree is kept for the several seconds, and this state is all extremely important for the diffusion and the diffusion of voltage input/drain impurity that prevent structure.

S106, as illustrated in figure 3f, the first photoresist 004A of removal, the second photoresist 004B, third photoresist 004C and 4th photoresist 004D.The first epitaxial layer region 0023 is etched using dry etch process, until retaining the silicon epitaxy layer of 300nm 002, form third epitaxial layer 008.

S107, as shown in figure 3g, at a temperature of 330 DEG C, using chemical gaseous phase deposition (CVD) technique in third epitaxial layer Epitaxial growth is on 008 with a thickness of 50nm, doping concentration 10²⁰cm^-(P++ doping the first Ge layer 009.

S108, as illustrated in figure 3h, at a temperature of 275~325 DEG C, thickness is grown using CVD technique on the first Ge layer 009 Degree is the first intrinsic Ge layer 010 of 40~50nm.

S109, as shown in figure 3i utilizes decompression CVD technique extension on the first intrinsic Ge layer 010 at a temperature of 350 DEG C Growth thickness is the intrinsic GeSn alloy layer 011 of 250nm, and control Sn component is 8%, achieves direct band gap.

S110, as shown in Fig. 3 j, at a temperature of 275~325 DEG C, using CVD technique on intrinsic GeSn alloy-layer 011 Epitaxial growth with a thickness of 40~50nm the second intrinsic Ge layer 012.

S111, as shown in figure 3k, at a temperature of 160 DEG C, utilizes the epitaxial growth on the second intrinsic Ge layer 012 of CVD technique With a thickness of 100nm, doping concentration 3*10^#9cm^-(N+ doping the 2nd Ge layer 013.

S112, as shown in Fig. 3 l, at a temperature of 275~325 DEG C, using CVD technique, extension is raw on the 2nd Ge layer 013 Length is with a thickness of 100nm, doping concentration 10²⁰cm^-(N++ doping N-shaped Si layer 014.

S113, as shown in figure 3m, the second oxide layer that growth thickness is 10nm on N-shaped Si layer 014 using LPCVD technique 015, wherein the second oxide layer 015 can be silicon dioxide layer (SiO₂)。

S114, as shown in Fig. 3 n, Fig. 4 a, Fig. 4 a be Fig. 3 n provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed.First with dry etch process, the first specified area is etched by HF Second oxide layer 015 and N-shaped Si layer 014, the 2nd Ge layer 013 and the second intrinsic Ge layer 012 in domain；Secondly it is using concentration ratio The HF:HNO of 1:2.5:10₍: CH₍The intrinsic GeSn alloy layer 011 and first that COOH etches the second specified region is Ge layers intrinsic 010, until being etched to the first Ge layer 009 forms LED10, waveguide 20, detector 30 and third groove 016.

Further, the intrinsic GeSn alloy layer 011 of taper among third groove 016 and the first intrinsic 010 region of Ge layer For waveguide 20, i.e. waveguide 20 is tapered transmission line；The stepped area of 016 two sides of third groove is respectively LED10 and detector 30.Tool Body, the first step part on third epitaxial layer 008, the first Ge layer 009 and the first Ge layer 009 forms LED10；Wherein, First step part is the first intrinsic Ge layer 010, intrinsic GeSn alloy layer 011, the second intrinsic Ge layer 012, the 2nd Ge layer 013, n The step part that type Si layer 014 and the second oxide layer 015 are formed.Third epitaxial layer 008, the first Ge layer 009 and the first Ge Second step part on layer 009 forms detector 30；Wherein, second step part is the first intrinsic Ge layer 010, intrinsic GeSn The stage portion that alloy-layer 011, the second intrinsic Ge layer 012, the 2nd Ge layer 013, N-shaped Si layer 014 and the second oxide layer 015 are formed Point.

It should be noted that the length of tapered transmission line is longer, the direction of propagation varying dimensions with regard to smaller, but be not Linearly increasing, with the increase of length, loss reduces just fewer and fewer therefore also just smaller on the influence of the transmission loss of light.

Fig. 5 a~5c is referred to, Fig. 5 a~5c is that the vertical view of three kinds of tapered transmission lines provided by the embodiment of the utility model is illustrated Figure.The not tapered transmission line of ipsilateral can be divided into three kinds of linear type, convex, concave structures.Tapered transmission line length L is longer, The varying dimensions of the direction of propagation are smaller, but be not it is linearly increasing, with the increase of length L, loss reduce it is just fewer and fewer, Therefore the transmission loss of light is influenced also just smaller.Wherein, linear type, convex, the selection of concave difference, the length L of tapered transmission line Also different.

Refer to Fig. 6, Fig. 6 be three kinds of linear type provided by the embodiment of the utility model, convex, concave tapered transmission lines not Transmission schematic diagram under co-wavelength.Linear type, convex, the concave transmission under phase co-wavelength are different.Wherein, side is concave The tapered transmission line transmission of structure is worst, and transmission loss is maximum；Side is the tapered transmission line transmission in the transmission of convex shape Preferably, transmission loss is relatively small；Side be linear structure tapered transmission line transmission and transmission loss degree all between Side is the tapered transmission line of concave structure and side structure is between the tapered transmission line of convex shape.

Preferably, it is convex shape best performance that tapered transmission line, which is side,.

Fig. 7 is referred to, Fig. 7 is tapered transmission line provided by the embodiment of the utility model in 5 μm, 10 μm, 15 μm of three kinds of length Under different wave length transmission schematic diagram.The longer transmission of wavelength is better.In the case where practical application allows, choose as far as possible Longer wavelength.Because photoelectric device design needs, wherein length L cannot be too long, and length L chooses 5 μm~15 μm mostly.

Preferably, the length L of tapered transmission line is 10um.

S115, as shown in Fig. 3 o, Fig. 4 b, Fig. 4 b be Fig. 3 o provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed, utilizes SiH₄And O₂The isolation of 20nm thickness is grown in third groove 016 Layer 0161, wherein separation layer 0161 can be SiO₂.Separation layer 0161 is etched using dry etch process, the isolation after etching 0161 thickness of layer is greater than the intrinsic GeSn alloy layer 011 of waveguide 20.Separation layer 0161 by active device and device for no reason at all carry out every From namely separation layer 0161 LED10, waveguide 20, detector 30 be isolated, and play the role of certain electric isolution, prevent Only both ends photoelectric device generates ghost effect.

SiO₂For separation layer shown in the transmission See Figure 8 under different-thickness, Fig. 8 is provided by the embodiment of the utility model Transmission analogous diagram of the separation layer under different-thickness, in Fig. 8 it can be seen from wavelength it is longer influenced by interface it is smaller；Base The SiO of this 20nm thickness₂Influence of the separation layer to optical transport is substantially consistent with when not having a separation layer, influences very little to entire optical transport Substantially it can be ignored；Work as SiO₂When separation layer gradually thickeies, transmissivity is gradually reduced, and increases identical thicker transmission Rate but reduces more.It therefore it can be concluded that, is not linear relationship between the thickness and transmission of separation layer, but with thickness The increase of degree, transmission reduce more.With the increase of thickness, SiO₂Scattering loss and reflection all increasing lead to coupling Loss is closed to increase.Wavelength is at 1.75 μm or so, no SiO₂Layer and 20nm thickness SiO₂Coupling between the device and waveguide of layer is imitated Rate is essentially 84%~85%, and coupling efficiency when SiO2 is with a thickness of 50nm is essentially 81%~82%.This illustrates SiO₂It is right What the loss influence between device and waveguide still be can not ignore.Further, the present embodiment is preferably isolated layer height and is 20nm。

S116, as shown in Fig. 3 p, Fig. 4 c, Fig. 4 c be Fig. 3 p provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed, grows coating on the intrinsic GeSn alloy layer 011 of waveguide 20 017, surface and 0161 flush of separation layer of coating 017.Further, coating 017 can be chosen for α-Si.Addition The case where coating can reduce coupling loss, this is coupled with optical fiber with device is almost the same, and opposite side wall design more can It is enough to reduce loss, therefore it is necessary to add coating.

Fig. 9 is referred to, Fig. 9 is the transmission signal of coating provided by the embodiment of the utility model at different wavelengths Figure.Transmission of the coating α-Si under any wavelength is all higher than intectate α-Si.Addition coating α-Si can reduce light Coupling loss between fine and device, therefore add coating α-Si.

Further, LED10, waveguide 20 and detector 30 collectively form optical device.

S117, as shown in Fig. 3 q, Fig. 4 d, Fig. 4 d be Fig. 3 q provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed prepares the first polysilicon in the first oxide layer 003 on n trap 005 Grid 018A；The second polysilicon gate 018B is prepared in the first oxide layer 003 on the first extension sub-regions 0024A.Specifically, Entire device is transferred to low-pressure chemical vapor phase deposition equipment, is 575 DEG C~650 DEG C in temperature, pressure is 0.2~1.0Torr's Under the conditions of, the gaseous mixture of silane and nitrogen that pure silane or content are 20%~30% is passed through into the process cavity of the equipment Body is decomposed by silane, the 003 surface deposition polysilicon of the first oxide layer on n trap 005, the first extension sub-regions 0024A Grid are respectively formed the first polysilicon gate 018A and the second polysilicon gate 018B.Further, the first polysilicon gate 018A and second Polysilicon gate 018B with a thickness of 50~60nm.

S118, as shown in Fig. 3 r, Fig. 4 e, Fig. 4 e be Fig. 3 r provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed, using electron beam evaporation process in the first source region 006A and the first drain region The upper growth thickness of 006B is that 70~80nm aluminium (Al) forms metal contact, falls specified region using etching technics selective etch Metal Al forms first electrode 019A；Growth thickness is 70~90nm aluminium on the second source region 007A and the second drain region 007B (Al) metal contact is formed, the metal Al in specified region is fallen using etching technics selective etch, forms second electrode 019B.

It is possible to further find out, the first extension sub-regions 0024A, the second source region 007A, the second drain region 007B, Two polysilicon gate 018B, second electrode 019B form NMOS device；N trap 005, the first source region 006A, the first drain region 006B, One polysilicon gate 018A, first electrode 019A form PMOS device.

NMOS device and PMOS device collectively form cmos device.

S119, as shown in Fig. 3 s, Fig. 4 f, Fig. 4 f be Fig. 3 s provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed, in PMOS device 50 and 20 surface of waveguide and surrounding growth thickness For the compression silicon nitride film 020 of 10~20nm, the compression silicon nitride that selective eating away specifies region is carved using etching technics Film 020.Specifically, at a temperature of 340~360 DEG C, using plasma-enhanced chemical vapor deposition process, in PMOS device 50 and 20 surface of waveguide and surrounding growth thickness be 10~20nm compression silicon nitride film 020.Plasma-enhancedization The process conditions for learning vapor deposition process are as follows: pressure 500mTorr, and the power in low frequency power source is 150W, and reaction gas is Silane (the SiH that flow-rate ratio is 2₄) and ammonia (NH₍).It should be noted that high-energy particle bombardment is introduced using low frequency power source, Lead to atom/ions binding or redistribution, i.e., so that silicon nitride film becomes that extension/expansion occurs with compressibility, thus Intrinsic compression is generated in silicon nitride film.Further, in the case that other process conditions are constant, reaction temperature is higher, is formed Silicon nitride film compression is bigger, and is in certain linear relationship.In the case where other process conditions are constant, reaction pressure is got over It is smaller to form silicon nitride film compression for height.In the case where other process conditions are constant, low frequency power is bigger, forms silicon nitride Membrane pressure stress is bigger.The compression and reaction temperature, reaction pressure, Frequency, reaction gas applied in compression silicon nitride film The relationship of body and bandwidth meets:

Tc=-1.0 × T-463.6；

Tc=1.03 × P-1363.5；

Tc=-0.7 × F-813.4；

Tc=24 × X²-167×X-560；

Tc=0.6+0.03 × Eg-0.02 × Eg²；Wherein, Tc indicates the compression applied in compression silicon nitride film, T Indicate reaction temperature, P indicates reaction pressure, and F indicates that Frequency, X indicate that reaction gas flow ratio, Eg indicate bandwidth.

S120, as shown in Fig. 3 t, Fig. 4 g, Fig. 4 g be Fig. 3 t provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed, in NMOS device 40 and 30 surface of detector and surrounding growth Stress silicon nitride film 021 carves the tensile stress silicon nitride film 021 that selective eating away specifies region using etching technics.Specifically, exist At a temperature of 240~280 DEG C, using plasma enhanced CVD technique, on 30 surface of NMOS device 40 and detector And surrounding growth thickness is the tensile stress silicon nitride film 021 of 10~20nm.Plasma-enhanced chemical vapor deposition process Process conditions it is as follows: pressure 1500mTorr, radio-frequency power 200W, reaction gas are that flow-rate ratio is 0.75 silane (SiH₄) and ammonia (NH₍).It should be noted that explorer portion wraps up the tensile stress silicon nitride film 021 of a thickness, film tool There is good consistency.Further, in the case where other process conditions are constant, reaction temperature is higher, forms silicon nitride film Tensile stress is bigger, and is in certain linear relationship.In the case where other process conditions are constant, reaction pressure is higher, forms nitrogen SiClx film tensile stress is bigger, and is in certain linear relationship.In the case where other process conditions are constant, radio-frequency power is bigger, It is bigger to form silicon nitride film tensile stress.The tensile stress and reaction temperature, reaction pressure, radio frequency function applied in tensile stress silicon nitride film The relationship of rate, reaction gas and forbidden bandwidth meets:

Ts=1.2 × T-34.1；

Ts=0.3 × P-28.5；

Ts=(- 2.48 × 10^-6)×R²+0.26×R+134.1；

Ts=-265.4 × X²+574.6×X+140.3；

Ts=0.6-0.1 × Eg；Wherein, Ts indicates that the tensile stress applied in tensile stress silicon nitride film, T indicate reaction temperature Degree, P indicate reaction pressure, and R indicates that radio-frequency power, X indicate that reaction gas flow ratio, Eg indicate bandwidth.

S121, as shown in Fig. 3 u, Fig. 4 h, Fig. 4 h be Fig. 3 u provided by the embodiment of the utility model shown in based on strain The device top view that optical integrated device preparation process is formed grows 10~20nm on the surface LED10 using electron beam evaporation process Thick aluminium (Al) forms metal contact, carves the metal Al that selective eating away specifies region using etching technics, forms electrode third Electrode 022A and the 4th electrode 022B is formed using tensile stress silicon nitride film 021 of the electron beam evaporation process on detector 30 Metal contact carves the metal Al that selective eating away specifies region using etching technics, forms the 5th electrode 022C and the 6th electrode 022D。

It should be noted that third electrode 022A is the positive electrode of LED10, the 4th electrode 022B is the negative electrode of LED10. 5th electrode 022C is the positive electrode of detector 30, and the 6th electrode 022D is the negative electrode of detector 30.

Need further exist for explanation, the basic structure of LED is a PN junction, and forward bias is minority carrier from knot Two sides injection, therefore near knot, there is the nonequilibrium carrier higher than equilibrium concentration, carrier occurs compound.In current-carrying In the recombination process of son, discharged along with energy.And the directly radiation between semiconductor direct bandgap conduction band bottom and top of valence band is multiple Conjunction accounts for compound leading position, is the luminous cardinal principle of LED.For P+N+, due to tensile stress and N-type heavy doping Collective effect, band structure becomes direct band gap, and light emitting region is depletion region, is concentrated mainly on depletion region and is partial to N+'s Side, for P+IN+, since increased eigen I area increases Carrier composite to broaden depletion region, from And luminous efficiency is increased, light emitting region concentrates on depletion region, and being concentrated mainly on depletion region, to be partial to the area N+ and the interface in the area I attached Closely.When meeting waveguide Eg > luminous tube Eg > detector Eg, light travels to explorer portion by waveguide region by LED section. The basic structure of photodetector is a PN junction, when the irradiation for receiving incident optical signal, meeting after electrons and holes are excited Transition occurs, and the energy absorbed determines the position of its transition.Transition in semiconductor, between direct band gap and indirect band gap Can be to corresponding photogenerated current be generated, under applying bias effect, photogenerated current is amplified, to generate detectable signal.For P For+N+ detector, transition area is in depletion region, but since depletion region is relatively narrow, some light may other than depletion region quilt It absorbs, so as to cause quantum efficiency reduction.For P+IN+ detector, eigen I area can broaden depletion region, biggish consumption Area to the greatest extent can increase the absorption region of light, to increase quantum efficiency.Therefore each device in optical integrated device in the present embodiment The forbidden bandwidth relationship of (waveguide, LED and detector) active layer material needs to meet: waveguide Eg > LEDEg > detector Eg, Si base changes Property Ge monolithic same layer light it is integrated when, the forbidden bandwidth of each section device active layer material is consistent, in order to realize that same layer light is integrated, needs The band structure of their each sections is modulated.The present embodiment is modulated using silicon nitride.Since silicon nitride film is directly made With in waveguide, dense film makes waveguide by compression, and forbidden bandwidth increases；Detector stress modulation: due to silicon nitride film with Across n-layer or p layers among intrinsic layer, stress cannot be applied directly to intrinsic layer, but apply stress by intrinsic layer two sides, Dense film makes intrinsic layer two sides by compression, answers so as to cause intrinsic layer in detector along perpendicular to optical transmission direction generation Power, forbidden bandwidth reduce.

In addition, the present embodiment cmos device, which applies silicon nitride film, introduces stress, can be improved in CMOS device NMOS and PMOS carrier mobility, further increases device property.

Optical device and cmos device are integrated on one piece of substrate and make by monolithic optoelectronic integration device provided in this embodiment Make, structural compatibility is preferable；In addition, the injection of CMOS source and drain carries out simultaneously with optical device heavy doping technique, processing compatibility is preferable； The silicon nitride stress film depositing technics of last optical device and cmos device carries out simultaneously, further increases processing compatibility.

In conclusion the specific case optical integrated device structure based on strain a kind of to the utility model used herein Principle and embodiment be expounded, the method for the above embodiments are only used to help understand the utility model and Its core concept；At the same time, for those skilled in the art, based on the idea of the present invention, in specific embodiment And there will be changes in application range, in conclusion the content of the present specification should not be construed as a limitation of the present invention, The protection scope of the utility model should be subject to the attached claims.

Claims (5)

1. a kind of optical integrated device structure based on strain characterized by comprising

Silicon substrate (001)；

LED (10), waveguide (20), detector (30), NMOS device (40) and PMOS device (50), are successively horizontally installed on institute It states on silicon substrate (001)；

Two first grooves (0021) are arranged on the silicon substrate (001), and are located at the LED (10), waveguide (20), visit Survey the two sides of device (30)；

Second groove (0022) is arranged in the centre of the NMOS device (40) and the PMOS device (50)；

Two third grooves (016) are arranged in the two sides of the waveguide (20)；

Stress silicon nitride film is arranged in the waveguide (20), the detector (30), the NMOS device (40) and the PMOS On device (50).

2. the optical integrated device structure based on strain as described in claim 1, which is characterized in that the LED (10) include according to Third epitaxial layer (008), the first Ge layers (009) and the first step part of secondary setting.

3. the optical integrated device structure based on strain as claimed in claim 2, which is characterized in that the first step part packet Include first set gradually Ge layers intrinsic (010), intrinsic GeSn alloy layer (011), second Ge layers intrinsic (012), the 2nd Ge layers (013), N-shaped Si layers (014) and the second oxide layer (015).

4. the optical integrated device structure based on strain as claimed in claim 3, which is characterized in that the detector (30) includes The third epitaxial layer (008), the described first Ge layers (009) and the second step part set gradually.

5. the optical integrated device structure based on strain as claimed in claim 4, which is characterized in that the second step part packet Include described first set gradually Ge layers intrinsic (010), the intrinsic GeSn alloy-layer (011), described second Ge layers intrinsic (012), the described 2nd Ge layers (013), N-shaped Si layers (014) and second oxide layer (015).