CN111354746A - Optoelectronic integrated circuit - Google Patents

Abstract

The invention relates to a photoelectric integrated circuit, comprising a photoelectric conversion region and a semiconductor device region; the photoelectric conversion region comprises a light-emitting device, a waveguide device and a detection device, wherein the light-emitting device, the waveguide device and the detection device are prepared on the same silicon-based substrate, and the light-emitting device, the waveguide device and the detection device are sequentially connected; the semiconductor device region comprises a semiconductor device, and the semiconductor device is connected with the detection device. According to the embodiment of the invention, the same-layer monolithic photoelectric integration is realized by arranging the compressive strain materials on the surface of the PMOS and the surface of the waveguide device, arranging the tensile strain materials on the surface of the NMOS and the surface of the detection device and modulating the forbidden band widths of the waveguide device and the detection device through strain.

Description

Optoelectronic integrated circuits

technical field

The invention belongs to the technical field of semiconductors, and particularly relates to an optoelectronic integrated circuit.

Background technique

The development of optical fiber communication is extremely rapid. By the end of 1991, 5.63 million kilometers of optical cables had been laid in the world, and by 1995, it had exceeded 11 million kilometers. Optical fiber communication can transmit a large amount of information per unit time. A pair of single-mode fibers can open 35,000 calls simultaneously, and it's growing rapidly. The construction cost of optical fiber communication is decreasing with the increase of the number of use. At the same time, it has the advantages of small size, light weight, less metal used, strong anti-electromagnetic interference and radiation resistance, good confidentiality, wide frequency band, and good anti-interference performance. Anti-eavesdropping, cheap and other advantages.

Optoelectronic integrated circuit (OEIC) refers to the integration of optical devices and electrical devices into modules or components with certain optoelectronic functions, which can directly apply optical fiber communication to the chip level and promote the further development of optical fiber communication. Core Technology. Generally speaking, the integration of the cores of discrete devices is called an optoelectronic hybrid integrated module, which is relatively mature in technology, while the integration of optical and electrical components on the same semiconductor substrate is called monolithic integration. Module, which is the development direction of optoelectronic integration.

However, in the current optoelectronic integrated circuits on the same semiconductor substrate, the problem of energy band modulation of detection devices and waveguide devices makes optoelectronic integration very difficult.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides an optoelectronic integrated circuit. The technical problem to be solved by the present invention is realized by the following technical solutions:

An embodiment of the present invention provides an optoelectronic integrated circuit, including a photoelectric conversion region and a semiconductor device region; wherein,

The photoelectric conversion region includes a light-emitting device, a waveguide device, and a detection device. The light-emitting device, the waveguide device, and the detection device are prepared on the same silicon-based substrate, and the light-emitting device, the waveguide device, and the detection device are fabricated. The detection devices are connected in sequence;

The semiconductor device region includes a semiconductor device, and the semiconductor device is connected to the detection device.

In an embodiment of the present invention, the light-emitting device is a PIN diode, the PIN diode includes a first GeSn alloy layer, a first Ge layer and a first Si layer, the first GeSn alloy layer, the first A Ge layer and the first Si layer are sequentially stacked on the silicon-based substrate.

In an embodiment of the present invention, the waveguide device includes a SiO ₂ layer, a second GeSn alloy layer, a Si cover layer and a compressive stress layer; wherein,

The SiO ₂ layer is located on both sides of the waveguide device, and is connected with the light-emitting device and the detection device to form isolation;

The second GeSn alloy layer, the Si cover layer and the compressive stress layer are sequentially stacked on the silicon-based substrate.

In an embodiment of the present invention, the compressive stress layer is a SiN film and has a thickness of 10-20 nm.

In an embodiment of the present invention, the waveguide device is an H-type structure.

In an embodiment of the present invention, the detection device includes a third GeSn alloy layer, a second Ge layer, a second Si layer and a tensile stress layer, the third GeSn alloy layer, the second Ge layer, the The second Si layer and the tensile stress layer are sequentially stacked on the silicon-based substrate.

In an embodiment of the present invention, the compressive stress layer is a SiN film and has a thickness of 10-20 nm.

In one embodiment of the present invention, the semiconductor device is a CMOS device.

In an embodiment of the present invention, the NMOS of the CMOS device is connected to the detection device, and a tensile stress layer is provided on the surface of the NMOS, and the thickness of the tensile stress layer is 10-20 nm.

In an embodiment of the present invention, a compressive stress layer is provided on the PMOS surface of the CMOS device, and the thickness of the compressive stress layer is 10-20 nm.

Compared with the prior art, the beneficial effects of the present invention:

1. By integrating light-emitting devices, waveguide devices and detection devices with semiconductor devices on the same silicon-based material, monolithic optoelectronic integration is achieved, and chip-level optical signal transmission is completed;

2. A stress film is arranged on the surface of the waveguide device and the detection device to realize the stress modulation of the waveguide device and the detection device, which can flexibly control the band gap of the waveguide device and the detection device, and improve the photoelectric conversion efficiency;

2. The preparation process of the present invention is compatible with the traditional silicon-based process, the process is simple and the cost is low.

Description of drawings

1(a)-FIG. 1(b) are schematic structural diagrams of an optoelectronic integrated circuit provided by an embodiment of the present invention;

2 is a schematic diagram of the relationship between the thickness of the SiO ₂ layer and the transmittance of the optical signal provided by the implementation of the present invention;

FIG. 3 is a schematic top-view structural diagram of a waveguide device provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of the influence of the transition waveguide shape of the waveguide device provided by the embodiment of the present invention on the transmission effect of the optical signal;

FIG. 5 is a schematic diagram of stress and force of a waveguide device under SiN film provided by an embodiment of the present invention;

6 is a schematic diagram of the stress and force of the detection device provided by the embodiment of the present invention under the SiN film;

7a-7u are schematic process diagrams of a method for fabricating an optoelectronic integrated circuit according to an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

The optoelectronic integrated circuit of the present invention may include a photoelectric conversion device and other semiconductor devices connected to the photoelectric conversion device. Among them, the photoelectric conversion device mainly includes a light-emitting device, a waveguide device and a detection device. The light-emitting device is used to emit a chip-level optical signal, the waveguide device is used to provide a transmission channel for the optical signal, and the detection device is used to receive the optical signal. The optical signal is converted into an electrical signal to realize photoelectric conversion as a whole. The semiconductor device connected to the photoelectric conversion device may be a CMOS device, a TFT device, a FinFET device, etc., and may be set according to actual circuit requirements, and no limitation is imposed here.

Specifically, please refer to FIG. 1 . FIGS. 1( a ) to 1 ( b ) are schematic structural diagrams of an optoelectronic integrated circuit provided by an embodiment of the present invention, and the semiconductor device is a CMOS device as an example for description. The optoelectronic integrated circuit includes a photoelectric conversion region and a semiconductor device region; wherein, the photoelectric conversion region includes a light-emitting device, a waveguide device and a detection device, the light-emitting device, the waveguide device and the detection device are prepared on the same silicon-based substrate, and the light-emitting device, the waveguide The device and the detection device are connected in sequence; the semiconductor device region includes the semiconductor device, and the semiconductor device is connected with the detection device.

The light-emitting device is a PIN diode, and the PIN diode includes a GeSn alloy layer 010, a Ge layer 011 and a Si layer 012 stacked on the silicon-based substrate. The silicon-based substrate may include a Si substrate 001 and a p-type Si epitaxial layer 002 .

The waveguide device includes a SiO ₂ layer 014 , a GeSn alloy layer 010 , a Si capping layer 015 and a compressive stress layer 018 . The GeSn alloy layer 010, the Si capping layer 015 and the compressive stress layer 018 are sequentially stacked on the silicon-based substrate. Among them, the SiO ₂ layer 014 is located on both sides of the waveguide device, and is connected with the light-emitting device and the detection device to form isolation. This layer of isolation isolates the active device from the passive device, and acts as an electrical isolation to prevent parasitic effects of the optoelectronic devices at both ends. It should be emphasized that the transmittance of the SiO ₂ isolation layer under different thicknesses is shown in Figure 2. Figure 2 is a schematic diagram of the relationship between the thickness of the SiO ₂ layer and the transmittance of the optical signal provided by the implementation of the present invention. It can be seen that the longer the wavelength is, the less the influence of the interface is; the influence of the 20nm-thick _SiO2 isolation layer on the light transmission is basically the same as that without the isolation layer. When the _SiO2 isolation layer is gradually thickened, the transmittance gradually decreases, and Increase the same thicker transmittance but decrease more. That is to say, there is no linear relationship between the thickness of the isolation layer and the transmittance, but the transmittance decreases more as the thickness increases. The above conclusion is because with the increase of thickness, the scattering loss and reflection of _SiO2 are both larger and larger, which leads to the increase of coupling loss. When the wavelength is about 1.75μm, the coupling efficiency between the device and the waveguide without _SiO2 layer and 20nm thick _SiO2 layer is basically 84%~85%, while the coupling efficiency with 50nm thick _SiO2 layer is basically 81%~82%. %.

In addition, the Si cover layer 015 is made of α-Si material, and the addition of the cover layer can reduce the coupling loss, which is basically the same as the coupling between the optical fiber and the device, and can reduce the loss more than the sidewall design.

Further, the waveguide device has an H-type structure. What needs to be emphasized here is that, as shown in FIG. 3 , which is a schematic top-view structure of a waveguide device provided by an embodiment of the present invention, in the shape and length of the tapered transition waveguide of the waveguide device connected to the light-emitting device, the transitions on different sides The waveguide can be concave or convex. It can be seen from the simulation results in Fig. 4 that the concave transition waveguide increases the transmission loss, and the convex transition waveguide has advantages in transmission with a fixed transition length. When practical applications allow, try to select a longer transition wavelength. In addition, the longer the length (L) of the tapered transition waveguide, the smaller the change size in the propagation direction, but it does not increase linearly. As the length increases, the loss decreases less and less, so the light transmission loss The impact is also smaller. Among them, the length L of the tapered transition waveguide is selected from 5 μm to 15 μm, preferably 10 μm.

The detection device includes a GeSn alloy layer 010, a Ge layer 011, a Si layer 012, and a tensile stress layer 019. The GeSn alloy layer 010, the Ge layer 011, the Si layer 012, and the tensile stress layer 019 are sequentially stacked on the silicon-based substrate. Wherein, the compressive stress layer is a SiN film, and the thickness can be 10-20 nm.

The compressive stress film and the tensile stress film are mainly described as follows:

Please refer to FIG. 5. FIG. 5 is a schematic diagram of stress and force of a waveguide device under a SiN film according to an embodiment of the present invention. The waveguide is wrapped in the SiN film 018. Under the action of the SiN film 018, both sides of the waveguide are subjected to compressive stress, and the band gap increases. The relationship between the compressive stress and the band gap is as follows:

F _wg =0.6+0.03×Eg-0.02×Eg ²

Among them, F _w# is the compressive stress received by the waveguide under the action of the SiN film 018, and Eg is the forbidden band width of the waveguide.

Under the condition that other process conditions remain unchanged, the higher the reaction temperature is, the greater the compressive stress of the silicon nitride film is formed, and there is a certain linear relationship. Under the condition that other process conditions remain unchanged, the higher the reaction pressure is, the smaller the compressive stress of the silicon nitride film is formed. Under the condition that other process conditions remain unchanged, the greater the low frequency power, the greater the compressive stress of the silicon nitride film formed.

Wherein, let _Fwg be the size of the compressive stress generated in the waveguide structure caused by the silicon nitride compressive stress film, then the relationship between _Fwg and temperature T ₂ satisfies:

F _wg = -1.0×T _wg -463.6

Wherein, the unit of F _wg is Pa, and the unit of T _wg is Celsius.

Preferably, the temperature ranges from 340°C to 360°C.

Specifically, under the condition that other process conditions remain unchanged, the higher the pressure, the smaller the compressive stress generated in the waveguide structure caused by the SiN film 018.

Among them, the relationship between the compressive stress F _wg and the pressure P _wg satisfies:

F _wg =1.03×P _wg -1365.5

The unit of P _wg is mTorr.

Preferably, the value of the pressure is 500 mTorr.

Specifically, the power is low-frequency power. Under the condition that other process conditions remain unchanged, the greater the power, the greater the compressive stress generated in the waveguide structure caused by the SiN film 018.

Among them, the relationship between the compressive stress F _wg and the first power R _wg satisfies:

F _wg =0.7×R _wg -813.4

Wherein, the unit of R _wg is W.

Preferably, the magnitude of the first power R _wg is 150W.

Specifically, under the condition that other process conditions remain unchanged, the relationship between the gas flow ratio X of silane (SiH ₄ ) and ammonia (NH ₃ ) and the compressive stress is as follows:

F _wg =265.4×X _wg ² -168×X _wg -560

Preferably, X _wg is 2.

Referring to FIG. 6 , FIG. 6 is a schematic diagram of stress and force under the SiN film of the detection device provided by the embodiment of the present invention. The SiN film 019 is a tensile stress film, and the detector is wrapped in the SiN film 019. Under the action of the tensile stress film, the two sides of the detector receive tensile stress, and the forbidden band width is reduced.

Among them, the relationship between tensile stress and forbidden band width is as follows:

F _ts =0.6-0.1×Eg

Among them, F _ts is the tensile stress received by the detector under the action of the tensile stress film, and Eg is the forbidden band width of the detector.

Specifically, under the condition that other process conditions remain unchanged, the higher the reaction temperature, the greater the tensile stress generated in the detector structure due to the formation of the tensile stress film, and has a certain linear relationship.

Wherein, let F _ts be the tensile stress generated by the silicon nitride tensile stress film in the detector structure, then the relationship between F _ts and temperature T _ts satisfies:

F _ts =1.2×T _ts -34.1

Among them, the unit of F _ts is Pa, and the unit of T _ts is Celsius.

Preferably, the temperature ranges from 240°C to 280°C.

Specifically, under the condition that other process conditions remain unchanged, the higher the pressure, the greater the tensile stress generated in the detector structure by the silicon nitride tensile stress film.

Among them, the relationship between the tensile stress F _ts and the pressure P _ts satisfies:

F _ts =0.3×P _ts -28.5

Among them, the unit of P _ts is mTorr.

Preferably, the value of the pressure is 500 mTorr.

Specifically, the power is radio frequency power. Under the condition that other process conditions remain unchanged, the greater the power, the greater the tensile stress generated in the detector structure by the silicon nitride tensile stress film.

Among them, the relationship between the tensile stress F _ts and the power R _ts satisfies:

F _ts =0.7×R _ts -813.4

Among them, the unit of R _ts is W.

Preferably, the magnitude of the power R _ts is 200W.

Specifically, the gas flow ratio of silane (SiH ₄ ) and ammonia gas (NH ₃ ) was 0.75.

In this embodiment, the compressive strain material is arranged on the surface of the PMOS and the surface of the waveguide device, and the tensile strain material is arranged on the surface of the NMOS and the detection device, and the band gap width of the waveguide device and the detection device is modulated by strain to realize the same layer Monolithic optoelectronic integration, simplifying the process, and realizing the manufacturing process of the optoelectronic integrated circuit which is compatible with the existing silicon-based process and has a simple process.

Embodiment 2

Please refer to FIG. 7a to FIG. 7u. FIGS. 7a to 7u are schematic process diagrams of a method for fabricating an optoelectronic integrated circuit according to an embodiment of the present invention. In this implementation, the preparation method is described in detail on the basis of the above-mentioned embodiment.

S101 , as shown in FIG. 7 a , a Si substrate 001 is selected, and a p-type Si epitaxial layer 002 is grown, and the doping concentration is in the order of 10 ¹⁶ cm ⁻³ .

S102, as shown in Figure 7b, a dry etching process is used to etch a groove, and a 10-20 nm _SiO2 layer 003 is deposited under the condition of low temperature plasma enhanced chemical vapor deposition (LPCVD), and the trench isolates the optoelectronic integration region and the CMOS device area.

S103 , as shown in FIG. 7 c , a photoresist 004 layer is used to shield the photoelectric integration region and the NMOS region.

S104 , as shown in FIG. 7d , perform P ion implantation and doping at a low temperature (200-300° C.) to form an N-well region 005 with a concentration of 10 ¹⁶ cm ⁻³ in CMOS and a thickness of 400 nm.

S105, as shown in FIG. 2e, coating photoresist, and exposing the source and drain regions of the PMOS.

S106 , as shown in FIG. 7 f , at 200-300° C., B ions are implanted twice to form PMOS source and drain regions 006 with a concentration of 10 ²⁰ cm ⁻³ level.

S107. As shown in Figure 7g, the NMOS source and drain regions are exposed, and at 200-300 °C, P ions are implanted twice to form NMOS source and drain regions 007 with a concentration of 10 ²⁰ cm ^-3 , and then the implanted silicon wafer is rapidly annealed ( In the RTP) device, high temperature annealing is performed on the NMOS and PMOS source and drain regions at the same time. Rapid annealing equipment can quickly reach a high temperature of around 1000 ° C and maintain the set temperature for several seconds. This state is extremely important for preventing the expansion of the structure and controlling the diffusion of impurities in the source and drain regions.

S108, as shown in Figure 7h, dry etching the photoelectric integration region, leaving a p+Si layer 008 with a thickness of 300 nm.

S109, as shown in Figure 7i, at 330°C, a p++ doped Ge layer 009 with a thickness of 50 nm is epitaxially grown on the Si layer 008 by chemical vapor deposition, and the doping concentration is on the order of 10 ²⁰ cm ^-3 ;

S110, as shown in Figure 7j, at a temperature of 350 °C, a 250 nm intrinsic GeSn alloy layer 010 is grown on the surface of the above-mentioned material by a decompression CVD process. Considering the actual process factors and the solid solubility of Sn in Ge, the composition of Sn is controlled. 3% to 5%.

S111, as shown in Figure 7k, an n+ doped Ge layer 011 with a thickness of 100 nm is epitaxially grown on the GeSn layer at 160°C by chemical vapor deposition, and the doping concentration is on the order of 3×10 ¹⁹ cm ⁻³ .

S112, as shown in FIG. 71, the n++ doped Si layer 012 with a thickness of 100 nm is epitaxially grown on the epitaxial layer by chemical vapor deposition at 275°C to 325°C, and the doping concentration is in the order of 10 ²⁰ cm ⁻³ .

S113 , as shown in FIG. 7m , a 10 nm SiO ₂ layer 013 is deposited on the surface by using a low temperature plasma enhanced chemical vapor deposition (LPCVD) method.

S114, as shown in Figure 7n(a) and Figure 7n(b), first use dry etching process to etch the SiO ₂ oxide layer and the n++ doped Si layer; secondly, use 1:2.5:10 HF: _HNO3 : CH3COOH etching of n+ doped Ge layer. 7n(a) is a cross-sectional view, and FIG. 7n(b) is a plan view.

S115, as shown in Figure 7o(a) and Figure 7o(b), pass SiH ₄ and O ₂ to deposit a 20nm thick SiO ₂ isolation layer 014, and then use a dry etching process to etch to form as shown in the figure, this layer The SiO ₂ isolation layer isolates the active device and the passive device, and plays a certain electrical isolation function to prevent the parasitic effect of the optoelectronic devices at both ends. 7o(a) is a cross-sectional view, and FIG. 7o(b) is a top view.

S116, as shown in Figure 7p(a) and Figure 7p(b), add α-Si cover layer 015 on the basis of the above-mentioned waveguide, adding the cover layer can reduce the coupling loss, which is basically consistent with the coupling between the fiber and the device, and The sidewall design is more able to reduce losses, so a cover layer needs to be added. 7p(a) is a cross-sectional view, and FIG. 7p(b) is a plan view.

S117, as shown in FIG. 7q(a) and FIG. 7q(b), polysilicon is deposited and the gate region 016 is photoetched. Transfer the silicon wafer to the low-pressure chemical vapor deposition equipment, under the conditions of temperature of 575℃～650℃ and pressure of 0.2～1.0 Torr, pure silane or the content of 20%～30% is introduced into the process chamber of the equipment The mixed gas of silane and nitrogen is decomposed by silane, and polysilicon gate is deposited on the surface of the silicon wafer, and the thickness of the deposited polysilicon gate is 50-60 nm. 7q(a) is a cross-sectional view, and FIG. 7q(b) is a plan view.

It should be noted that this S117 can also be completed after S107, and no limitation is imposed here.

S118, as shown in Figure 7r(a) and Figure 7r(b), use electron beam evaporation to deposit aluminum (Al) 017 with a thickness of 70-80 nm to form ohmic contacts in the source and drain regions; use an etching process to selectively etch away designated areas metal Al to form electrodes. Fig. 7r(a) is a cross-sectional view, and Fig. 7r(b) is a plan view.

S119, as shown in Fig. 7s(a) and Fig. 7s(b), the compressive stress SiN film 018 is deposited in the optical waveguide region and the PMOS region, and the plasma-enhanced chemical vapor deposition (PECVD) is used at a temperature of 340℃～360℃. , the process conditions are 500mTorr pressure, apply a low frequency power source, 150W low frequency power, the reaction gas silane (SiH4)/ammonia (NH3) flow ratio is 2, deposit 10 ~ 20nm thick SiN film 018, use the low frequency power The source introduces high-energy particle bombardment, resulting in atom/ion combination or redistribution, that is, the SiN film becomes compressible and stretched/expanded, thereby generating intrinsic compressive stress in the SiN film, which is selectively etched away by the etching process The SiN film in the designated area and the silicon nitride film wrap the waveguide; under the condition that other process conditions remain unchanged, the higher the reaction temperature is, the greater the compressive stress of the silicon nitride film is formed, and there is a certain linear relationship. Under the condition that other process conditions remain unchanged, the higher the reaction pressure is, the smaller the compressive stress of the silicon nitride film is formed. Under the condition that other process conditions remain unchanged, the greater the low frequency power, the greater the compressive stress of the silicon nitride film formed. Among them, Fig. 7s(a) is a cross-sectional view, and Fig. 7s(b) is a plan view.

S120, as shown in Figure 7t(a) and Figure 7t(b), a tensile stress SiN film 019 is deposited in the photodetection area and the NMOS area, and the process conditions are 1500mTorr pressure, 200W RF power, 240 ℃ ~ 280 ℃, using plasma Volume-enhanced chemical vapor deposition (PECVD), the reaction gas silane (SiH4)/ammonia (NH3) flow ratio is 0.75; the detector part is wrapped with a 10-20nm thick tensile stress SiN film 019, so that the film has Very good consistency, the SiN film in the designated area is selectively etched by the etching process, and the silicon nitride film wraps the detector part; under the condition that other process conditions remain unchanged, the higher the reaction temperature, the formation of silicon nitride The larger the tensile stress of the film, the greater the linear relationship. Under the condition that other process conditions remain unchanged, the higher the reaction pressure is, the greater the tensile stress of the silicon nitride film is formed, and there is a certain linear relationship. Under the condition that other process conditions remain unchanged, the greater the RF power, the greater the tensile stress of the silicon nitride film formed. 7t(a) is a cross-sectional view, and FIG. 7t(b) is a plan view.

S121, as shown in Figure 7u(a) and Figure 7u(b), use electron beam evaporation to deposit aluminum (Al) 020 with a thickness of 10-20 nm to form a metal contact; use an etching process to selectively etch away the metal Al in the designated area , forming electrodes. 7u(a) is a cross-sectional view, and FIG. 7u(b) is a top view.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. An optoelectronic integrated circuit, comprising a photoelectric conversion region and a semiconductor device region; wherein, The photoelectric conversion region includes a light-emitting device, a waveguide device, and a detection device. The light-emitting device, the waveguide device, and the detection device are prepared on the same silicon-based substrate, and the light-emitting device, the waveguide device, and the detection device are fabricated. The detection devices are connected in sequence; The semiconductor device region includes a semiconductor device, and the semiconductor device is connected to the detection device. 2 . The optoelectronic integrated circuit according to claim 1 , wherein the light-emitting device is a PIN diode, and the PIN diode comprises a first GeSn alloy layer, a first Ge layer and a first Si layer, and the first A GeSn alloy layer, the first Ge layer and the first Si layer are sequentially stacked on the silicon-based substrate. 3. The optoelectronic integrated circuit according to claim 2, wherein the waveguide device comprises a _SiO2 layer, a second GeSn alloy layer, a Si cover layer and a compressive stress layer; wherein, The SiO ₂ layer is located on both sides of the waveguide device, and is connected with the light-emitting device and the detection device to form isolation; The second GeSn alloy layer, the Si cover layer and the compressive stress layer are sequentially stacked on the silicon-based substrate. 4 . The optoelectronic integrated circuit according to claim 3 , wherein the compressive stress layer is a SiN film and has a thickness of 10-20 nm. 5 . 5. The optoelectronic integrated circuit according to claim 2, wherein the waveguide device has an H-type structure. 6 . The optoelectronic integrated circuit according to claim 1 , wherein the detection device comprises a third GeSn alloy layer, a second Ge layer, a second Si layer and a tensile stress layer, the third GeSn alloy layer, The second Ge layer, the second Si layer and the tensile stress layer are sequentially stacked on the silicon-based substrate. 7 . The optoelectronic integrated circuit according to claim 6 , wherein the compressive stress layer is a SiN film and has a thickness of 10-20 nm. 8 . 8. The optoelectronic integrated circuit according to claim 1, wherein the semiconductor device is a CMOS device. 9 . The optoelectronic integrated circuit according to claim 8 , wherein the NMOS of the CMOS device is connected to the detection device, and a tensile stress layer is provided on the surface of the NMOS, and the thickness of the tensile stress layer is 10 . ~20nm. 10 . The optoelectronic integrated circuit according to claim 9 , wherein a compressive stress layer is provided on the PMOS surface of the CMOS device, and the thickness of the compressive stress layer is 10-20 nm. 11 .

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