CN210325799U - Optical integrated device structure - Google Patents

Abstract

The utility model relates to an optical integrated device structure. The structure includes: a substrate (001); a first trench (0021) disposed on the substrate (001); a light device (100) disposed between the first trenches (0021); a CMOS device (200) disposed on a side of the first trench (0021); a stressed silicon nitride film disposed on the CMOS device (200). The utility model provides an optical integrated device structure forms on through integrating a substrate with optical device and CMOS device, and device novel structure is compatible good, the device integrated level is high, the processing cost is low.

Description

Optical integrated device structure

Technical Field

The utility model relates to an integrated circuit technical field, in particular to optical integrated device structure.

Background

A photodetector is a kind of photodetector device made by using the photoconductive effect of semiconductor materials. The photoelectric detector has wide application in various fields of military and national economy. The infrared radiation sensor is mainly used for ray measurement and detection, industrial automatic control, photometric measurement and the like in visible light or near infrared wave bands; the infrared band is mainly used for missile guidance, infrared thermal imaging, infrared remote sensing and the like. With the development of large-scale integrated circuit technology, the feature size of devices is continuously reduced, the integration scale is larger and larger, the information processing capability is continuously enhanced, and how to realize the integration of photoelectric detection devices, namely optical devices and MOS devices, on a single chip becomes a problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

Therefore, for solving the technical defect and not enough that prior art exists, the utility model provides an optical integrated device structure.

Specifically, an embodiment of the present invention provides an optical integrated device structure, including:

a substrate 001;

a first trench 0021 disposed on the substrate 001;

a light device 100 disposed between the first grooves 0021;

a CMOS device 200 disposed on one side of the first trench 0021;

a stressed silicon nitride film disposed on the CMOS device 200.

In an embodiment of the present invention, the optical device 100 includes: the laser comprises an LED10, a waveguide 20 and a detector 30 which are transversely distributed in sequence, wherein the LED10, the waveguide 20 and the detector 30 are isolated by a third groove 014, the waveguide 20 is arranged in the middle of the third groove 014, and the LED10 and the detector 30 are arranged on two sides of the third groove 014.

In one embodiment of the present invention, the LED10 includes:

a third epitaxial layer 008 disposed on the substrate 001;

a first Ge layer 009 disposed on the third epitaxial layer 008;

a first stepped portion provided on the first Ge layer 009; the first step portion includes a first intrinsic GeSn material layer, a second Ge layer 011, a Si layer 012, and a second oxide layer 013 distributed in sequence.

In an embodiment of the present invention, the detector 30 includes:

a third epitaxial layer 008 disposed on the substrate 001;

a first Ge layer 009 disposed on the third epitaxial layer 008;

a second stepped portion provided on the first Ge layer 009; wherein the second step portion includes a second intrinsic GeSn material layer, a second Ge layer 011, a Si layer 012, and a second oxide layer 013 distributed in sequence.

In an embodiment of the present invention, the LED10 and the detector 30 share the third epitaxial layer 008 and the first Ge layer 009, and the third trench 014 is disposed on the first Ge layer 009.

In an embodiment of the present invention, the optical device 100 further includes a third electrode 020A, a fourth electrode 020B, a fifth electrode 020C, and a sixth electrode 020D; wherein the third electrode 020A is a positive electrode of the LED10, the fourth electrode 020B is a negative electrode of the LED10, the fifth electrode 020C is a positive electrode of the detector 30, and the sixth electrode 020D is a negative electrode of the detector 30.

The utility model has the advantages as follows:

the utility model discloses form the optical integrated device with integrated to a substrate of optical device and CMOS device, device novel structure compatibility is good, the device integrated level is high, the processing cost is low.

Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.

Drawings

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an optical integrated device according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another optical integrated device according to an embodiment of the present invention;

fig. 3a to fig. 3u are schematic diagrams illustrating a manufacturing process of an optical integrated device according to an embodiment of the present invention;

fig. 4a is a top view of a device formed by the optical integrated device manufacturing process shown in fig. 3n according to an embodiment of the present invention;

fig. 4b is a top view of the optical integrated device shown in fig. 3o according to an embodiment of the present invention;

fig. 4c is a top view of the optical integrated device shown in fig. 3p according to an embodiment of the present invention;

fig. 4d is a top view of the optical integrated device shown in fig. 3q according to an embodiment of the present invention;

fig. 4e is a top view of the optical integrated device shown in fig. 3r according to an embodiment of the present invention;

fig. 4f is a top view of the optical integrated device shown in fig. 3s according to an embodiment of the present invention;

fig. 4g is a top view of the optical integrated device shown in fig. 3t according to an embodiment of the present invention;

fig. 4h is a top view of the optical integrated device shown in fig. 3u according to an embodiment of the present invention;

fig. 5a to 5c are schematic top views of three tapered waveguides provided in the embodiments of the present invention;

fig. 6 is a schematic diagram of transmittance at different wavelengths of three types of tapered waveguides, namely, a linear type waveguide, a convex type waveguide, and a concave type waveguide, according to an embodiment of the present invention;

fig. 7 is a schematic diagram of the transmittance of the tapered waveguide at three lengths of 5 μm, 10 μm, and 15 μm according to an embodiment of the present invention;

fig. 8 is a schematic diagram of the transmittance of the isolation layer at different thicknesses according to an embodiment of the present invention;

fig. 9 is a schematic diagram of transmittance of the cover layer at different wavelengths according to an embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of an optical integrated device according to an embodiment of the present invention. The structure includes: a substrate 001, wherein the substrate 001 is a monocrystalline silicon substrate; a first trench 0021 disposed on the substrate 001; a light device 100 disposed between the first grooves 0021; a CMOS device 200 disposed on one side of the first trench 0021; a stressed silicon nitride film disposed on the CMOS device 200.

The optical integrated device structure in the embodiment is formed by integrating the optical device and the CMOS device on one substrate, and has the advantages of novel structure, good compatibility, high device integration level and low process cost.

Example two

Referring to fig. 2, fig. 2 is a schematic view of another optical integrated device structure according to an embodiment of the present invention, and on the basis of the foregoing embodiment, the present embodiment will describe the optical integrated device structure according to the present invention in more detail. The optical device 100 includes: the laser comprises an LED10, a waveguide 20 and a detector 30 which are transversely distributed in sequence, wherein the LED10, the waveguide 20 and the detector 30 are isolated by a third groove 014, the waveguide 20 is arranged in the middle of the third groove 014, and the LED10 and the detector 30 are arranged on two sides of the third groove 014. Wherein, LED10 includes: a third epitaxial layer 008 disposed on the substrate 001; a first Ge layer 009 disposed on the third epitaxial layer 008; a first stepped portion provided on the first Ge layer 009; the first step portion includes a first intrinsic GeSn material layer, a second Ge layer 011, a Si layer 012, and a second oxide layer 013 distributed in sequence. Wherein the detector 30 comprises: a third epitaxial layer 008 disposed on the substrate 001; a first Ge layer 009 disposed on the third epitaxial layer 008; a second stepped portion provided on the first Ge layer 009; wherein the second step portion includes a second intrinsic GeSn material layer, a second Ge layer 011, a Si layer 012, and a second oxide layer 013 distributed in sequence. Wherein the LED10 and the detector 30 share the third epitaxial layer 008 and the first Ge layer 009, and the third trench 014 is disposed on the first Ge layer 009. Wherein the optical device 100 further comprises a third electrode 020A, a fourth electrode 020B, a fifth electrode 020C and a sixth electrode 020D; wherein the third electrode 020A is a positive electrode of the LED10, the fourth electrode 020B is a negative electrode of the LED10, the fifth electrode 020C is a positive electrode of the detector 30, and the sixth electrode 020D is a negative electrode of the detector 30. Wherein the waveguide 20 includes: a third intrinsic GeSn material layer; and a capping layer 015 disposed on the third intrinsic GeSn material layer. The intrinsic GeSn material layer 010 includes a first intrinsic GeSn material layer, a second intrinsic GeSn material layer, and a third intrinsic GeSn material layer, wherein the Sn component in the first intrinsic GeSn material layer is 3%, the Sn component in the second intrinsic GeSn material layer is 5%, and the Sn component in the third intrinsic GeSn material layer is 1%. Wherein the CMOS device 200 includes: a second trench 0022, an NMOS device, and a PMOS device; wherein the NMOS device and the PMOS device are disposed on respective sides of the second trench 0022. Wherein the stressed silicon nitride film comprises: a compressive stress silicon nitride film 018 disposed over said PMOS device; and the tensile stress silicon nitride film 019 is arranged on the NMOS device. The thickness of the compressive stress silicon nitride film 018 and the thickness of the tensile stress silicon nitride film 019 are both 10-20 nm.

EXAMPLE III

Referring to fig. 3a to fig. 3u, fig. 3a to fig. 3u are schematic diagrams illustrating a manufacturing process of an optical integrated device according to an embodiment of the present invention, and based on the above embodiments, the present embodiment will describe in detail the manufacturing process of the optical integrated device according to the present invention. The method comprises the following steps:

s101, selecting a substrate as shown in figure 3a, selecting a monocrystalline silicon substrate 001, extending a silicon layer on the monocrystalline silicon substrate 001, and carrying out light doping on p-type impurities to form a silicon epitaxial layer 002 with the doping concentration of 10¹⁶cm^-3；

S102, etching a trench and depositing an oxide layer as shown in fig. 3B, etching the silicon epitaxial layer 002 by using a dry etching process to form a first trench 0021 and a second trench 0022, wherein the first trench 0021 isolates the silicon epitaxial layer 002 into a first epitaxial layer region 0023 and a second epitaxial layer region 0024, and further the second trench 0022 isolates the second epitaxial layer region 0024 into a first epitaxial layer sub-region 0024A and a second epitaxial layer sub-region 0024B. Depositing a first oxide layer 003, which may be SiO, on the first trench 0021, the first epitaxial layer region 0023, the first epitaxial layer sub-region 0024A, the second epitaxial layer sub-region 0024B, and the second trench 0022 by a low-temperature plasma enhanced chemical vapor deposition (LPCVD) process at a temperature of 250-450 deg.c₂And (3) a layer. The thickness of the first oxide layer 003 is 10-20 nm, that is, the thickness of the first trench 0021, the first epitaxial layer region 0023, the first epitaxial layer sub-region 0024A, the second epitaxial layer sub-region 0024B and the first oxide layer 003 on the surface of the second trench 0022 is 10-20 nm.

S103, coating photoresist

As shown in fig. 3c, a first photoresist 004A is coated on the first trench 0021, the second trench 0022, the first epitaxial layer region 0023, and the first oxide layer 003 on the surface of the first epitaxial layer subregion 0024A. The first photoresist 004A can protect the material underneath from ion implantation, and the high energy impurity ions in the regions not covered by the photoresist can penetrate the upper surface of the material for doping.

S104, ion implantation

As shown in fig. 3d, high energy P ion implantation is performed on the second epitaxial layer sub-region 0024B at a low temperature to form an n-well 005 with a thickness of 200nm and a n-well concentration of 10¹⁶cm^-3(ii) a Further, the temperature can be selected to be 200-300 ℃, and the P ion implantation energy can be selected to be 200 KeV.

S105, coating photoresist

As shown in fig. 3e, a second photoresist 004B is coated on the middle portion of the first oxide layer 003 on the surface of the second epitaxial sub-region 0024B;

S106、preparing a first source region and a first drain region as shown in fig. 3f, performing B ion implantation on the n-well 005 at a temperature of 200-300 ℃ to form a first source region 006A and a first drain region 006B, wherein the doping concentration of the first source region 006A and the first drain region 006B is 10²⁰cm^-3；

S107, preparing a second source region and a second drain region

As shown in fig. 3g, a third photoresist 004C and a fourth photoresist 004D are respectively coated on the first oxide layer 003 on the first source region 006A and the first drain region 006B. Etching the first photoresist 004A on the first oxide layer 003 on the first epitaxial-layer subregion 0024A by an etching process, and reserving a middle portion of the first photoresist 004A on the first oxide layer 003 on the first epitaxial-layer subregion 0024A. Performing P ion implantation on the first epitaxial layer sub-region 0024A at the temperature of 200-300 ℃ to form a second source region 007A and a second drain region 007B; and then annealed in a rapid thermal annealing (RTP) apparatus. The rapid annealing device can rapidly reach high temperature of about 1000 ℃ and keep for several seconds at the set temperature, and the state is very important for preventing the diffusion of the structure and controlling the diffusion of the source/drain region impurities.

S108, etching the first epitaxial layer region

As shown in fig. 3h, the first photoresist 004A, the second photoresist 004B, the third photoresist 004C, and the fourth photoresist 004D are removed. The first epitaxial layer region 0023 is etched by an etching process until the 300nm silicon epitaxial layer 002 remains to form the third epitaxial layer 008.

S109, growing a first Ge layer

As shown in fig. 3i, a p + + doped first Ge layer 009 with a doping concentration of 10nm is epitaxially grown on the third epitaxial layer 008 at a temperature of 330 c to a thickness of 50nm using chemical vapor deposition²⁰cm^-3。

S110, growing intrinsic GeSn material layer 010

As shown in fig. 3j, an intrinsic GeSn material layer 010 with a thickness of 250nm is grown on the first Ge layer 009 by a reduced-pressure CVD process at a temperature of 350 ℃, the Sn composition of the middle portion is controlled to be 1% and the Sn compositions of the two side portions are controlled to be 3% and 5% respectively by partial masking and ion implantation techniques, and the forbidden bandwidth is modulated by the difference of the Sn composition content to satisfy Eg, wherein Eg > leedeg > detector Eg.

S111, growing a second Ge layer

As shown in fig. 3k, an n + doped second Ge layer 011 is epitaxially grown on the intrinsic GeSn material layer 010 at a temperature of 160 ℃ and a doping concentration of 3 x 10 to a thickness of 100nm by a CVD process¹⁹cm^-3。

S112, growing a Si layer

As shown in FIG. 3l, an n + + doped Si layer 012 with a thickness of 100nm is epitaxially grown on the second Ge layer 011 by a CVD process at 275-325 ℃, wherein the doping concentration is 10 ℃²⁰cm^-3。

S113, growing a second oxide layer

As shown in fig. 3m, a second oxide layer 013 with a thickness of 10nm is grown on the Si layer 012 using a low temperature plasma enhanced chemical vapor deposition (LPCVD) process, wherein the second oxide layer 013 may be a silicon dioxide layer (SiO Layer) (LPCVD)₂)。

S114, etching

As shown in fig. 3n and fig. 4a, fig. 4a is a top view of a device formed by the optical integrated device manufacturing process shown in fig. 3n according to an embodiment of the present invention. Firstly, etching the second oxide layer 013 and the Si layer 012 in the first designated area by HF (hydrogen fluoride) by using a dry etching process; secondly, the concentration ratio of 1: 2.5: HF of 10: HNO₃：CH₃Etching the second Ge layer 011 in the first designated area by COOH; finally, the concentration ratio is 1: 2.5: HF of 10: HNO₃：CH₃The COOH etches the second designated region of the layer 010 of intrinsic GeSn material until the first Ge layer 009 is etched to form the LED10, waveguide 20, probe 30, and third trench 014.

Further, the tapered intrinsic GeSn material layer 010 region in the middle of the third trench 014 is the waveguide 20, i.e. the waveguide 20 is a tapered waveguide; the stepped areas on both sides of the third groove 014 are the LED10 and the probe 30, respectively. Specifically, the third epitaxial layer 008, the first Ge layer 009, and the first stepped portion on the first Ge layer 009 form the LED 10; wherein the first step portion is formed by the first intrinsic GeSn material layer, the second Ge layer 011, the Si layer 012, and the second oxide layer 013. The second stepped portions on the third epitaxial layer 008, the first Ge layer 009, and the first Ge layer 009 form the detector 30; wherein the second step portion is a step portion formed by the second intrinsic GeSn material layer, the second Ge layer 011, the Si layer 012, and the second oxide layer 013.

It should be noted that the longer the length of the tapered waveguide, the smaller the change size in the propagation direction, but the longer the tapered waveguide is, the more the length is increased, the less the loss is reduced, and therefore the influence on the transmission loss of light is reduced.

Referring to fig. 5a to 5c, fig. 5a to 5c are schematic top views of three tapered waveguides provided in an embodiment of the present invention. The tapered waveguides with different side surfaces can be divided into three structures, namely a linear type structure, a convex type structure and a concave type structure. The longer the length L of the tapered waveguide, the smaller its variation in the propagation direction, but not the linear increase, the less the loss decreases with increasing length L, and therefore the less the transmission loss of light is affected. Wherein, the linear type, the convex type and the concave type are selected differently, and the length L of the conical waveguide is also different.

Referring to fig. 6, fig. 6 is a schematic diagram of transmittance of three types of tapered waveguides of a linear type, a convex type, and a concave type according to an embodiment of the present invention at different wavelengths. The linear type, the convex type and the concave type have different transmittance under the same wavelength. The side surface of the conical waveguide with a concave structure has the worst transmittance and the largest transmission loss; the conical waveguide with the convex side surface has the best transmission degree in transmission, and the transmission loss is relatively small; the transmission degree and the transmission loss degree of the tapered waveguide with the linear side surface structure are between those of the tapered waveguide with the concave side surface structure and those of the tapered waveguide with the convex side surface structure.

Preferably, the tapered waveguide is optimally performance-optimized for a convex-sided structure.

Referring to fig. 7, fig. 7 is a schematic diagram of transmittance of the tapered waveguide at three lengths of 5 μm, 10 μm, and 15 μm according to an embodiment of the present invention. The longer the wavelength the better the transmission. The longer wavelength is selected as much as practical. Because of the design requirement of the photoelectric device, the length L cannot be too long, and the length L is mostly selected to be 5 μm to 15 μm.

Preferably, the length L of the tapered waveguide is 10 um.

S115, growing an isolation layer

As shown in fig. 3o and fig. 4b, fig. 4b is a top view of the optical integrated device formed by the process of fig. 3o according to the embodiment of the present invention, and SiH is utilized₄And O₂ An isolation layer 0141 with a thickness of 20nm is grown in the third trench 014, wherein the isolation layer 0141 may be SiO₂. The isolation layer 0141 is etched by a dry etching process, and the thickness of the etched isolation layer 0141 is greater than the intrinsic GeSn material layer 010 of the waveguide 20. The isolation layer 0141 isolates the active device from the passive device, that is, the isolation layer 0141 isolates the LED10, the waveguide 20 and the detector 30, and plays a certain electrical isolation role to prevent the photoelectric devices at two ends from generating parasitic effect.

Due to SiO₂The transmittance of the isolation layer under different thicknesses is shown in fig. 8, fig. 8 is a transmittance simulation diagram of the isolation layer under different thicknesses provided by the embodiment of the present invention, and it can be seen from fig. 8 that the longer the wavelength is, the smaller the influence of the interface is; SiO of substantially 20nm thickness₂The influence of the isolation layer on the optical transmission is basically consistent with that of the isolation layer, and the influence on the whole optical transmission is very small and can be basically ignored; when SiO is present₂As the spacer layer is progressively thicker, the transmission progressively decreases, and the same increase in thicker transmission decreases more. It follows that the thickness of the spacer layer is not linearly related to the transmittance, but that the transmittance decreases more as the thickness increases. SiO with increasing thickness₂The coupling loss increases as both scattering loss and reflection increase. No SiO when the wavelength is about 1.75 mu m₂Layer and 20nm thick SiO₂The coupling efficiency between the devices of the layer and the waveguide is substantially 84-85%, while the coupling efficiency at a thickness of 50nm of SiO2 is substantially 81-82%. This indicates that SiO₂The effect on the loss between the device and the waveguide is not negligible. Further, the height of the isolation layer is preferably 20nm in this embodiment.

S116, growing a covering layer

As shown in fig. 3p and 4c, fig. 4c is a top view of the device formed by the optical integrated device manufacturing process shown in fig. 3p according to an embodiment of the present invention, a cladding layer 015 is grown on the intrinsic GeSn material layer 010 of the waveguide 20, and the surface of the cladding layer 015 is flush with the surface of the isolation layer 0141. further, the cladding layer 015 may be selected from α to Si. to reduce the coupling loss, which is substantially consistent with the coupling between the optical fiber and the device, and the loss can be reduced more compared to the sidewall design, so that it is necessary to add the cladding layer.

Referring to fig. 9, fig. 9 is a schematic diagram of the transmittance of the cladding layer at different wavelengths according to the present invention, the transmittance of the cladding layer α -Si at any wavelength is higher than that of the cladding layer α -Si., and the cladding layer α -Si is added to reduce the coupling loss between the optical fiber and the device, so the cladding layer α -Si is added.

Further, the LED10, the waveguide 20, and the detector 30 collectively constitute a light device.

S117, preparing the polysilicon gate

As shown in fig. 3q and 4d, fig. 4d is a top view of the device formed by the optical integrated device manufacturing process shown in fig. 3q according to an embodiment of the present invention, wherein a first polysilicon gate 016A is formed on a first oxide layer 003 on an n-well 005; a second polysilicon gate 016B is formed over the first oxide layer 003 over the first epi subregion 0024A. Specifically, the whole device is transferred into low-pressure chemical vapor deposition equipment, pure silane or mixed gas of silane and nitrogen with the content of 20% -30% is introduced into a process cavity of the equipment under the conditions that the temperature is 575-650 ℃ and the pressure is 0.2-1.0 Torr, and polysilicon gates are deposited on the surfaces of the n-well 005 and the first epitaxial layer sub-region 0024A and the first oxide layer 003 on the first epitaxial layer sub-region 0024A through silane decomposition to respectively form a first polysilicon gate 016A and a second polysilicon gate 016B. Further, the thicknesses of the first polysilicon gate 016A and the second polysilicon gate 016B are 50-70 nm.

S118, preparing a first electrode and a second electrode

As shown in fig. 3r and 4e, fig. 4e is a top view of the device formed by the optical integrated device manufacturing process shown in fig. 3r according to an embodiment of the present invention, aluminum (Al) with a thickness of 70-90 nm is grown on the first source region 006A and the first drain region 006B by an electron beam evaporation process to form a metal contact, and the metal Al in the designated region is selectively etched away by an etching process to form a first electrode 017A; aluminum (Al) with the thickness of 70-90 nm grows on the second source region 007A and the second drain region 007B to form metal contacts, and the metal Al in the designated region is selectively etched by an etching process to form a second electrode 017B.

Further, it can be seen that the first epitaxial layer sub-region 0024A, the second source region 007A, the second drain region 007B, the second polysilicon gate 016B, and the second electrode 017B form an NMOS device; the n-well 005, the first source region 006A, the first drain region 006B, the first polysilicon gate 016A, and the first electrode 017A form a PMOS device.

The NMOS device and the PMOS device together form a CMOS device.

S119, grow compressive stress silicon nitride film as shown in fig. 3S, fig. 4f is the embodiment of the present invention provides a device top view formed by the optical integrated device preparation process shown in fig. 3S, grows compressive stress silicon nitride film 018 with thickness of 10-20 nm on PMOS device 50, and etches away silicon nitride film 018 in the designated area selectively by using the etching process. Specifically, a compressive stress silicon nitride film 018 with a thickness of 10-20 nm is grown on the PMOS device 50 by a plasma enhanced chemical vapor deposition process at a temperature of 340-360 ℃. The process conditions of the plasma enhanced chemical vapor deposition process are as follows: the pressure was 500mTorr, the power of the low frequency power source was 150W, and the reactant gas was Silane (SiH) at a flow ratio of 2₄) And ammonia (NH)₃). It is noted that the introduction of high energy particle bombardment using a low frequency power source results in atomic/ion bonding or redistribution, i.e., the silicon nitride film becomes compressive and stretches/expands, thereby creating intrinsic compressive stress in the silicon nitride film.

S120, growing tensile stress silicon nitride film

As shown in fig. 3t and 4g, fig. 4g is a top view of the device formed by the optical integrated device manufacturing process shown in fig. 3t according to an embodiment of the present invention, and the tensile stress is grown on the NMOS device 40And a tensile stress silicon nitride film 019 is selectively etched away in a designated area by using an etching process. Specifically, a tensile stress silicon nitride film 019 with the thickness of 10-20 nm is grown on the NMOS device 40 by a plasma enhanced chemical vapor deposition process at the temperature of 240-280 ℃. The process conditions of the plasma enhanced chemical vapor deposition process are as follows: the pressure is 1500mTorr, the radio frequency power is 200W, and the reaction gas is 0.75 Silane (SiH) in flow ratio₄) And ammonia (NH)₃)。

S121, preparing an electrode

As shown in fig. 3u and fig. 4h, fig. 4h is a top view of the device formed by the optical integrated device manufacturing process shown in fig. 3u provided by the embodiment of the present invention, aluminum (Al) with a thickness of 10-20 nm is grown on the surface of LED10 by the electron beam evaporation process to form metal contact, metal Al in the designated area is etched selectively by the etching process, third electrode 020A and fourth electrode 020B are formed, aluminum (Al) with a thickness of 10-20 nm is grown on the surface of detector 30 by the electron beam evaporation process to form metal contact, metal Al in the designated area is etched selectively by the etching process, fifth electrode 020C and sixth electrode 020D are formed.

The third electrode 020A is a positive electrode of the LED10, and the fourth electrode 020B is a negative electrode of the LED 10. The fifth electrode 020C is a positive electrode of the probe 30, and the sixth electrode 020D is a negative electrode of the probe 30.

It should be further noted that the basic structure of the LED is a PN junction, and the forward bias is that minority carriers are injected from both sides of the junction, so that non-equilibrium carriers with a concentration higher than the equilibrium concentration exist near the junction, and the carriers recombine. During the recombination of the carriers, energy is released. And the direct radiation recombination between the bottom of the direct band gap conduction band and the top of the valence band of the semiconductor dominates the recombination, which is the main principle of LED luminescence. For P + N +, the energy band structure becomes a direct band gap due to the combined action of tensile stress and N-type heavy doping, the light emitting region is a depletion region and mainly concentrated on one side of the depletion region biased to N +, for P + IN +, the depletion region is widened due to the added intrinsic I region, the carrier recombination region is enlarged, the light emitting efficiency is increased, and the light emitting region is concentrated on the depletion region and mainly concentrated near the interface of the depletion region biased to N + region and I region. When waveguide Eg > leeg > detector Eg is satisfied, light propagates from the LED section through the waveguide region to the detector section. The basic structure of the photodetector is a PN junction, and when irradiated by an incident light signal, electrons and holes are excited to make a transition, and the absorbed energy determines the position of the transition. In the semiconductor, the transition between the direct band gap and the indirect band gap generates corresponding photo-generated current, and the photo-generated current is amplified under the action of external bias voltage, so that a detection signal is generated. For a P + N + detector, the transition region is in the depletion region, but since the depletion region is narrow, part of the light may be absorbed outside the depletion region, resulting in a decrease in quantum efficiency. For a P + IN + detector, the intrinsic I region can widen the depletion region, and the larger depletion region can increase the absorption range of light, thereby increasing the quantum efficiency. Therefore, the forbidden bandwidth relationship of the active layer materials of the devices (waveguide, LED and detector) in the optical integrated device in this embodiment needs to satisfy: when the waveguide Eg, the LEDEG and the detector Eg are integrated by the same-layer light, the forbidden band widths of active layer materials of all parts of the device are consistent, and the energy band structures of all parts of the device are required to be modulated in order to realize the same-layer light integration. In the embodiment, the forbidden band width is modulated by using different Sn component contents to meet the requirement of Eg, so that waveguide Eg > LEDEG > detector Eg.

In addition, the CMOS device of the embodiment applies silicon nitride film to introduce stress, so that the carrier mobility of NMOS and PMOS in the CMOS device can be improved, and the device characteristic is further improved.

The monolithic photoelectric integrated device provided by the embodiment integrates the optical device and the CMOS device on one substrate, so that the structural compatibility is good; in addition, CMOS source drain injection and a light device heavy doping process are carried out simultaneously, and the process compatibility is good; and finally, the silicon nitride stress film deposition processes of the optical device and the CMOS device are carried out simultaneously, so that the process compatibility is further improved.

In summary, the structure principle and the implementation of the optical integrated device of the present invention are explained by applying specific examples, and the above descriptions of the examples are only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be changes in the specific embodiments and applications, and in summary, the content of the present specification should not be understood as a limitation to the present invention, and the scope of the present invention should be defined by the appended claims.

Claims (2)

1. An optical integrated device structure, comprising:

a substrate (001);

a first trench (0021) disposed on the substrate (001);

a light device (100) disposed between the first trenches (0021);

a CMOS device (200) disposed on a side of the first trench (0021);

a stressed silicon nitride film disposed on the CMOS device (200).

2. The photonic integrated device structure according to claim 1, wherein the photonic device (100) comprises: LED (10), waveguide (20) and detector (30) that transversely distribute in proper order, wherein, LED (10) waveguide (20) with detector (30) are through third slot (014) isolation, waveguide (20) set up the centre of third slot (014), LED (10) with detector (30) set up the both sides of third slot (014).

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