CN209462356U - Multiple power supplies timing reset circuit, power supply device and electronic equipment - Google Patents
Multiple power supplies timing reset circuit, power supply device and electronic equipment Download PDFInfo
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Abstract
The utility model discloses a kind of multiple power supplies timing reset circuit, power supply device and electronic equipment, and wherein the multiple power supplies timing reset circuit includes first switch circuit, delay circuit, second switch circuit and third switching circuit；Wherein, the first switch circuit is connect with the first power supply, the first switch circuit also with the second switch circuit connection, the delay circuit is connect with second source, the delay circuit also with the second switch circuit connection, the second switch circuit is also connect with the third switching circuit, and the third switching circuit is also separately connected with third power supply and reset terminal；The electrifying timing sequence for presetting system is first power supply electrifying earlier than the third power supply electrifying, and the third power supply electrifying is powered on earlier than the second source.Technical solutions of the utility model, which can be realized, makes system reset timing, and reduces cost.
Description
Technical field
The utility model relates to timing reset technical field, in particular to a kind of multiple power supplies timing reset circuit, power supply
Device and electronic equipment.
Background technique
With the development of integrated circuit technique, it is embedded in the SOC (System on chip, system on chip) of microcontroller
As the Main way of chip design, and it has been widely used as the memory that storage program uses.It is given in electronic system
When memory powers on, power supply usually requires to reach stable state through after a period of time, and in this process, system mode is not
Determining, it may result in software and start the risk that abnormal or power down storage program is wiped free of, it is therefore desirable to system power supply
Electrification reset is carried out after stabilization and system power supply power down preferentially resets, and protection storage program is not wiped free of.
It is generally solved in the prior art with dedicated PMU (Power Management Unit, Power Management Unit), PMU
Although can be very good to solve system power-on reset timing, cost is relatively high.
Utility model content
The main purpose of the utility model is to provide a kind of multiple power supplies timing reset circuit, it is intended to which can be realized makes system
Reset timing, and reduce cost.
To achieve the above object, the utility model proposes multiple power supplies timing reset circuit include first switch circuit,
Delay circuit, second switch circuit and third switching circuit；Wherein, the first switch circuit is connect with the first power supply, described
Also with the second switch circuit connection, the delay circuit connect first switch circuit with second source, the delay circuit
Also with the second switch circuit connection, the second switch circuit also connect with the third switching circuit, and the third is opened
Powered-down road is also separately connected with third power supply and reset terminal；The electrifying timing sequence for presetting system is that first power supply electrifying is early
In the third power supply electrifying, the third power supply electrifying is powered on earlier than the second source；
When a system is powered up, according to the electrifying timing sequence, in first power supply electrifying, the first switch circuit is defeated
First level signal out, when the second source powers on, the delay circuit exports time delayed signal after predetermined time delay；
According to the first level signal that the time delayed signal and the first switch circuit input, the second switch circuit output first
Level signal；According to the first level signal that the second switch circuit inputs, the third switching circuit is by the third
The first level signal exported when power supply electrifying is switched to output second electrical level signal to the reset terminal, to complete the system
Electrifying timing sequence reset.
Preferably, the power-off sequential that the multiple power supplies timing reset circuit is also used to complete the system resets；Wherein,
The power-off sequential for presetting the system is first power supply power-fail earlier than the third power supply power-fail；
When it is described system is powered down when, according to the power-off sequential, the first switch electricity in first power supply power-fail
Road exports cut-off signals；According to the cut-off signals of first switch circuit input and the delay letter of delay circuit input
Number, the second switch circuit output Continuity signal；According to the Continuity signal that the second switch circuit inputs, the third is opened
The power-off sequential reset that the first level signal of circuit output starts the system to the reset terminal is closed, and according to the power down
The power-off sequential that timing completes the system when the third power supply power-fail is the first level resets.
Preferably, the first switch circuit includes the first resistor, second resistance and the first triode；Wherein,
The first end of the first resistor is connect with first power supply, the second end of the first resistor and described second
The first end of resistance and the base stage of first triode are separately connected, the second end of the second resistance and the one or three pole
The emitter of pipe is grounded.
Preferably, the delay circuit includes 3rd resistor, the 4th resistance and first capacitor；Wherein,
The first end of the 3rd resistor is connect with the second source, the second end of the 3rd resistor and the described 4th
The first end of the first end of resistance and the first capacitor is separately connected, the second end and the first capacitor of the 4th resistance
Second end be grounded.
Preferably, the second switch circuit includes the second triode；Wherein,
The base stage of second triode and the second end of the 3rd resistor, the first end of the 4th resistance and described
The first end of first capacitor is separately connected, and the emitter of second triode is connect with the collector of first triode.
Preferably, the third switching circuit includes the 5th resistance, the 6th resistance and third transistor；Wherein,
The base stage of the third transistor and the first end of the 6th resistance respectively all with the second triode current collection
Pole connection, the emitter ground connection of the third transistor, the first of the collector of the third transistor and the 5th resistance
End and the reset terminal are separately connected, the second end of the second end of the 5th resistance and the 6th resistance respectively all with it is described
The connection of third power supply.
The utility model also proposes that a kind of power supply device, the power supply device include that multiple power supplies timing as described above is multiple
Position circuit.
The utility model also proposes a kind of electronic equipment, and the electronic equipment includes power supply device as described above.
Technical solutions of the utility model are opened by setting first switch circuit, delay circuit, second switch circuit and third
Powered-down road forms a kind of multiple power supplies timing reset circuit.Wherein, the electrifying timing sequence for presetting system is first electricity
Source is powered on earlier than the third power supply electrifying, and the third power supply electrifying is powered on earlier than the second source；When a system is powered up,
According to the electrifying timing sequence, first level signal of first switch circuit output in first power supply electrifying, described
The delay circuit exports time delayed signal after predetermined time delay when second source powers on；According to the time delayed signal and described
First level signal of first switch circuit input, first level signal of second switch circuit output；According to described second
First level signal of switching circuit input, the third switching circuit are electric by export in the third power supply electrifying first
Ordinary mail number is switched to output second electrical level signal to the reset terminal, is resetted with completing the electrifying timing sequence of the system.This is practical
New technique scheme, which can be realized, makes system reset timing, and reduces cost.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the utility model, for those of ordinary skill in the art, in the premise not made the creative labor
Under, the structure that can also be shown according to these attached drawings obtains other attached drawings.
Fig. 1 is the functional block diagram of one embodiment of the utility model multiple power supplies timing reset circuit；
Fig. 2 is the electrical block diagram of one embodiment of the utility model multiple power supplies timing reset circuit；
Fig. 3 is the time stimulatiom figure of the utility model multiple power supplies timing reset circuit.
Drawing reference numeral explanation:
| Label | Title | Label | Title |
| 100 | First switch circuit | Q1~Q3 | First triode is to third transistor |
| 200 | Second switch circuit | R1~R6 | First resistor is to the 6th resistance |
| 300 | Third switching circuit | VCC1~VCC3 | First power supply is to third power supply |
| 400 | Delay circuit | C1 | First capacitor |
| RST | Reset terminal | GND | Ground connection |
The embodiments will be further described with reference to the accompanying drawings for the realization, functional characteristics and advantage of the utility model aim.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describing, it is clear that described embodiment is only a part of the embodiment of the utility model, rather than all
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative work premise
Under every other embodiment obtained, fall within the protection scope of the utility model.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute in the utility model embodiment
It is only used for explaining in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, such as
When the fruit particular pose changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being related to " first ", " second " etc. in the present invention is used for description purposes only, and cannot understand
For its relative importance of indication or suggestion or implicitly indicate the quantity of indicated technical characteristic.Define as a result, " first ",
The feature of " second " can explicitly or implicitly include at least one of the features.In addition, the technical side between each embodiment
Case can be combined with each other, but must be based on can be realized by those of ordinary skill in the art, when the combination of technical solution
Occur it is conflicting or when cannot achieve should people think that the combination of this technical solution is not present, also do not wanted in the utility model
Within the protection scope asked.
The utility model proposes a kind of multiple power supplies timing reset circuits.
Referring to Fig.1, in the utility model embodiment, which includes first switch circuit
100, delay circuit 400, second switch circuit 200 and third switching circuit 300；Wherein, the first switch circuit 100 and
One power supply VCC1 connection, the first switch circuit 100 are also connect with the second switch circuit 200, the delay circuit 400
It is connect with second source VCC2, the delay circuit 400 is also connect with the second switch circuit 200, the second switch electricity
Road 200 is also connect with the third switching circuit 300, the third switching circuit 300 also with third power supply VCC3 and reset terminal
RST is separately connected；The electrifying timing sequence for presetting system is that the first power supply VCC1 is powered on earlier than the third power supply VCC3
It powers on, the third power supply VCC3 is powered on to be powered on earlier than the second source VCC2；
When a system is powered up, according to the electrifying timing sequence, the first switch electricity when the first power supply VCC1 is powered on
Road 100 exports the first level signal, and when the second source VCC2 is powered on, the delay circuit 400 is after predetermined time delay
Export time delayed signal；According to the first level signal that the time delayed signal and the first switch circuit 100 input, described second
Switching circuit 200 exports the first level signal；According to the first level signal that the second switch circuit 200 inputs, described the
Three switching circuits 300 are switched to output second electrical level letter by the first level signal exported when the third power supply VCC3 is powered on
Number to the reset terminal RST, resetted with completing the electrifying timing sequence of the system.
It should be noted that first level signal is low level signal, the second electrical level signal in the present embodiment
For high level signal；It can be readily appreciated that first level signal can be high level signal, institute according to specific requirements application
Stating second electrical level signal is low level signal.
It is worth noting that be that the electrifying timing sequence of the system resets in the present embodiment, it can also be according to the reality of the system
Border application demand is completed power-off sequential and is resetted, and will do it statement explanation in next embodiment, details are not described herein again.
Technical solutions of the utility model pass through setting first switch circuit 100, delay circuit 400, second switch circuit 200
And third switching circuit 300, form a kind of multiple power supplies timing reset circuit.Wherein, the electrifying timing sequence of system is preset
It powers on for the first power supply VCC1 and is powered on earlier than the third power supply VCC3, the third power supply VCC3 is powered on earlier than described
Two power supply VCC2 are powered on；When a system is powered up, according to the electrifying timing sequence, when the first power supply VCC1 is powered on described in first
Switching circuit 100 exports the first level signal, the delay after predetermined time delay when the second source VCC2 is powered on
Circuit output time delayed signal；It is described according to the first level signal that the time delayed signal and the first switch circuit 100 input
Second switch circuit 200 exports the first level signal；According to the first level signal that the second switch circuit 200 inputs, institute
It states third switching circuit 300 and the second electricity of output is switched to by the first level signal exported when the third power supply VCC3 is powered on
Ordinary mail number is resetted to the reset terminal RST with completing the electrifying timing sequence of the system.Technical solutions of the utility model can be realized
Make system reset timing, and reduces cost.
Specifically, the power-off sequential that the multiple power supplies timing reset circuit is also used to complete the system resets；Wherein,
The power-off sequential for presetting the system is the first power supply VCC1 power down earlier than the third power supply VCC3 power down；
When it is described system is powered down when, according to the power-off sequential, in the first power supply VCC1 power down described in first open
Powered-down road 100 exports cut-off signals；The cut-off signals and the delay circuit 400 inputted according to the first switch circuit 100
The time delayed signal of input, the second switch circuit 200 export Continuity signal；According to the second switch circuit 200 input
Continuity signal, the third switching circuit 300 export the first level signal to the reset terminal RST to start falling for the system
Electric timing reset, and the system is completed when the third power supply VCC3 power down is the first level according to the power-off sequential
Power-off sequential resets.
It should be noted that being that the power-off sequential of the system resets in the present embodiment；First level is low electricity
It is flat, identical demand application is resetted according to the electrifying timing sequence of the system, first level signal is low level signal；It is easy to
Understand, according to specific requirements application, first level signal can be high level signal.
Specifically, with reference to Fig. 2, the first switch circuit 100 includes the first resistor R1, second resistance R2 and first
Triode Q1；Wherein,
The first end of the first resistor R1 is connect with the first power supply VCC1, the second end of the first resistor R1 with
The first end of the second resistance R2 and the base stage of the first triode Q1 are separately connected, the second end of the second resistance R2
And the emitter of the first triode Q1 is grounded.
It should be noted that in the present embodiment, when a system is powered up, according to the electrifying timing sequence, in first power supply
Make the first triode Q1 conducting to export the first level signal by the first resistor R1 when VCC1 is powered on；Work as system
When power down, according to the power-off sequential, in the first power supply VCC1 power down, the base voltage of the first triode Q1 is
0 makes the first triode Q1 cut-off to export cut-off signals.
Specifically, the delay circuit 400 includes 3rd resistor R3, the 4th resistance R4 and first capacitor C1；Wherein,
The first end of the 3rd resistor R3 is connect with the second source VCC2, the second end of the 3rd resistor R3 with
The first end of the 4th resistance R4 and the first end of the first capacitor C1 are separately connected, the second end of the 4th resistance R4
It is grounded with the second end of the first capacitor C2.
It should be noted that in the present embodiment, when a system is powered up, according to the electrifying timing sequence, described second
When power supply VCC2 is powered on, by the delay circuit 400, the base stage of the second diode Q2 is due to the delay circuit
400 may be implemented certain delay, and time delayed signal is exported after predetermined time delay；Wherein, delay calculation formula isVoFor the initial voltage value on the first capacitor C1, V1It can be finally charged to for the first capacitor C1
Or the voltage value being put into, VtFor the voltage value on first capacitor C1 described in t moment, R is the 3rd resistor R3 and the described 4th
The resistance value in parallel of resistance；When the voltage value in the first capacitor is charged to 0.7 volt, i.e., arrived after the predetermined time delay
When up to t moment, the second triode Q2 is connected in output time delayed signal.
It should also be noted that, the present embodiment in, when it is described system is powered down when, according to the power-off sequential, due to described
Delay circuit 400 makes the base voltage of the second triode Q2 still be able to maintain its conducting.
Specifically, the second switch circuit 200 includes the second triode Q2；Wherein,
The base stage of the second triode Q2 and second end, the first end of the 4th resistance R4 of the 3rd resistor R3
And the first end of the first capacitor C1 is separately connected, the emitter of the second triode Q2 is with the first triode Q1's
Collector connection.
It should be noted that in the present embodiment, when a system is powered up, according to the time delayed signal and first switch electricity
The first level signal that road 100 inputs is connected and exports the first level signal to the third switching circuit 300；When the system
When power down, led according to the time delayed signal that the cut-off signals of the first switch circuit 100 input and the delay circuit 400 input
Lead to and exports Continuity signal to the third switching circuit 300.
Specifically, the third switching circuit 300 includes the 5th resistance R5, the 6th resistance R6 and third transistor Q3；Its
In,
The base stage of the third transistor Q3 and the first end of the 6th resistance R6 respectively all with second triode
The connection of Q2 collector, the emitter ground connection of the third transistor Q3, the collector of the third transistor Q3 and the described 5th
The first end of resistance R5 and the reset terminal RST are separately connected, the second end of the 5th resistance R5 and the 6th resistance R6
Second end respectively all connect with the third power supply VCC3.
It should be noted that in the present embodiment, when a system is powered up, according to the electrifying timing sequence in the third power supply
Make the third transistor Q3 conducting ground connection to export the first level signal by the 6th resistance R6 when VCC3 is powered on, when
The second switch circuit 200 makes the third transistor Q3 end and be switched to output second when inputting the first level signal
Level signal is resetted to the reset terminal RST with completing the electrifying timing sequence of the system.
It should also be noted that, the present embodiment in, when it is described system is powered down when, according to the power-off sequential, according to described
The Continuity signal that second switch circuit 200 inputs, so that third transistor Q3 conducting is to export the first level signal to institute
Reset terminal RST is stated to start the reset of the power-off sequential of the system, and according to the power-off sequential in the third power supply VCC3
The system is completed in power down power-off sequential when being the first level resets.
It is the time stimulatiom figure of the utility model multiple power supplies timing reset circuit referring to Fig. 3.
In the present embodiment, as shown in figure 3, the first power supply VCC1 is set as 5V, (V in the present embodiment is voltage list
Position volt) power supply and corresponding waveform be ordinate scale be 5 corresponding lines, the second source VCC2 is set as 3.3V power supply
And it is 3.3 corresponding lines that corresponding waveform, which is ordinate scale, the third power supply VCC3 is set as 1.8V power supply, reset terminal
RST waveform is that the nearly scale in ordinate starting point is 0 corresponding lines；According to the electrifying timing sequence and the power-off sequential, from when
In sequence analogous diagram it can be seen that when the second source VCC2 is powered on, since the delay circuit 400 postpones preset time, institute
The low level that reset terminal RST is still able to maintain a period of time is stated, system is completed to reset during this period of time；In first power supply
While VCC1 power down, also power down is low level to the reset terminal RST, at this time the second source VCC2 and the third power supply
VCC3 does not complete power down also, and system starts power-off reset, completes the system when the third power supply VCC3 power down is low level
The power-off sequential of system resets.
The utility model also proposes that a kind of power supply device, the power supply device include that multiple power supplies timing as described above is multiple
Position circuit.
The power supply device includes above-mentioned multiple power supplies timing reset circuit, the specific knot of the multiple power supplies timing reset circuit
Structure at least has referring to above-described embodiment since this power supply device uses whole technical solutions of above-mentioned all embodiments
There are all beneficial effects brought by the technical solution of above-described embodiment, this is no longer going to repeat them.
The power supply device can be applied in the system of multiple power supplies input.
The utility model also proposes a kind of electronic equipment, and the electronic equipment includes power supply device as described above.
The electronic equipment includes above-mentioned power supply device, since this power supply device uses whole skills of above-mentioned all embodiments
Art scheme, therefore at least all beneficial effects brought by the technical solution with above-described embodiment, this is no longer going to repeat them.
The above is only the preferred embodiment of the present invention, and therefore it does not limit the scope of the patent of the utility model,
It is all under the inventive concept of the utility model, equivalent structure made based on the specification and figures of the utility model becomes
It changes, or directly/be used in other related technical areas indirectly and be included in the scope of patent protection of the utility model.
Claims (8)
1. a kind of multiple power supplies timing reset circuit, which is characterized in that including first switch circuit, delay circuit, second switch
Circuit and third switching circuit；Wherein, the first switch circuit is connect with the first power supply, the first switch circuit also with institute
Second switch circuit connection is stated, the delay circuit is connect with second source, and the delay circuit is also electric with the second switch
Road connection, the second switch circuit also connect with the third switching circuit, the third switching circuit also with third power supply
And reset terminal is separately connected；The electrifying timing sequence for presetting system is first power supply electrifying earlier than on the third power supply
Electricity, the third power supply electrifying are powered on earlier than the second source；
When a system is powered up, according to the electrifying timing sequence, the first switch circuit output in first power supply electrifying
One level signal, when the second source powers on, the delay circuit exports time delayed signal after predetermined time delay；According to
The time delayed signal and the first level signal of first switch circuit input, first level of second switch circuit output
Signal；According to the first level signal that the second switch circuit inputs, the third switching circuit is by the third power supply
The first level signal exported when powering on is switched to output second electrical level signal to the reset terminal, to complete the upper of the system
Electric timing reset.
2. multiple power supplies timing reset circuit as described in claim 1, which is characterized in that the multiple power supplies timing reset electricity
The power-off sequential that road is also used to complete the system resets；Wherein, the power-off sequential for presetting the system is described first
Power supply power-fail is earlier than the third power supply power-fail；
When it is described system is powered down when, according to the power-off sequential, in first power supply power-fail, the first switch circuit is defeated
Cut-off signals out；According to the cut-off signals of first switch circuit input and the time delayed signal of delay circuit input, institute
State second switch circuit output Continuity signal；According to the Continuity signal that the second switch circuit inputs, the third switch electricity
Road exports the power-off sequential reset that the first level signal starts the system to the reset terminal, and according to the power-off sequential
The power-off sequential that the system is completed when the third power supply power-fail is the first level resets.
3. multiple power supplies timing reset circuit as claimed in claim 2, which is characterized in that the first switch circuit includes the
One resistance, second resistance and the first triode；Wherein,
The first end of the first resistor is connect with first power supply, the second end of the first resistor and the second resistance
First end and the base stage of first triode be separately connected, the second end of the second resistance and first triode
Emitter is grounded.
4. multiple power supplies timing reset circuit as claimed in claim 3, which is characterized in that the delay circuit includes third electricity
Resistance, the 4th resistance and first capacitor；Wherein,
The first end of the 3rd resistor is connect with the second source, the second end of the 3rd resistor and the 4th resistance
First end and the first end of the first capacitor be separately connected, the of the second end of the 4th resistance and the first capacitor
Two ends are grounded.
5. multiple power supplies timing reset circuit as claimed in claim 4, which is characterized in that the second switch circuit includes the
Two triodes；Wherein,
The base stage of second triode and second end, the first end and described first of the 4th resistance of the 3rd resistor
The first end of capacitor is separately connected, and the emitter of second triode is connect with the collector of first triode.
6. multiple power supplies timing reset circuit as claimed in claim 5, which is characterized in that the third switching circuit includes the
Five resistance, the 6th resistance and third transistor；Wherein,
The base stage of the third transistor and the first end of the 6th resistance all connect with second transistor collector respectively
Connect, the emitter of third transistor ground connection, the first end of the collector of the third transistor and the 5th resistance and
The reset terminal is separately connected, the second end of the second end of the 5th resistance and the 6th resistance respectively all with the third
Power supply connection.
7. a kind of power supply device, which is characterized in that the power supply device includes more as described in claim 1 to 6 any one
Road power supply timing reset circuit.
8. a kind of electronic equipment, which is characterized in that the electronic equipment includes power supply device as claimed in claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920293435.8U CN209462356U (en) | 2019-03-07 | 2019-03-07 | Multiple power supplies timing reset circuit, power supply device and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920293435.8U CN209462356U (en) | 2019-03-07 | 2019-03-07 | Multiple power supplies timing reset circuit, power supply device and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209462356U true CN209462356U (en) | 2019-10-01 |
Family
ID=68047100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920293435.8U Expired - Fee Related CN209462356U (en) | 2019-03-07 | 2019-03-07 | Multiple power supplies timing reset circuit, power supply device and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209462356U (en) |
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2019
- 2019-03-07 CN CN201920293435.8U patent/CN209462356U/en not_active Expired - Fee Related
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Granted publication date: 20191001 |