CN209418501U - A kind of fan-out package structure - Google Patents
A kind of fan-out package structure Download PDFInfo
- Publication number
- CN209418501U CN209418501U CN201822269751.XU CN201822269751U CN209418501U CN 209418501 U CN209418501 U CN 209418501U CN 201822269751 U CN201822269751 U CN 201822269751U CN 209418501 U CN209418501 U CN 209418501U
- Authority
- CN
- China
- Prior art keywords
- chip
- interconnection
- conductive
- layer
- posts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model discloses a kind of fan-out package structures, comprising: transfer layer has at least one layer of first conductive interconnection line；First packaging body, the first chip including multiple stackings and multiple first interconnection posts with different height, the first chip, the pad connection of first interconnection posts one end and chip are respectively arranged in mutually level first interconnection posts, the first interconnection posts other end is electrically connected with the first conductive interconnection line.Using in the transfer layer in bottom, it is connected with each other multiple chips successively by conductive column, the metal terminal of package bottom is connect with transfer layer；Conductive column and chip carry out encapsulating processing, by connecting the conductive column of different height, guarantee that the connection entirely encapsulated is in one plane completed, guarantee the stability of chip, while by the conductive column of connection different height, carrying out pressure equalization；It prevents repeatability laying from rerouting layer and insertion epoxy resin, realizes that multi-chip is integrated because multilayer dielectricity stacks generation chip deformation.
Description
Technical field
The utility model relates to technical field of semiconductor encapsulation, and in particular to a kind of fan-out package structure.
Background technique
Increasingly develop to miniaturization, intelligence, high-performance and high reliability direction to meet electronic product, chip
Miniaturization, it is intelligent make the quantity of chip package pin while being promoted, the size of packaging pin also drops at the fast speed.
I/O connection terminal is dispersed within chip surface area in traditional flip chip wafer grade encapsulation scheme, to limit I/O
Linking number.Fan-out-type wafer-level packaging can solve this problem, simultaneously because it has miniaturization, low cost and height
The advantages that integrated level, therefore rapidly becoming the selection of novel chip and Wafer level packaging.
Usually the back side of bare chip is embedded in the epoxy in the prior art, is then formed and is situated between in the front of bare chip
Electric layer and rewiring layer, and formed and be electrically connected between the positive pad of bare chip and rewiring layer, rerouting layer can advise again
The route for being connected to peripheral epoxy regions from the I/O on bare chip is drawn, then forms soldered ball on the pad for rerouting layer and dashes forward
Structure is played, fan-out package structure is consequently formed.But the fan-out package structure is laid with by repeatability and reroutes layer and insertion
Epoxy resin；Chip deformation is generated because multilayer dielectricity stacks, influences product quality.
Utility model content
Therefore, the utility model provides a kind of fan-out package structure, is generated with reducing packaging body because multilayer dielectricity stacks
Chip deformation, guarantee the product quality of chip.
According in a first aspect, the utility model embodiment provides a kind of fan-out-type structure, include at least:
Transfer layer has at least one layer of conductive interconnection line；First packaging body, the first chip including multiple stackings and has
Multiple first interconnection posts of different height, are respectively arranged with first chip in mutually level first interconnection posts, and described
One interconnection posts one end is connect with the pad of the chip, and the first interconnection posts other end is connect with the conductive interconnection line.
Optionally, the fan-out package structure includes: the second packaging body, is arranged in first packaging body and described turn
It moves between layer, including at least one second chip；
The transfer layer further includes the second interconnection posts, the pad company of second interconnection posts one end and second chip
It connects, the second interconnection posts other end is connect with the first conductive interconnection line.
Optionally, the fan-out package structure includes: the second conductive interconnection line, setting second packaging body towards
The side of first packaging body is connect with first interconnection posts；
The transfer layer further includes third interconnection posts, and third interconnection posts one end and the second conductive interconnection line connect
It connects, the other end of the third interconnection posts is connect with the first conductive interconnection line.
Optionally, the transfer layer includes multilayer the first conductive interconnection line, and the first conductive interconnection described in encapsulating multilayer
The dielectric layer of line layer；It wherein, between different layers is between the first conductive interconnection line by the conductive through hole on the dielectric layer
Electrical connection.
Optionally, the fan-out package structure, comprising:
First encapsulated layer encapsulates first chip, the first conductive column and the second conductive interconnection line；
Second encapsulated layer encapsulates second chip.
Technical solutions of the utility model have the advantages that
In compared with the prior art in the epoxy by the back side insertion of bare chip, it is then formed in the front of bare chip
Dielectric layer and rewiring layer, and formed and be electrically connected between the positive pad of bare chip and rewiring layer, rerouting layer can be again
Planning is connected to the route of peripheral epoxy regions from the I/O on bare chip, then forms soldered ball on the pad for rerouting layer
Raised structures are formed by fan-out package structure.The method is to keep multiple chips logical using in the transfer layer in bottom
It crosses conductive column to be successively connected with each other, the metal terminal of package bottom is connect with transfer layer；Conductive column and chip carry out at encapsulating
Reason guarantees that the connection entirely encapsulated is in one plane completed, guarantees the stabilization of chip by connecting the conductive column of different height
Property, while by the conductive column of connection different height, carry out pressure equalization；It prevents repeatability to be laid with and reroutes layer and insertion epoxy
Resin realizes that multi-chip is integrated because multilayer dielectricity stacks generation chip deformation.
Detailed description of the invention
It, below will be right in order to illustrate more clearly of specific embodiment of the present invention or technical solution in the prior art
Specific embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, it is described below
In attached drawing be that some embodiments of the utility model are not paying creativeness for those of ordinary skill in the art
Under the premise of labour, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the exemplary structure chart of fan-out package structural section of chip provided by the embodiment of the utility model；
Fig. 2-Fig. 6 is chip fan-out package structure chart provided by the embodiment of the utility model.
Appended drawing reference:
10- transfer layer；11- the first conductive interconnection line；12- the second conductive interconnection line；13- conductive through hole；14- first is led
The dielectric layer of electrical interconnection line layer；
The first packaging body of 20-；The first chip of 21-；The first interconnection posts of 22-；23- insulating materials；
The second packaging body of 30-；The second chip of 31-；The second interconnection posts of 32-；33- third interconnection posts.
Specific embodiment
The technical solution of the utility model is clearly and completely described below in conjunction with attached drawing, it is clear that described
Embodiment is the utility model a part of the embodiment, instead of all the embodiments.Based on the embodiments of the present invention, originally
Field those of ordinary skill every other embodiment obtained without making creative work belongs to practical
Novel protected range.
In addition, as long as technical characteristic involved in the utility model different embodiments disclosed below is each other
Not constituting conflict can be combined with each other.
The utility model embodiment provides a kind of fan-out package structure, as shown in Figure 1, the structure includes: transfer layer 10,
With at least one layer of first conductive interconnection line 11；First packaging body 20, the first chip 21 including multiple stackings and has difference
Multiple first interconnection posts 22 of height are respectively arranged with first chip 21 in mutually level first interconnection posts 22, described
First interconnection posts, 22 one end is connect with the pad of the chip 21, and 22 other end of the first interconnection posts and first conduction are mutually
Line electrical connection 11.
In the present embodiment, transfer layer 10 is stacked by the first conductive interconnection of multilayer line 11 and is formed, and transfer layer 10 can also
With referred to as re-wiring layer；First packaging body 20 is made of multiple first chips 21, and there is the gold of band signal in 21 front of the first chip
Belong to pad to be used for and the connection of level first interconnection posts 22；It is connected on transfer layer 10 by the first interconnection posts 22 of different height
The first conductive interconnection line 11, realize multi-chip connection；It is connected using the first conductive column of different height, it is ensured that stacked chips
Planarization guarantees that the chip is in steady state, while the first conductive column of different height carries out pressure point to the chip of stacking
It dissipates, prevents chip deformation.There is capsulation material around first chip 21 of first packaging body 20, passes through grinding or photoetching etc.
Technology realizes that the chip back at the back side is smooth.
Compared to the prior art；In the present embodiment, the first of different height is in using the connection of different height conductive column
Chip 21 reduces repeatability and is laid with rewiring layer and insertion epoxy resin by the chip overall package of multiple stackings；And multilayer
Medium stacking generates chip deformation problems.
As optional embodiment, as shown in Figure 2；Further include: the second packaging body 30 is arranged in first packaging body 20
Between the transfer layer 10, including at least one second chip 31；Second chip, 31 surrounding is surrounded by capsulation material, by grinding
The technologies such as mill or photoetching realize the smooth of the second chip 31.The transfer layer 10 further includes the second interconnection posts 32, and described second
32 one end of interconnection posts is connect with the pad of second chip 31, and 32 other end of the second interconnection posts and first conduction are mutually
Line 11 connects.
In the present embodiment, by increasing by the second packaging body 30 between the first packaging body 20 and transfer layer 10, connection the
One conductive interconnection line 11, it can be achieved that in same finished chip different chips interconnection.
As optional embodiment, further includes: the second conductive interconnection line 12 is arranged in second packaging body 30 towards institute
The side for stating the first packaging body 20 is connect with first interconnection posts 22；
The transfer layer 10 further includes third interconnection posts 33, described 33 one end of third interconnection posts and second conductive interconnection
Line 12 connects, and the other end of the third interconnection posts 33 is connect with the first conductive interconnection line 11.In 20 He of the first packaging body
Increase by the second packaging body 30 between transfer layer 10, third interconnection posts 33 are attached by conductive interconnection line, guarantee stacked chips
Between uniform force, prevent deformation, realize stable multi-chip connection.
Compared to the prior art；The present embodiment is by increasing by the second packaging body between transfer layer 10 and the first packaging body 20
30, chip deformation can not only be prevented, moreover it is possible to realize the interconnection between different chips, improve the integration of chip package.
Fan-out-type structure provided in this embodiment, as shown in Figure 3；Further include: the transfer layer 10 includes that multilayer first is led
Electrical interconnection line 11, and the dielectric layer 14 of the first conductive interconnection line layer described in encapsulating multilayer；It wherein, between different layers is first
It is electrically connected between conductive interconnection line 11 by the conductive through hole 13 on the dielectric layer.By increasing medium in transfer layer 10
Layer is interfered by encasement medium layer blocking signal to prevent close generate between layers from interfering, enables the chip to stablize work
Make, connect conductive interconnection line using conductive through hole 13, is to realize multichip interconnection to realize signal transfer between layers.
It is attached in compared to the prior art by re-laying re-wiring layer, line of transference is connected by conductive column
Layer, can be reduced deformation caused by pressure/welding between chip and re-wiring layer.
The material for preparing of the dielectric layer may is that oxide layer, PI, PBO either resin type organic etc..
Conductive interconnection line in the transfer layer 10 prepares material are as follows: the metal materials such as Al, Cu, W.
Conductive through hole 13 prepares material are as follows: the metal materials such as Al, Cu, W.
The preparation method of first conductive interconnection column 22, the second conductive interconnection column 32, third conductive interconnection column 33: by pre-
The conductive metal first placed performs etching to be formed, and preparing material may is that Al, Cu, SnAg, the metals such as Au, NiAu.
Fan-out-type structure provided in this embodiment, further includes:
First encapsulated layer encapsulates first chip 21, the first conductive column and the second conductive interconnection line 12；
Second encapsulated layer encapsulates second chip 31.
First encapsulated layer and the second encapsulated layer, can be described as encapsulated layer, and the main material of encapsulated layer includes silica, silicon nitride,
The materials such as PI, by being encapsulated to the first chip 21, the first conductive column and the second conductive interconnection line 12, the second chip 31,
Guarantee that signal can stablize transmission in the line, non-stationary member structure can be fixed.
A kind of fan-out package method is present embodiments provided, in conjunction with Fig. 3-Fig. 6, by the detailed encapsulating structure of introducing
The production method of manufacturing process, the encapsulating structure may include steps of:
Step S1: providing transfer layer 10, and the transfer layer 10 has at least one layer of first conductive interconnection line 11；
In the present embodiment, transfer layer 10 is connected by the first conductive interconnection line 11, the conductive through hole 13 of multilayer；It is formed
Transfer layer 10.10 surface of transfer layer is laid with the first conductive interconnection line 11, connect with first conductive column one end, 10 other side of transfer layer
Surface can carry out the techniques such as photoetching, sputtering, plating by surface exposed conductive metal wire out and form metal pad, be planted
Ball forms structure shown in Fig. 3 by executing step S1.
Step S2: multiple first interconnection posts 22 of different height, an interconnection posts the are formed on the transfer layer 10
One end is electrically connected with the first conductive interconnection line 11；
In the present embodiment, the first interconnection posts 22 of different height are no less than 2, and mutually level first conductive column is pairs of
Occur, the first interconnection cylinder is connect to 10 side of transfer layer with the first conductive interconnection line 11, forms Fig. 4 by executing step S2
Shown in structure.
Step S3: the first chip 21 is installed on the other end of mutually level first interconnection posts 22 respectively；
In the present embodiment, the first chip 21 is placed in mutually level first interconnection posts 22 successively to put from low to high
It sets, forms structure shown in fig. 5 by executing step S3.
Step S4: forming the first encapsulated layer on the transfer layer 10, encapsulates first chip 21 and the first interconnection posts
22。
In the present embodiment, first chip 21 and the first interconnection posts 22 are encapsulated, by stacked complete
At structure in fill out fill insulating materials 23, to its structure be formed.Structure shown in fig. 6 is formed by executing step S4.
In the present embodiment, in addition to above-mentioned steps, step S2 further include:
S21. metal layer is formed by being electroplated or being vaporized on the transfer layer 10；
S22. multiple first interconnection posts 22 of different height are formed by multiple etching, wherein etching is formed of the same race every time
Multiple first interconnection posts 22 of height.
In conjunction with Fig. 2, the second packaging body 30 is formed on the transfer layer 10, second packaging body 30 includes at least one
A second chip 31；The transfer layer 10 further includes the second interconnection posts 32, described second interconnection posts, 32 one end and second core
The pad of piece 31 connects, and 32 other end of the second interconnection posts is connect with the first conductive interconnection line 11.In second envelope
The non-chip area for filling body 30 forms third interconnection posts 33, one end of the third interconnection posts 33 and the first conductive interconnection line
11 connections；
The second conductive interconnection line 12 is formed towards the one side of first packaging body 20 in second packaging body 30, it is described
Second conductive interconnection line 12 is connect with the other end of the third interconnection posts 33.
In the present embodiment, middle using naked compared with the prior art by executing the S1-S4 of above-mentioned fan-out package method
The back side insertion of chip in the epoxy, then forms dielectric layer in the front of bare chip and reroutes layer, and in bare chip
It is formed and is electrically connected between positive pad and rewiring layer, rewiring layer can be planned again to be connected to outside from the I/O on bare chip
The route of epoxy regions is enclosed, then forms soldered ball raised structures on the pad for rerouting layer, fan-out package is consequently formed
The method of the method for structure, the present embodiment carries out multi-chip connection by conductive column, is connected by the line of transference in transfer layer 10
Chip, conductive column connect line of transference, carry out signal transmission, easy to assembly by encapsulating to each layer, and arriving for being convenient for is complete
Chip is connected by conductive column between layers, then carries out overall package, without repeatedly encapsulation, can prevent chip shape
Become.Example: transfer layer is complete package body, and there is metal pad on surface, and multiple first packaging body, 20 back sides have the metal of extraction to lead
Electric column is finally being encapsulated by welding/vapor deposition treatment to transfer layer and the first packaging body 20, obtains one completely
Fan-out-type fabric chip.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And thus amplify out it is obvious variation or
It changes among the protection scope created still in the utility model.
Claims (5)
1. a kind of fan-out package structure characterized by comprising transfer layer has at least one layer of first conductive interconnection line；
First packaging body, the first chip including multiple stackings and multiple first interconnection posts with different height, identical height
The first interconnection posts on be respectively arranged with first chip, first interconnection posts one end is connect with the pad of the chip,
The first interconnection posts other end is electrically connected with the first conductive interconnection line.
2. fan-out package structure according to claim 1, which is characterized in that further include:
Second packaging body is arranged between first packaging body and the transfer layer, including at least one second chip；
The transfer layer further includes the second interconnection posts, and second interconnection posts one end is connect with the pad of second chip, institute
The second interconnection posts other end is stated to connect with the first conductive interconnection line.
3. fan-out package structure according to claim 2, which is characterized in that further include:
Side of second packaging body towards first packaging body is arranged in second conductive interconnection line, mutually with described first
Pedestal connection；
The transfer layer further includes third interconnection posts, and third interconnection posts one end is connect with the second conductive interconnection line, institute
The other end for stating third interconnection posts is connect with the first conductive interconnection line.
4. fan-out package structure according to claim 3, which is characterized in that the transfer layer includes that multilayer first is conductive
Interconnection line, and the dielectric layer of the first conductive interconnection line layer described in encapsulating multilayer；Wherein, between different layers be first it is conductive mutually
Pass through the conductive through hole electrical connection on the dielectric layer between line.
5. fan-out package structure according to claim 3, which is characterized in that further include:
First encapsulated layer encapsulates first chip, the first conductive column and the second conductive interconnection line；
Second encapsulated layer encapsulates second chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822269751.XU CN209418501U (en) | 2018-12-29 | 2018-12-29 | A kind of fan-out package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822269751.XU CN209418501U (en) | 2018-12-29 | 2018-12-29 | A kind of fan-out package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209418501U true CN209418501U (en) | 2019-09-20 |
Family
ID=67942046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822269751.XU Active CN209418501U (en) | 2018-12-29 | 2018-12-29 | A kind of fan-out package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209418501U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599390A (en) * | 2018-12-29 | 2019-04-09 | 华进半导体封装先导技术研发中心有限公司 | A kind of fan-out package structure and packaging method |
-
2018
- 2018-12-29 CN CN201822269751.XU patent/CN209418501U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109599390A (en) * | 2018-12-29 | 2019-04-09 | 华进半导体封装先导技术研发中心有限公司 | A kind of fan-out package structure and packaging method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9966276B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105118823A (en) | Stacked type chip packaging structure and packaging method | |
| CN103681607B (en) | Semiconductor devices and preparation method thereof | |
| US9741589B2 (en) | Substrate pad structure | |
| US9847284B2 (en) | Stacked wafer DDR package | |
| US20090032928A1 (en) | Multi-chip stack structure having through silicon via and method for fabrication the same | |
| US20080006948A1 (en) | Stack die packages | |
| CN110021701B (en) | STT-MRAM flip-chip magnetic shielding and manufacturing method thereof | |
| TW201216390A (en) | Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers | |
| CN105140213A (en) | Chip packaging structure and chip packaging method | |
| CN205039151U (en) | Stacked chip package structure | |
| US20200321326A1 (en) | Stress Reduction Apparatus and Method | |
| KR20150091933A (en) | Manufacturing method of semiconductor device and semiconductor device thereof | |
| CN107452702A (en) | The encapsulating structure and method for packing of semiconductor chip | |
| US20070108623A1 (en) | Chip and package structure | |
| CN109599390A (en) | A kind of fan-out package structure and packaging method | |
| CN209418501U (en) | A kind of fan-out package structure | |
| CN110010589B (en) | Stacked semiconductor packaging method and packaging structure | |
| US9576888B2 (en) | Package on-package joint structure with molding open bumps | |
| CN107611045A (en) | A kind of three-dimensional chip encapsulating structure and its method for packing | |
| TW201112387A (en) | Multi-chip package and method of forming multi-chip package | |
| CN216413054U (en) | Multi-chip wafer level fan-out packaging structure | |
| CN114551364A (en) | Multi-chip fan-out type packaging structure and packaging method | |
| KR20130077627A (en) | Semicondcutor apparatus and method of manufacturing the same | |
| US9355902B2 (en) | Method of fabricating semiconductor apparatus with through-silicon via and method of fabricating stack package including the semiconductor chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |