CN209313818U - A kind of novel UART interface level conversion and multiplex electronics - Google Patents
A kind of novel UART interface level conversion and multiplex electronics Download PDFInfo
- Publication number
- CN209313818U CN209313818U CN201822232765.4U CN201822232765U CN209313818U CN 209313818 U CN209313818 U CN 209313818U CN 201822232765 U CN201822232765 U CN 201822232765U CN 209313818 U CN209313818 U CN 209313818U
- Authority
- CN
- China
- Prior art keywords
- level
- transistor
- uart interface
- novel
- level transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Logic Circuits (AREA)
Abstract
The utility model relates to electronic circuit technology fields, specifically, it is a kind of novel UART interface level conversion and multiplex electronics, including two transistors, transistor uses three-level transistor, it is respectively set as three-level transistor Q1 and three-level transistor Q2, the ground level of three-level transistor Q1 and three-level transistor Q2 are connected to respective modules logical high voltage U1, U2, the emitter of three-level transistor Q1 and three-level transistor Q2 are connected with a UART interface respectively, respective modules logical high voltage U3 is connected to after connecting after the collector of three-level transistor Q1 and three-level transistor Q2 are in parallel with a resistance R1, a UART is also connected with after the collector of three-level transistor Q1 and three-level transistor Q2 are in parallel, the utility model circuit is simple, it is very easy to use, It can solve the problems, such as hardware resource deficiency.
Description
Technical field
The utility model relates to electronic circuit technology fields, specifically, being a kind of novel UART interface level conversion
And multiplex electronics.
Background technique
Electronic circuit refers to the circuit being made of electronic device and related radio component.Including amplification, oscillation, rectification,
The circuits such as detection, modulation, frequency transformation, waveform convertion and various control circuits, are widely used in various electronic equipments.
With science and technology it is increasingly developed, electronic product require realize function it is more and more.Based on current communication products
How modularized design integrates more functional modules under limited hardware interface resources, is that each scientific & technical corporation exerts always
Try hard to pursue the target asked.In the case where UART hardware interface is not enough, current existing technical solution is to pass through single-chip microcontroller nothing but
The microcontroller of the resource of the I/O port simulation UART interface or directly selection multichannel UART interface of equal microcontrollers.
Above-mentioned technical proposal has the disadvantage that:
1, the I/O resource and software capacity of microcontroller can be occupied, and use occasion (not having microcontroller circuit) also can
It is restricted.
2, selecting in the obvious cost and size of microcontroller of rich hardware resource can all increased.
3, some circuit Us ART level will be converted, and need to additionally increase component or chip.
Utility model content
In order to solve the above-mentioned technical problem, the utility model discloses a kind of novel UART interface level conversion and multichannel
Multiplex circuit, the circuit are based on hard-wired UART interface level conversion and multiplex electronics, it is by two crystal
Guan Jiayi resistance, symmetrical circuit structure guarantee that another way is unaffected when communication all the way, reaches the function of multiplexing.
The specific technical solution that the utility model uses is as follows:
A kind of novel UART interface level conversion and multiplex electronics, including two transistors, transistor use three
Grade transistor, is respectively set as the base of three-level transistor Q1 and three-level transistor Q2, three-level transistor Q1 and three-level transistor Q2
Grade is connected to respective modules logical high voltage U1, U2, the emitter of three-level transistor Q1 and three-level transistor Q2 respectively with
One UART interface is connected, after connecting after the collector of three-level transistor Q1 and three-level transistor Q2 are in parallel with a resistance R1 again
It is also connected with after being connected to the collector parallel connection of respective modules logical high voltage U3, three-level transistor Q1 and three-level transistor Q2
There is a UART.
Further improvement of the utility model, three-level transistor use DTC143ZETL digital transistor.
Further improvement of the utility model, the resistance value of resistance R1 are 100K ohm.
Further improvement of the utility model, respective modules logical high voltage U1, U2, U3 be+2.8V ,+3.3V ,+
5V。
Further improvement of the utility model, UART interface level are the Transistor-Transistor Logic level of standard.
The utility model has the beneficial effects that the novel UART interface level conversion and multiplexing that the utility model discloses
Circuit circuit is simple, very easy to use, can solve the problems, such as hardware resource deficiency.
Detailed description of the invention
Fig. 1 is the circuit connection diagram of the utility model.
Fig. 2 is the utility model connection schematic diagram in actual circuit.
Specific embodiment
In order to deepen the understanding to the utility model, the utility model is done further below in conjunction with drawings and examples
Detailed description, the embodiment are only used for explaining the utility model, do not constitute and limit to the protection scope of the utility model.
Embodiment: as depicted in figs. 1 and 2, TXD1 and RXD1 are UART1 interface；TXD2 and RXD2 is UART2 interface；
TXD3 and RXD3 is UART3 interface, and U1, U2, U3 are that respective modules logical high voltage (can be+2.8V ,+3.3V ,+5V
Deng).Two-way interface UART1 and UART2 can timesharing communicated with UART3 interface.When UART1 does not have data transmission,
TXD1 is defaulted as high level, and transistor Q1 is in off state, and the low and high level of TXD2 and RXD3 are consistent, i.e. UART2 with
UART3 completes communication；When UART2 does not have data transmission, TXD2 is defaulted as high level, and transistor Q2 is in cut-off shape
The low and high level of state, TXD1 and RXD3 are consistent, i.e. UART1 is communicated with UART3 completion.
In the present embodiment, Q1, Q2 are DTC143ZETL digital transistor, and R1 is 100K resistance；UART interface level is
The Transistor-Transistor Logic level of standard is the circuit of two-way UART interface multiplexing in figure, and the circuit on three tunnels, four tunnels and multiplexing is right according to this
Circuit structure is claimed to analogize.Q1, Q2 transistor can also be realized with N-channel MOS.
The basic principles and main features and advantage of the utility model have been shown and described above.The technical staff of the industry
It should be appreciated that the present utility model is not limited to the above embodiments, the above embodiments and description only describe this
The principle of utility model, on the premise of not departing from the spirit and scope of the utility model, the utility model also has various change
And improvement, these various changes and improvements fall within the scope of the claimed invention.The utility model requires protection scope
It is defined by the appending claims and its equivalent thereof.
Claims (5)
1. a kind of novel UART interface level conversion and multiplex electronics, which is characterized in that described including two transistors
Transistor uses three-level transistor, be respectively set as three-level transistor Q1 and three-level transistor Q2, the three-level transistor Q1 and
The ground level of three-level transistor Q2 is connected to respective modules logical high voltage U1, U2, and the three-level transistor Q1 and three-level are brilliant
The emitter of body pipe Q2 is connected with a UART interface respectively, and the collector of the three-level transistor Q1 and three-level transistor Q2 are simultaneously
Respective modules logical high voltage U3, the three-level transistor Q1 and three-level are connected to after connecting after connection with a resistance R1
A UART is also connected with after the collector of transistor Q2 is in parallel.
2. novel UART interface level conversion and multiplex electronics according to claim 1, which is characterized in that described
Three-level transistor uses DTC143ZETL digital transistor.
3. novel UART interface level conversion and multiplex electronics according to claim 2, which is characterized in that described
The resistance value of resistance R1 is 100K ohm.
4. novel UART interface level conversion and multiplex electronics according to claim 3, which is characterized in that described
Respective modules logical high voltage U1, U2, U3 are+2.8V ,+3.3V ,+5V.
5. novel UART interface level conversion and multiplex electronics according to claim 4, which is characterized in that described
UART interface level is the Transistor-Transistor Logic level of standard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822232765.4U CN209313818U (en) | 2018-12-28 | 2018-12-28 | A kind of novel UART interface level conversion and multiplex electronics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822232765.4U CN209313818U (en) | 2018-12-28 | 2018-12-28 | A kind of novel UART interface level conversion and multiplex electronics |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209313818U true CN209313818U (en) | 2019-08-27 |
Family
ID=67679597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822232765.4U Active CN209313818U (en) | 2018-12-28 | 2018-12-28 | A kind of novel UART interface level conversion and multiplex electronics |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209313818U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560808A (en) * | 2018-12-28 | 2019-04-02 | 南京康派电子有限公司 | A kind of novel UART interface level conversion and multiplex electronics |
-
2018
- 2018-12-28 CN CN201822232765.4U patent/CN209313818U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560808A (en) * | 2018-12-28 | 2019-04-02 | 南京康派电子有限公司 | A kind of novel UART interface level conversion and multiplex electronics |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102324922A (en) | Low voltage difference signal drive circuit and digital signal conveyer | |
| CN209313818U (en) | A kind of novel UART interface level conversion and multiplex electronics | |
| CN106227686A (en) | A kind of MIPI interface signal level shifting circuit based on domestic FPGA and application thereof | |
| CN103686037A (en) | Driver circuit | |
| CN105898493A (en) | Asynchronous receiver transmitter and USB interface multiplexing circuit and circuit board | |
| CN103346771A (en) | Multi-channel switching control circuit compatible with two kinds of protocols and control method | |
| CN106209067B (en) | A kind of reception circuit of interface duplex | |
| CN203135922U (en) | HART modulator-demodulator | |
| CN205883718U (en) | MIPI uses high -speed circuit board | |
| CN109560808A (en) | A kind of novel UART interface level conversion and multiplex electronics | |
| CN207408937U (en) | A kind of conversion circuit of TTL RS 232s interface level | |
| CN206224465U (en) | The circuit of the variable bus address of IIC devices | |
| CN205070974U (en) | Be applied to level shifting circuit of camera | |
| CN106126459B (en) | A kind of I/O data capture card and its collecting method based on CPLD | |
| CN204440388U (en) | A kind of easy data transmission circuit | |
| CN210518267U (en) | Low-rate level conversion circuit | |
| CN103067324B (en) | A kind of HART modulator-demodulator and data transmission method thereof | |
| CN204406394U (en) | USB and ADC interface multiplexing circuit | |
| CN207559972U (en) | A kind of level shifting circuit based on metal-oxide-semiconductor | |
| CN206039509U (en) | MIPI interface signals level shifting circuit based on homemade FPGA | |
| CN204595215U (en) | Based on the GNSS receiver of IMX28 platform minimum systematic module | |
| CN204856475U (en) | Signaling conversion circuit | |
| CN204206154U (en) | The gate circuit conversion equipment of a kind of universal serial port and ISO7816 agreement | |
| CN204680001U (en) | A kind of STM32 chip program programming circuit | |
| CN202551059U (en) | Multifunctional USB (Universal Serial Bus) network card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |