CN106227686A - A kind of MIPI interface signal level shifting circuit based on domestic FPGA and application thereof - Google Patents
A kind of MIPI interface signal level shifting circuit based on domestic FPGA and application thereof Download PDFInfo
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- CN106227686A CN106227686A CN201610579379.5A CN201610579379A CN106227686A CN 106227686 A CN106227686 A CN 106227686A CN 201610579379 A CN201610579379 A CN 201610579379A CN 106227686 A CN106227686 A CN 106227686A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The present invention provides a kind of MIPI interface signal level shifting circuit based on domestic FPGA, including the DSI interface resistors match circuit of the GW1N 4 domestic fpga chip of type, the CSI interface resistors match circuit of MIPI and MIPI.The present invention is directed to the deficiency of signal level conversion plan between FPGA and MIPI interface, turned by signal level between reasonable resistors match real-time performance FPGA and MIPI interface, eliminate electrical level transferring chip, reduce cost, space, circuit complexity etc., improve versatility and the portability of interface circuit.
Description
Technical field
The present invention relates to a kind of MIPI interface signal level shifting circuit based on domestic FPGA and application thereof, belong to circuit
The technical field of design.
Background technology
MIPI interface is the open standard formulated for Mobile solution processor initiated of MIPI alliance and specification, be one
The most popular high speed image transmission means, is mainly used in imageing sensor and processor (CSI interface), processor
And the data transmission between display (DSI interface).MIPI interfacing is at virtual implementing helmet, unmanned plane, intelligence hands
The fields such as machine, panel computer, video camera, wearable device, man machine interface (HMI) are widely applied.
The bridging chip realizing MIPI CSI interface and DSI interface in early days is mostly asic chip, but along with FPGA technology
Development and progress, inherent advantage able to programme with it, reconfigurable progressively replaces asic chip, become user's MIPI interface bridge joint
The first-selection of design.
In the last few years, domestic FPGA product was gradually shown up prominently.The GW1N-4 product of high cloud semiconductor company is high cloud half
Conductor apis florea (LittleBee) family first generation product, has low-power consumption, instantaneous starting, low cost, non-volatile, Gao An
The features such as Quan Xing, encapsulated type are abundant, easy to use and flexible.GW1N-4 chip has abundant I/O resource, logical resource, quiet
State random access memory (B-SRAM) resource, phaselocked loop (PLL) resource, digital signal processing module (DSP) resource and multiple I/O electricity
Flat standard resource.MIPI bridge design can be met, there is the features such as low cost, high-performance, flexible design.
In current CSI interface/DSI Interface design, the signal level conversion between FPGA and MIPI interface uses signal level more
Conversion chip realizes, and the program has the shortcomings such as cost height, complex circuit designs, poor universality, disappears for space requirement harshness
Expense terminal series products is more the increase in design difficulty.Utilize GW1N-4 chip abundant technical characterstic design one be suitable for FPGA with
Signal level shift circuit between MIPI interface becomes the technical problem that technical staff is urgently to be resolved hurrily.
Summary of the invention
For the deficiencies in the prior art, the present invention provides a kind of MIPI interface signal level conversion based on domestic FPGA electricity
Road.
The present invention also provides for signal level conversion between a kind of MIPI interface utilizing foregoing circuit to realize domestic FPGA
Method.The present invention is directed to the deficiency of signal level conversion plan between FPGA and MIPI interface, by reasonable resistors match network
Realize signal level between FPGA and MIPI interface to turn, eliminate electrical level transferring chip, reduce cost, space, circuit complexity
Deng, improve versatility and the portability of interface circuit.
Technical scheme is as follows:
A kind of MIPI interface signal level shifting circuit based on domestic FPGA, including the domestic fpga chip of GW1N-4 type,
The CSI interface resistors match circuit of MIPI and the DSI interface resistors match circuit of MIPI；
Described CSI interface resistors match circuit includes resistance R1, resistance R2；MIPI_I_P difference positive signal receives letter
It is divided into HS_I_P high speed signal and LP_I_P low speed signal during number I/O being sent in described fpga chip；MIPI_I_N difference
HS_I_N high speed signal and LP_I_N low speed letter it is divided into during the I/O that positive signal reception signal is sent in described fpga chip
Number；
HS_I_P high speed signal and HS_I_N high speed signal and the LVDS25I/O interface phase of Bank0 in described fpga chip
Even；
By resistance R1 connection MIPI_I_P difference positive signal to the LVCMOS12I/ of Bank1 in described fpga chip
O Interface, Standard resistance range 30 Ω～75 Ω of described resistance R1；
By resistance R2 connection MIPI_I_N difference positive signal to the LVCMOS12I/ of Bank1 in described fpga chip
O Interface, described resistance R2 Standard resistance range 30 Ω～75 Ω；
The long process such as the advantage of the design is, it is achieved MIPI high speed, reliable and stable transmission, differential signal line need, and control
Differential impedance value processed is at 90 Ω～110 Ω.It addition, resistance R1, resistance R2 are placed on Bank0 in described fpga chip as far as possible
Near LVDS25 interface I/O.If using outer end connecting resistance, it is also desirable to as far as possible near the LVDS25 interface I/O of Bank0；
Described DSI interface resistors match circuit includes resistance R4, resistance R5, resistance R6, resistance R7；
By resistance R4 connection MIPI_O_P signal to the LVDS25I/O interface of Bank2, resistance R4 in described fpga chip
Standard resistance range 100 Ω～400 Ω；
By resistance R5 connection MIPI_O_N signal to the LVDS25I/O interface of Bank2, resistance R5 in described fpga chip
Standard resistance range 100 Ω～400 Ω；
MIPI_O_P signal is connected to the LVCMOS12I/O interface of Bank3, resistance in described fpga chip by resistance R6
R6 Standard resistance range 30 Ω～75 Ω；
By resistance R7 connection MIPI_O_N signal to the LVCMOS12I/O interface of Bank3 in described fpga chip, hinder R7
Standard resistance range 30 Ω～75 Ω；The advantage of the design is, in described fpga chip the HS_O_P high speed signal of I/O interface and
LP_O_P low speed signal merges into MIPI_O_P signal after sealing in resistance, delivers to MIPI interface display device；FPGAI/O connects
HS_O_N high speed signal and the LP_O_N low speed signal of mouth merge into MIPI_O_N signal after sealing in resistance, deliver to MIPI and connect
Mouth display device.In order to realize MIPI at a high speed, reliable and stable transmission, the long process such as differential signal line need, and control differential impedance
Value is at 90 Ω～110 Ω.It addition, resistance R4, resistance R5, resistance R6, resistance R7 are placed on the LVDS25 interface of Bank2 as far as possible
Near I/O.
According to currently preferred, as described MIPI interface signal level shifting circuit not enabled LP based on domestic FPGA
During pattern, described CSI interface resistors match circuit includes also including resistance R3, and the two ends also by resistance R3 connect HS_I_P height
Speed signal and HS_I_N high speed signal, described resistance R3 resistance 100 Ω.
According to currently preferred, described resistance R1, resistance R2, resistance R4, resistance R5, resistance R6 and the resistance of resistance R7
It is respectively 49.9 Ω, 49.9 Ω, 300 Ω, 300 Ω, 51 Ω, 51 Ω.
A kind of method of signal level conversion between MIPI interface utilizing foregoing circuit to realize domestic FPGA, including:
MIPI interface image collecting device is connected with described fpga chip by described CSI interface resistors match circuit；
MIPI interface display device is connected with described fpga chip by described DSI interface resistors match circuit.
According to currently preferred, described that MIPI interface image collecting device is electric by described CSI interface resistors match
When road is connected with described fpga chip, it is achieved MIPI high speed, stable transmission, etc. long process differential signal line, control differential impedance
Value is at 90 Ω～110 Ω.
According to currently preferred, described by MIPI interface display device by described DSI interface resistors match circuit with
When described fpga chip is connected, in described fpga chip, HS_O_P high speed signal and the LP_O_P low speed signal of I/O interface pass through
Merge into MIPI_O_P signal after sealing in resistance R4, resistance R5, deliver to MIPI interface display device；
The HS_O_N high speed signal of FPGAI/O interface and LP_O_N low speed signal close after sealing in resistance R6, resistance R7
And be MIPI_O_N signal, deliver to MIPI interface display device, it is achieved MIPI high speed, stable transmission, etc. long process differential signal
Line, controls differential impedance value at 90 Ω～110 Ω.
The advantage of the present invention:
1) present invention uses fpga chip to be the domestic fpga chip of GW1N-4 type, and this chip has abundant I/O characteristic, bag
Include LVCMOS33/25/18/15/12, LVTTL33, SSTL33/25/18_I/II, SSTL15, HSTL18_I/II, HSTL15_I,
The multiple single-ended level standard such as PCI and LVDS25E, RSDS, LVDS25, BLVDSE, MLVDSE, LVPECLE, RSDSE etc. are multiple
Differential level standard.I/O Bank supply voltage VCCO can be set to flexibly as required 1.2V, 1.5V, 1.8V, 2.5V,
3.3V。
2) MIPI physical layer of the present invention supports HS (High Speed) and two kinds of mode of operations of LP (Low Power).HS mould
Using Low Voltage Differential Signal under formula, differential amplitude 200mV, data rate is 80M～1Gbps；Single-ended signal is used under LP pattern,
Signal amplitude 1.2V, data rate is less than 10Mbps.
3) GW1N-4 chip has plurality of level standard, can meet MIPI interface level conversion requirements well.Pass through
Bank0 and Bank2 uses LVDS25 level standard to realize docking with MIPI interface HS pattern, adopts additionally by Bank1 and Bank3
Realize docking with MIPI interface LP pattern with LVCMOS12 level standard.
4) MIPI interface RX side, the HS pattern of MIPI sends amplitude 200mV, and the LVDS25 of FPGA receives amplitude and has
The receiving ability of 200mV, so the HS signal of MIPI can directly be connected with the LVDS25 electric level interface of Bank0, in order to go
Except the common mode disturbances in differential lines, need to enable 100 Ω terminating resistors of Bank0I/O interface, it is possible to external connection end connecting resistance.Separately
Outward, the LP mode amplitude of MIPI is 1.2V, meets the LVCMOS12 level standard of FPGA, can be with the LVCMOS12 electricity of Bank1
Straight cut is connected.Owing to sharing a pair holding wire under HS and LP pattern, in order to ensure CSI interface under HS and LP both of which
Reliable and stable work, needs to connect suitable build-out resistor between HS signal and LP signal.
5) MIPI interface TX side, the transmission amplitude about 350mV of LVDS25 electric level interface, send bias voltage about 1.25V, for
Receive amplitude and bias voltage ranges under coupling HS pattern, need to seal in proper fit resistance at HS and LP transmitting terminal, it is ensured that
MIPI interface display device can be properly received.
To sum up, the present invention uses the domestic fpga chip of GW1N-4 type of high cloud quasiconductor, and this chip is MIPI bridgt circuit
Core；Give full play to I/O level resource, I/O logical resource and I/O interface capability that GW1N-4FPGA chip is abundant,
Realize effective combination of MIPI interface display device and image capture device and domestic GW1N-4FPGA chip；In conjunction with GW1N-4 core
Sheet feature, is changed by the signal level of reasonable resistors match real-time performance MIPI interface HS and LP both of which, it is ensured that
The high speed of MIPI channel data, transmitting, reduce cost, circuit complexity simultaneously, saved circuit space, improve and connect
The versatility of mouth circuit and portability.
Accompanying drawing explanation
Fig. 1 is the circuit signal that the present invention is connected with MIPI interface image collecting device and MIPI interface image display device
Figure.
Detailed description of the invention
Below in conjunction with embodiment and Figure of description, the present invention is described in detail, but is not limited to this.
As shown in Figure 1.
Embodiment 1,
A kind of MIPI interface signal level shifting circuit based on domestic FPGA, including the domestic fpga chip of GW1N-4 type,
The CSI interface resistors match circuit of MIPI and the DSI interface resistors match circuit of MIPI；
Described CSI interface resistors match circuit includes resistance R1, resistance R2；MIPI_I_P difference positive signal receives letter
It is divided into HS_I_P high speed signal and LP_I_P low speed signal during number I/O being sent in described fpga chip；MIPI_I_N difference
HS_I_N high speed signal and LP_I_N low speed letter it is divided into during the I/O that positive signal reception signal is sent in described fpga chip
Number；
HS_I_P high speed signal and HS_I_N high speed signal and the LVDS25I/O interface phase of Bank0 in described fpga chip
Even；
By resistance R1 connection MIPI_I_P difference positive signal to the LVCMOS12I/ of Bank1 in described fpga chip
O Interface, Standard resistance range 30 Ω～75 Ω of described resistance R1；
By resistance R2 connection MIPI_I_N difference positive signal to the LVCMOS12I/ of Bank1 in described fpga chip
O Interface, described resistance R2 Standard resistance range 30 Ω～75 Ω；
Described DSI interface resistors match circuit includes resistance R4, resistance R5, resistance R6, resistance R7；
By resistance R4 connection MIPI_O_P signal to the LVDS25I/O interface of Bank2, resistance R4 in described fpga chip
Standard resistance range 100 Ω～400 Ω；
By resistance R5 connection MIPI_O_N signal to the LVDS25I/O interface of Bank2, resistance R5 in described fpga chip
Standard resistance range 100 Ω～400 Ω；
MIPI_O_P signal is connected to the LVCMOS12I/O interface of Bank3, resistance in described fpga chip by resistance R6
R6 Standard resistance range 30 Ω～75 Ω；
By resistance R7 connection MIPI_O_N signal to the LVCMOS12I/O interface of Bank3 in described fpga chip, hinder R7
Standard resistance range 30 Ω～75 Ω.
Embodiment 2,
A kind of MIPI interface signal level shifting circuit based on domestic FPGA, its difference is, institute
When stating MIPI interface signal level shifting circuit not enabled LP pattern based on domestic FPGA, described CSI interface resistors match electricity
Road includes also including resistance R3, and the two ends also by resistance R3 connect HS_I_P high speed signal and HS_I_N high speed signal, described
Resistance R3 resistance 100 Ω.
Embodiment 3,
A kind of MIPI interface signal level shifting circuit based on domestic FPGA, its difference is, institute
State the resistance of resistance R1, resistance R2, resistance R4, resistance R5, resistance R6 and resistance R7 be respectively 49.9 Ω, 49.9 Ω, 300 Ω,
300Ω、51Ω、51Ω。
Embodiment 4,
The side of signal level conversion between the MIPI interface of a kind of utilization domestic FPGA of circuit realiration as described in embodiment 1-3
Method, including:
MIPI interface image collecting device is connected with described fpga chip by described CSI interface resistors match circuit；
MIPI interface display device is connected with described fpga chip by described DSI interface resistors match circuit.
Embodiment 5,
The method of signal level conversion between the MIPI interface of the domestic FPGA of circuit realiration, its difference as described in Example 4
It is, described MIPI interface image collecting device is connected with described fpga chip by described CSI interface resistors match circuit
Time, it is achieved MIPI high speed, stable transmission, etc. long process differential signal line, control differential impedance value at 90 Ω～110 Ω.
Described MIPI interface display device is connected with described fpga chip by described DSI interface resistors match circuit
Time, in described fpga chip, HS_O_P high speed signal and the LP_O_P low speed signal of I/O interface pass through and seal in resistance R4, resistance R5
After merge into MIPI_O_P signal, deliver to MIPI interface display device；
The HS_O_N high speed signal of FPGAI/O interface and LP_O_N low speed signal close after sealing in resistance R6, resistance R7
And be MIPI_O_N signal, deliver to MIPI interface display device, it is achieved MIPI high speed, stable transmission, etc. long process differential signal
Line, controls differential impedance value at 90 Ω～110 Ω.
Claims (6)
1. a MIPI interface signal level shifting circuit based on domestic FPGA, it is characterised in that described level shifting circuit
DSI interface resistors match electricity including the domestic fpga chip of GW1N-4 type, the CSI interface resistors match circuit of MIPI and MIPI
Road；
Described CSI interface resistors match circuit includes resistance R1, resistance R2；MIPI_I_P difference positive signal receives signal and passes
Deliver to during the I/O in described fpga chip, be divided into HS_I_P high speed signal and LP_I_P low speed signal；MIPI_I_N difference positive pole
Property signal receive signal be sent in described fpga chip I/O time be divided into HS_I_N high speed signal and LP_I_N low speed signal；
HS_I_P high speed signal is connected with the LVDS25I/O interface of Bank0 in described fpga chip with HS_I_N high speed signal；
Connect MIPI_I_P difference positive signal by resistance R1 to connect to the LVCMOS12I/O of Bank1 in described fpga chip
Mouthful, Standard resistance range 30 Ω～75 Ω of described resistance R1；
Connect MIPI_I_N difference positive signal by resistance R2 to connect to the LVCMOS12I/O of Bank1 in described fpga chip
Mouthful, described resistance R2 Standard resistance range 30 Ω～75 Ω；
Described DS PCI interface resistors match circuit includes resistance R4, resistance R5, resistance R6, resistance R7；
By resistance R4 connection MI PI_O_P signal to the LVDS25I/O interface of Bank2 in described fpga chip, resistance R4's
Standard resistance range 100 Ω～400 Ω；
MIPI_O_N signal is connected to the LVDS25I/O interface of Bank2 in described fpga chip, resistance R5 resistance by resistance R5
Scope 100 Ω～400 Ω；
Connect MIPI_O_P signal by resistance R6 to hinder to the LVCMOS12I/O interface of Bank3 in described fpga chip, resistance R6
Value scope 30 Ω～75 Ω；
MIPI_O_N signal is connected to the LVCMOS12I/O interface of Bank3 in described fpga chip, resistance R7 resistance by resistance R7
Scope 30 Ω～75 Ω.
A kind of MIPI interface signal level shifting circuit based on domestic FPGA the most according to claim 1, its feature exists
In, when described MIPI interface signal level shifting circuit not enabled LP pattern based on domestic FPGA, described CSI interface resistance
Match circuit includes also including resistance R3, and the two ends also by resistance R3 connect HS_I_P high speed signal and HS_I_N letter at a high speed
Number, described resistance R3 resistance 100 Ω.
A kind of MIPI interface signal level shifting circuit based on domestic FPGA the most according to claim 1, its feature exists
In, the resistance of described resistance R1, resistance R2, resistance R4, resistance R5, resistance R6 and resistance R7 be respectively 49.9 Ω, 49.9 Ω,
300Ω、300Ω、51Ω、51Ω。
4. signal level between the MIPI interface of the utilization domestic FPGA of circuit realiration as described in claim 1-3 any one
The method of conversion, it is characterised in that the method includes:
MIPI interface image collecting device is connected with described fpga chip by described CSI interface resistors match circuit；Will
MIPI interface display device is connected with described fpga chip by described DSI interface resistors match circuit.
The most according to claim 4, the method for signal level conversion between the MIPI interface of the domestic FPGA of circuit realiration, it is special
Levy and be, described by MIPI interface image collecting device by described CSI interface resistors match circuit and described fpga chip phase
Lian Shi, it is achieved MIPI high speed, stable transmission, etc. long process differential signal line, controls differential impedance value at 90 Ω～110 Ω.
The most according to claim 4, the method for signal level conversion between the MIPI interface of the domestic FPGA of circuit realiration, it is special
Levy and be, described time MIPI interface display device is connected with described fpga chip by described DSI interface resistors match circuit,
In described fpga chip, the HS_O_P high speed signal of I/O interface and LP_O_P low speed signal are after sealing in resistance R4, resistance R5
Merge into MIPI_O_P signal, deliver to MIPI interface display device；
HS_O_N high speed signal and the LP_O_N low speed signal of FPGAI/O interface are merged into after sealing in resistance R6, resistance R7
MIPI_O_N signal, delivers to MIPI interface display device, it is achieved MIPI high speed, stable transmission, etc. long process differential signal line, control
Differential impedance value processed is at 90 Ω～110 Ω.
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| CN110300221A (en) * | 2019-05-20 | 2019-10-01 | 努比亚技术有限公司 | MIPI control circuit and system, circuit control and circuit system control method |
| CN110336970A (en) * | 2019-07-18 | 2019-10-15 | 广州健飞通信有限公司 | A kind of circuit and its signal synthesis method of multiple signals interface |
| CN114783334A (en) * | 2022-01-10 | 2022-07-22 | 广西显沛光电科技有限公司 | Method for recycling burnt display driving chip |
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Cited By (7)
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| TWI645297B (en) * | 2017-05-26 | 2018-12-21 | 聚晶半導體股份有限公司 | Data transmission system |
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| CN114783334A (en) * | 2022-01-10 | 2022-07-22 | 广西显沛光电科技有限公司 | Method for recycling burnt display driving chip |
| CN116561035A (en) * | 2023-07-07 | 2023-08-08 | 西安智多晶微电子有限公司 | Method and device for two-way communication between FPGA and MIPI and electronic equipment |
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Application publication date: 20161214 |