CN209296010U - A kind of linear hall sensor circuit of adjustable track to track output of sensitivity - Google Patents
A kind of linear hall sensor circuit of adjustable track to track output of sensitivity Download PDFInfo
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- CN209296010U CN209296010U CN201821877138.XU CN201821877138U CN209296010U CN 209296010 U CN209296010 U CN 209296010U CN 201821877138 U CN201821877138 U CN 201821877138U CN 209296010 U CN209296010 U CN 209296010U
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Abstract
A kind of linear hall sensor circuit of adjustable track to track output of sensitivity, including Hall element, sampling hold circuit, chopper amplification circuit, dynamic offset cancellation circuit, low-pass filter circuit, sensitivity control circuit and ratio track to track output circuit.The utility model is the compatible linear hall sensor circuit of CMOS technology, and Hall element is realized using the N trap in CMOS technology, it can be achieved that the advantage that transducer sensitivity is high, consistency is good；Circuit uses the MOS device of voltage-type, low in energy consumption；Using the export structure of track to track, output linearly can reach the range greater than ground voltage 0.1V and less than supply voltage 0.1V, the sensitivity of circuit can be adjusted by the external feedback resistance of track to track output amplifier structure simultaneously, realize the adjustable advantage of sensitivity.
Description
Technical field
The utility model relates to a kind of linear hall sensor circuits, especially provide a kind of adjustable track to track of sensitivity
Export linear hall sensor circuit.
Background technique
Hall sensor chip is that Hall element and signal processing circuit are integrated in same core using microelectric technique
The monolithic integrated circuit of on piece is to can be not only used for magnetic-field measurement using extensive magnetic field sensor at present, can be also used for electricity
The measurement of the physical quantitys such as stream, speed, position, angle, in automotive electronics, smart grid, accurate measurement, industrial automation, household
The fields such as electric appliance and emerging consumer electronics are widely used.
The linear hall sensor of traditional bipolar process, Hall element realized using epitaxial layer, the sensitivity of product due to
Epitaxy layer thickness is big, uneven, simultaneously because the influence of the factors such as manufacturing process drift, encapsulation stress, magnetic field sensitivity is low, and
Fluctuate larger, consistency is poor, and yield rate is low；The linear hall sensor of traditional bipolar process uses in the realization of circuit
Current mode triode device, power consumption is larger, is not suitable for the requirement of low-power consumption application, and in addition its linear output range is narrow, general big
In ground voltage 0.7V and range less than supply voltage 0.7V, above it is restricted in application.
Utility model content
To solve the above-mentioned problems, the purpose of the utility model is to provide a kind of high sensitivity, consistency are good, low in energy consumption
The adjustable track to track of sensitivity export linear hall sensor circuit.
In order to achieve the above objectives, the technical solution of the utility model is as follows: a kind of adjustable track to track output of sensitivity
Linear hall sensor circuit, including it is Hall element, sampling hold circuit, chopper amplification circuit, dynamic offset cancellation circuit, low
Bandpass filter circuit, sensitivity control circuit and ratio track to track output circuit；The Hall element uses CMOS technology, can monolithic
It is integrated, it is realized with N-type semiconductor silicon materials, for incuding external magnetic strength induction signal；The sampling hold circuit is to Hall member
The magnetic signal of part carries out sampling holding, and modulates magnetic strength induction signal；Output of the chopper amplification circuit to sampling hold circuit
Faint magnetic signal carries out chopper amplification, demodulates magnetic strength induction signal, and eliminate noise；The dynamic offset cancellation circuit puts copped wave
The output signal of big circuit carries out the elimination of offset voltage；It is generated in the low-pass filter circuit filtering circuit signal processing
High-frequency signal and burr；The gain of the sensitivity control circuit control ratio track to track output circuit, to realize adjustment
Hall sensing circuit it is sensitive；The ratio track to track output circuit realize magnetic strength induction signal fixed gain and track to track it is defeated
Out.
Further, the ratio track to track output circuit is by several resistance and switch arrays and track to track output circuit group
At；The resistance and switch arrays include R1-K1 array, R9-K5 array, R17-K9 array and R22-K11 array；The R1-
K1 array includes resistance R1, R2, R3, R4, R5, R6, R7, the R8 being cascaded and in parallel with resistance R5, R6, R7, R8 respectively
Switch K1, K2, K3, K4, the supply voltage VDD/2 of the termination of R1-K1 array one 1/2, other end connects track to track output
The positive input terminal INP of circuit；The R9-K5 array include the resistance R9, R10 being cascaded, R11, R12, R13, R14,
R15, R16 and switch K5, K6, K7, K8 in parallel with resistance R13, R14, R15, R16 respectively, R9-K5 array one end integrate with
To the negative input end INN of rail output circuit, other end connects the output end of track to track output circuit；The R17-K9 array includes
It is R17-K9 gusts described respectively with resistance R17, R18 concatenated switch K9, K10 and in parallel resistance R17, R18, R19, R20, R21
1 port of the termination input of column one, other end meet the positive input terminal INP of track to track output circuit；The R22-K11 array includes point
It is R22-K11 gusts described not with resistance R25, R26 concatenated switch K11, K12 and in parallel resistance R22, R23, R24, R25, R26
2 ports of the termination input of column one, other end meet the negative input end INN of track to track output circuit.
Further, the track to track output circuit includes current source I1, I2, I3, I4, I5, NMOS tube MN1, MN2, MN3,
MN4, MN5, MN6, MN7, PMOS tube MP1, MP2, MP3, MP4, MP5, MP6, MP7 and capacitor C1, C2；The current source I1 is
NMOS tube MN1, MN2 provides bias current, a termination VDD, the drain electrode of another termination NMOS tube MN1；NMOS tube MN1, MN2
Being connected into diode connection type, i.e. drain and gate links together, the drain electrode of the source electrode connection NMOS tube MN2 of NMOS tube MN1,
The source electrode of NMOS tube MN2 meets GND；NMOS tube MN1, MN7 connects into current mirror manner, provides image current for MN7；It is described
Current source I2 mono- terminates GND, and the drain electrode of another termination PMOS tube MP1 provides bias current for PMOS tube MP1；The PMOS tube
The grid of MP1 is connected with drain electrode, and described PMOS tube MP1, MP3 and MP5 connect into current mirror manner, mentions for PMOS tube MP3, MP5
For image current, the source electrode of PMOS tube MP1, MP3 and MP5 meet VDD, and the drain electrode of the PMOS tube MP3 connects the source of PMOS tube MP4
Pole, the drain electrode of PMOS tube MP5 connect the source electrode of PMOS tube MP6；The NMOS tube MN3 and MN4 is differential pair, input terminal INN and INP
The negative input end and positive input terminal of electric current are exported for track to track, the drain electrode of NMOS tube MN3 and MN4 meet PMOS tube MP4 and MP6 respectively
Source electrode, constitute the amplifier architecture of cascade；The current source I3 mono- terminates the source electrode of NMOS tube MN3, MN4, the other end
GND is met, provides tail current for the differential pair；The source electrode of the PMOS tube MP2 meets VDD, and grid is connected with drain electrode, drain electrode connection
Current source I4 is followed by GND, and current source I4 provides bias current for PMOS tube MP2；Described PMOS tube MP2, MP4 and MP6 are connected into
Current mirror manner provides image current for PMOS tube MP4, MP6；The drain electrode of the drain electrode connection NMOS tube MN7 of the PMOS tube MP6
With the grid of PMOS tube MP7；The drain electrode of the source electrode connection NMOS tube MN6 of the NMOS tube MN7；The drain electrode of the NMOS tube MN5
The drain electrode of PMOS tube MP4 is connect, grid is connected with drain electrode；The NMOS tube MN5 and MN6 connects into current mirror manner, NMOS tube MN5
GND is met with the source electrode of MN6, grid is followed by GND by capacitor C2；The capacitor C2 is to stablize capacitor；The PMOS tube MP7's
Source electrode meets VDD, and drain electrode connection current source I5 is followed by GND, and bias current is provided by current source I5；The capacitor C1 and resistance R1
It is connected across grid and the drain electrode of PMOS tube MP7 after series connection, as miller compensation, makes amplifier that there is certain phase margin, surely
Determine system, the PMOS tube MP7 is efferent duct, and drain electrode is the output port of track to track output circuit.
Further, the resistance value of the R1-K1 array and R9-K5 array is equal and strictly matches, R17-K9 array and R22-
The resistance value of K11 array is equal and strictly matches.
Further, the quantity of the resistance and switch arrays can be done according to the actual demand of product and increase and decrease, to realize difference
Sensitivity.
Further, the number of the resistance and the resistance in switch arrays can by the mask of chip die production process come
Modification.
Further, the switch in the resistance and switch arrays can blow the side such as resistance by fuse opening resistance, laser
Formula is realized.
The beneficial effects of the utility model are: (1) the utility model is the compatible linear hall sensor electricity of CMOS technology
Road, Hall element are realized using the N trap in CMOS technology, it can be achieved that the advantage that transducer sensitivity is high, consistency is good；(2) electric
Road uses the MOS device of voltage-type, low in energy consumption；(3) export structure of track to track is used, output, which linearly can reach, is greater than ground electricity
0.1V and the range less than supply voltage 0.1V are pressed, while the sensitivity of circuit can pass through the outer of track to track output amplifier structure
Portion's feedback resistance adjusts, and realizes the adjustable advantage of sensitivity.
Detailed description of the invention
Fig. 1 is that the adjustable track to track of the utility model sensitivity exports linear hall sensor circuit block diagram；Fig. 2 is this
Utility model ratio track to track output circuit internal frame diagram；Fig. 3 is the utility model track to track output circuit figure.
Specific embodiment
Specific embodiment of the present utility model is described in detail with reference to the accompanying drawing.
As shown in Figure 1, a kind of adjustable track to track of sensitivity exports linear hall sensor circuit, including Hall member
Part, sampling hold circuit, chopper amplification circuit, dynamic offset cancellation circuit, low-pass filter circuit, sensitivity control circuit and ratio
Example track to track output circuit；The Hall element use CMOS technology, can single-chip integration, with N-type semiconductor silicon materials realize, use
Magnetic strength induction signal outside induction；The sampling hold circuit carries out sampling holding to the magnetic signal of Hall element, and modulates
Magnetic strength induction signal；The chopper amplification circuit carries out chopper amplification to the faint magnetic signal of the output of sampling hold circuit, solves adjustable magnetic
Inductive signal, and eliminate noise；The dynamic offset cancellation circuit carries out offset voltage to the output signal of chopper amplification circuit
Elimination；The high-frequency signal and burr generated in the low-pass filter circuit filtering circuit signal processing；The sensitivity
Control circuit controls the gain of ratio track to track output circuit, to realize the sensitive of adjustment hall sensing circuit；The ratio
Track to track output circuit realizes the fixed gain of magnetic strength induction signal and the output of track to track.
As shown in Fig. 2, the ratio track to track output circuit exports electricity by several resistance and switch arrays and track to track
Road composition；The resistance and switch arrays include R1-K1 array, R9-K5 array, R17-K9 array and R22-K11 array；It is described
R1-K1 array include resistance R1, R2, R3, R4, R5, R6, R7, the R8 being cascaded and respectively with resistance R5, R6, R7, R8 simultaneously
Switch K1, K2, K3, K4 of connection, the supply voltage VDD/2 of the termination of R1-K1 array one 1/2, it is defeated that other end connects track to track
The positive input terminal INP of circuit out；The R9-K5 array include the resistance R9, R10 being cascaded, R11, R12, R13, R14,
R15, R16 and switch K5, K6, K7, K8 in parallel with resistance R13, R14, R15, R16 respectively, R9-K5 array one end integrate with
To the negative input end INN of rail output circuit, other end connects the output end of track to track output circuit；The R17-K9 array includes
It is R17-K9 gusts described respectively with resistance R17, R18 concatenated switch K9, K10 and in parallel resistance R17, R18, R19, R20, R21
1 port of the termination input of column one, other end meet the positive input terminal INP of track to track output circuit；The R22-K11 array includes point
It is R22-K11 gusts described not with resistance R25, R26 concatenated switch K11, K12 and in parallel resistance R22, R23, R24, R25, R26
2 ports of the termination input of column one, other end meet the negative input end INN of track to track output circuit.
As shown in figure 3, the track to track output circuit includes current source I1, I2, I3, I4, I5, NMOS tube MN1, MN2,
MN3, MN4, MN5, MN6, MN7, PMOS tube MP1, MP2, MP3, MP4, MP5, MP6, MP7 and capacitor C1, C2；The current source I1
Bias current, a termination VDD, the drain electrode of another termination NMOS tube MN1 are provided for NMOS tube MN1, MN2；The NMOS tube MN1,
MN2 is connected into diode connection type, i.e. drain and gate links together, the leakage of the source electrode connection NMOS tube MN2 of NMOS tube MN1
The source electrode of pole, NMOS tube MN2 meets GND；NMOS tube MN1, MN7 connects into current mirror manner, provides image current for MN7；
The current source I2 mono- terminates GND, and the drain electrode of another termination PMOS tube MP1 provides bias current for PMOS tube MP1；It is described
The grid of PMOS tube MP1 with drain electrode be connected, described PMOS tube MP1, MP3 and MP5 connect into current mirror manner, for PMOS tube MP3,
MP5 provides image current, and the source electrode of PMOS tube MP1, MP3 and MP5 meet VDD, and the drain electrode of the PMOS tube MP3 connects PMOS tube
The source electrode of MP4, the drain electrode of PMOS tube MP5 connect the source electrode of PMOS tube MP6；The NMOS tube MN3 and MN4 is differential pair, input terminal
INN and INP is the negative input end and positive input terminal that track to track exports electric current, and the drain electrode of NMOS tube MN3 and MN4 connect PMOS tube respectively
The source electrode of MP4 and MP6 constitutes the amplifier architecture of cascade；The current source I3 mono- terminates the source of NMOS tube MN3, MN4
Pole, another termination GND provide tail current for the differential pair；The source electrode of the PMOS tube MP2 connects VDD, grid and drain electrode phase
Even, drain electrode connection current source I4 is followed by GND, and current source I4 provides bias current for PMOS tube MP2；PMOS tube MP2, MP4
Current mirror manner is connected into MP6, provides image current for PMOS tube MP4, MP6；The drain electrode of the PMOS tube MP6 connects NMOS
The drain electrode of pipe MN7 and the grid of PMOS tube MP7；The drain electrode of the source electrode connection NMOS tube MN6 of the NMOS tube MN7；The NMOS
The drain electrode of pipe MN5 connects the drain electrode of PMOS tube MP4, and grid is connected with drain electrode；The NMOS tube MN5 and MN6 connects into current mirror side
The source electrode of formula, NMOS tube MN5 and MN6 meets GND, and grid is followed by GND by capacitor C2；The capacitor C2 is to stablize capacitor；Institute
The source electrode for stating PMOS tube MP7 meets VDD, and drain electrode connection current source I5 is followed by GND, and bias current is provided by current source I5；It is described
It is connected across grid and the drain electrode of PMOS tube MP7 after capacitor C1 and resistance R1 series connection, as miller compensation, there is amplifier certain
Phase margin, systems stabilisation, the PMOS tube MP7 be efferent duct, drain electrode be track to track output circuit output port.
The resistance value of the R1-K1 array and R9-K5 array is equal and strictly matches, R17-K9 array and R22-K11 array
Resistance value it is equal and strictly match.Track to track output circuit is essentially a differential operational amplifier, therefore ratio track to track is defeated
The voltage gain of circuit is the resistance value of R9-K5 array divided by the resistance value of R22-K11 array out.When the input of input 1 and input 2 is total
When mould level, supply voltage, that is, VDD/2 that the output level of ratio track to track output circuit is 1/2.
Switch in the resistance and switch arrays can blow the modes such as resistance by fuse opening resistance, laser and realize.
The quantity of the resistance and switch arrays can be done according to the actual demand of product to be increased and decreased, to realize different sensitivity.The electricity
The number of resistance in resistance and switch arrays can be modified by the mask of chip die production process.Chopper amplification in Fig. 1
This method can also be used inside device and realize variable gain, realize the bigger adjustment of Hall sensor sensitivity.
It is to be illustrated to the preferable implementation of the utility model, but the invention is not limited to the reality above
Example is applied, those skilled in the art can also make various equivalent variations on the premise of without prejudice to spirit of the invention or replace
It changes, these equivalent deformations or replacement are all included in the scope defined by the claims of the present application.
Claims (7)
1. a kind of adjustable track to track of sensitivity exports linear hall sensor circuit, it is characterised in that: including Hall element,
Sampling hold circuit, chopper amplification circuit, dynamic offset cancellation circuit, low-pass filter circuit, sensitivity control circuit and ratio
Track to track output circuit；The Hall element use CMOS technology, can single-chip integration, with N-type semiconductor silicon materials realize, be used for
Magnetic strength induction signal outside induction；The sampling hold circuit carries out sampling holding to the magnetic signal of Hall element, and modulates magnetic
Inductive signal；The chopper amplification circuit carries out chopper amplification to the faint magnetic signal of the output of sampling hold circuit, demodulates magnetic strength
Induction signal, and eliminate noise；The dynamic offset cancellation circuit carries out offset voltage to the output signal of chopper amplification circuit
It eliminates；The high-frequency signal and burr generated in the low-pass filter circuit filtering circuit signal processing；The sensitivity control
The gain of circuit control ratio track to track output circuit processed, to realize the sensitive of adjustment hall sensing circuit；The ratio rail
The fixed gain of magnetic strength induction signal and the output of track to track are realized to rail output circuit.
2. the adjustable track to track of a kind of sensitivity according to claim 1 exports linear hall sensor circuit, special
Sign is: the ratio track to track output circuit is made of several resistance and switch arrays and track to track output circuit；It is described
Resistance and switch arrays include R1-K1 array, R9-K5 array, R17-K9 array and R22-K11 array；The R1-K1 array packet
Include resistance R1, R2, R3, R4, R5, R6, R7, R8 being cascaded and switch K1 in parallel with resistance R5, R6, R7, R8 respectively,
K2, K3, K4, the supply voltage VDD/2 of the termination of R1-K1 array one 1/2, other end connect the just defeated of track to track output circuit
Enter to hold INP；The R9-K5 array includes resistance R9, R10, R11, R12, R13, R14, R15, the R16 being cascaded and difference
Switch K5, K6, K7, K8 in parallel with resistance R13, R14, R15, R16, R9-K5 array one end connect track to track output circuit
Negative input end INN, other end connects the output end of track to track output circuit；The R17-K9 array include respectively with resistance
Resistance R17, R18, R19, R20, R21 of R17, R18 concatenated switch K9, K10 and parallel connection, the R17-K9 array one terminates defeated
Enter 1 port, other end meets the positive input terminal INP of track to track output circuit；The R22-K11 array include respectively with resistance
Resistance R22, R23, R24, R25, R26 of R25, R26 concatenated switch K11, K12 and parallel connection, the R22-K11 array one terminate
2 ports are inputted, other end meets the negative input end INN of track to track output circuit.
3. the adjustable track to track of a kind of sensitivity according to claim 2 exports linear hall sensor circuit, special
Sign is: the track to track output circuit includes current source I1, I2, I3, I4, I5, NMOS tube MN1, MN2, MN3, MN4, MN5,
MN6, MN7, PMOS tube MP1, MP2, MP3, MP4, MP5, MP6, MP7 and capacitor C1, C2；The current source I1 be NMOS tube MN1,
MN2 provides bias current, a termination VDD, the drain electrode of another termination NMOS tube MN1；NMOS tube MN1, MN2 is connected into two poles
Pipe connection type, i.e. drain and gate link together, the drain electrode of the source electrode connection NMOS tube MN2 of NMOS tube MN1, NMOS tube
The source electrode of MN2 meets GND；NMOS tube MN1, MN7 connects into current mirror manner, provides image current for MN7；The current source
I2 mono- terminates GND, and the drain electrode of another termination PMOS tube MP1 provides bias current for PMOS tube MP1；The grid of the PMOS tube MP1
Pole is connected with drain electrode, and described PMOS tube MP1, MP3 and MP5 connect into current mirror manner, provides mirror image electricity for PMOS tube MP3, MP5
Stream, the source electrode of PMOS tube MP1, MP3 and MP5 meet VDD, and the drain electrode of the PMOS tube MP3 meets the source electrode of PMOS tube MP4, PMOS
The drain electrode of pipe MP5 connects the source electrode of PMOS tube MP6；The NMOS tube MN3 and MN4 is differential pair, and input terminal INN and INP are rail pair
Rail exports the negative input end and positive input terminal of electric current, and the drain electrode of NMOS tube MN3 and MN4 connect the source of PMOS tube MP4 and MP6 respectively
Pole constitutes the amplifier architecture of cascade；The current source I3 mono- terminates the source electrode of NMOS tube MN3, MN4, another termination
GND provides tail current for the differential pair；The source electrode of the PMOS tube MP2 meets VDD, and grid is connected with drain electrode, drain electrode connection electricity
Stream source I4 is followed by GND, and current source I4 provides bias current for PMOS tube MP2；Described PMOS tube MP2, MP4 and MP6 connect into electricity
Mirror mode is flowed, provides image current for PMOS tube MP4, MP6；The PMOS tube MP6 drain electrode connection NMOS tube MN7 drain electrode and
The grid of PMOS tube MP7；The drain electrode of the source electrode connection NMOS tube MN6 of the NMOS tube MN7；The drain electrode of the NMOS tube MN5 connects
The drain electrode of PMOS tube MP4, grid are connected with drain electrode；The NMOS tube MN5 and MN6 connects into current mirror manner, NMOS tube MN5 and
The source electrode of MN6 meets GND, and grid is followed by GND by capacitor C2；The capacitor C2 is to stablize capacitor；The source of the PMOS tube MP7
Pole meets VDD, and drain electrode connection current source I5 is followed by GND, and bias current is provided by current source I5；The capacitor C1 and resistance R1 string
Grid and the drain electrode of PMOS tube MP7 are connected across after connection, the PMOS tube MP7 is efferent duct, and drain electrode is track to track output circuit
Output port.
4. the adjustable track to track of a kind of sensitivity according to claim 2 exports linear hall sensor circuit, special
Sign is: the resistance value of the R1-K1 array and R9-K5 array is equal and strictly matches, R17-K9 array and R22-K11 array
Resistance value is equal and strictly matches.
5. the adjustable track to track of a kind of sensitivity according to claim 2 exports linear hall sensor circuit, special
Sign is: the quantity of the resistance and switch arrays can be done according to the actual demand of product to be increased and decreased, to realize different sensitivity.
6. the adjustable track to track of a kind of sensitivity according to claim 2 exports linear hall sensor circuit, special
Sign is: the number of the resistance in the resistance and switch arrays can be modified by the mask of chip die production process.
7. the adjustable track to track of a kind of sensitivity according to claim 2 exports linear hall sensor circuit, special
Sign is: the switch in the resistance and switch arrays can blow the modes such as resistance by fuse opening resistance, laser and realize.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821877138.XU CN209296010U (en) | 2018-11-14 | 2018-11-14 | A kind of linear hall sensor circuit of adjustable track to track output of sensitivity |
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| CN201821877138.XU CN209296010U (en) | 2018-11-14 | 2018-11-14 | A kind of linear hall sensor circuit of adjustable track to track output of sensitivity |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109341730A (en) * | 2018-11-14 | 2019-02-15 | 厦门安斯通微电子技术有限公司 | A kind of linear hall sensor circuit of adjustable track to track output of sensitivity |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109341730A (en) * | 2018-11-14 | 2019-02-15 | 厦门安斯通微电子技术有限公司 | A kind of linear hall sensor circuit of adjustable track to track output of sensitivity |
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Effective date of registration: 20220601 Address after: 361011 units 704, 705 and 706, 7th floor, Wanxiang international business center 2 South Building, No. 1694, Gangzhong Road, Xiamen area, China (Fujian) pilot Free Trade Zone, Xiamen, Fujian Patentee after: XIAMEN XINYIDAI INTEGRATED CIRCUIT Co.,Ltd. Address before: Unit 305, integrated circuit industrial base, No. 1702, Gangzhong Road, Huli District, Xiamen, Fujian 361011 Patentee before: XIAMEN ASTSEMI TECHNOLOGY CO.,LTD. |