CN209282209U - Semiconductor devices - Google Patents
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- CN209282209U CN209282209U CN201821576533.4U CN201821576533U CN209282209U CN 209282209 U CN209282209 U CN 209282209U CN 201821576533 U CN201821576533 U CN 201821576533U CN 209282209 U CN209282209 U CN 209282209U
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Abstract
The utility model discloses a kind of semiconductor devices.Wherein, the semiconductor devices includes semiconductor substrate；Passivation layer, setting is on a semiconductor substrate；Anode, the first extension and the second extension including main part and the connection main part, wherein side of the passivation layer far from the semiconductor substrate is arranged in the main part, first extension is through the passivation layer and partially protrudes into the semiconductor substrate, and dielectric layer is provided between end and the semiconductor substrate of first extension far from the main part, second extension is through the passivation layer and partially protrudes into the semiconductor substrate, and end of second extension far from the main part and the semiconductor substrate form Schottky contacts；Cathode forms Schottky contacts through the end face of the passivation layer and the cathode and the semiconductor substrate.
Description
Technical field
The utility model relates to technical field of semiconductors more particularly to a kind of semiconductor device structures.
Background technique
Schottky barrier diode is to utilize a kind of semiconductor devices made of metal contact semiconductor layer.Itself and tradition are anticipated
Semiconductor diode in justice is compared, and has the characteristics that reverse recovery time is extremely short, and therefore, Schottky barrier diode is answered extensively
For circuits such as Switching Power Supply, frequency converter, drivers.Gallium nitride material is third generation semiconductor material with wide forbidden band, due to its tool
Have big forbidden bandwidth, high electron saturation velocities, high breakdown electric field, higher heat-conductivity, it is corrosion-resistant and anti-radiation the features such as, become
Make the optimal material of shortwave opto-electronic device and high voltagehigh frequency rate high power device.To sum up, it is prepared using gallium nitride material
Schottky barrier diode combines the advantage of above-mentioned Schottky barrier diode and gallium nitride material, fast with switching speed,
, there is good development prospect in the advantages that field strength height and good thermal property in power rectifier market.
However traditional Schottky barrier diode structure reverse leakage is very big, the strongest place of electric field concentrates on anode side
Edge causes electric-field intensity distribution uneven, reduces the electric field strength of main schottky junction, reduces gallium nitride base (GaN-
Based) the pressure resistance of Schottky barrier diode affects the performance of gallium nitride based schottky barrier diode.For Schottky
This very big problem of structure reverse leakage, much researchs and proposes solution although having had at present, for example, by using schottky junction
Terminal etc., can reduce reverse current.But it is difficult to produce two pole of Schottky barrier of Low dark curient using COMS compatible technology
Pipe.
Utility model content
The utility model is big for Schottky barrier diode reverse leakage in the prior art, very using COMS compatible technology
Difficulty produces the technical problems such as the Schottky barrier diode of Low dark curient, proposes a kind of semiconductor device structure.
Specifically, a kind of semiconductor devices that the utility model embodiment proposes includes: substrate；Buffer layer is arranged in institute
It states on substrate；Side of the buffer layer far from the substrate is arranged in barrier layer；Passivation layer is arranged remote in the barrier layer
Side from the buffer layer；First anode contact hole through the passivation layer and protrudes into the barrier layer；Dielectric layer, setting
In side of the passivation layer far from the barrier layer and the first anode contact hole；Second plate contact hole, runs through
The dielectric layer, the passivation layer and protrude into the barrier layer；Anode, including the first metal layer and second metal layer, wherein institute
The first metal layer is stated side of the dielectric layer far from passivation layer is arranged in and extends to the first anode contact hole and institute
It states in second plate contact hole to cover the dielectric layer and the second plate that are located at first anode contact hole bottom
Contact hole bottom, the second metal layer is arranged on the first metal layer and the filling first anode contact hole and described
Second plate contact hole；The dielectric layer and the passivation layer are run through in cathode contacts hole；Cathode is arranged on the dielectric layer
And the filling cathode contacts hole；Field plate is arranged on the dielectric layer and between the anode and the cathode
In region.
On the other hand, one embodiment of the utility model proposes a kind of semiconductor devices, comprising: semiconductor substrate；It is blunt
Change layer, is arranged on the semiconductor substrate；First anode contact hole through the passivation layer and protrudes into described semiconductor-based
Plate；Dielectric layer is arranged in side and the first anode contact hole of the passivation layer far from the semiconductor substrate；The
The semiconductor substrate through the dielectric layer, the passivation layer and is protruded into two positive contact holes；Anode, including the first metal
Layer and second metal layer, wherein the first metal layer is arranged in side of the dielectric layer far from passivation layer and extends to
To cover the institute for being located at first anode contact hole bottom in the first anode contact hole and the second plate contact hole
Dielectric layer and second plate contact hole bottom are stated, the second metal layer is arranged on the first metal layer and filling institute
State first anode contact hole and the second plate contact hole；The dielectric layer and the passivation layer are run through in cathode contacts hole；Yin
Pole is arranged on the dielectric layer and fills the cathode contacts hole.
In one embodiment of the utility model, above-mentioned semiconductor substrate includes: substrate；Nitride buffer layer, setting
Over the substrate；And aluminium gallium nitride alloy barrier layer, side of the nitride buffer layer far from the substrate is set.
In one embodiment of the utility model, above-mentioned semiconductor device further includes field plate, and the field plate is arranged in institute
State the region on dielectric layer and between the anode and the cathode.
In one embodiment of the utility model, above-mentioned second metal layer, the cathode and the field plate are respectively more
Layer metal structure.
In one embodiment of the utility model, above-mentioned semiconductor device includes Schottky barrier diode, and described
Schottky barrier diode has the anode, the field plate and the cathode.
Another aspect, one embodiment of the utility model propose a kind of semiconductor devices, comprising: semiconductor substrate；It is blunt
Change layer, setting is on a semiconductor substrate；Anode, the first extension and second including main part and the connection main part extend
Portion, wherein side of the passivation layer far from the semiconductor substrate is arranged in the main part, first extension runs through
The passivation layer and partially protrude into the semiconductor substrate and first extension end and institute far from the main part
It states and is provided with dielectric layer between semiconductor substrate, second extension is through the passivation layer and partially protrudes into the semiconductor
The end of substrate and second extension far from the main part and the semiconductor substrate form Schottky contacts；Yin
Pole forms Schottky contacts through the end face of the passivation layer and the cathode and the semiconductor substrate.
In one embodiment of the utility model, aforesaid semiconductor substrate includes: substrate；Nitride buffer layer, setting
Over the substrate；And aluminium gallium nitride alloy barrier layer, side of the nitride buffer layer far from the substrate is set.
In one embodiment of the utility model, aforementioned semiconductor device further includes field plate, and the field plate is arranged in institute
State side of the passivation layer far from the semiconductor substrate and the region between the anode and the cathode.
In one embodiment of the utility model, aforesaid anode is made of the first quantity metal layer being laminated, the yin
Pole and the field plate are made of the second quantity metal layer being laminated, and first quantity is greater than second quantity.
The above-mentioned technical proposal of the utility model can have following one or more the utility model has the advantages that in the first metal layer
Lower section forms one layer of dielectric layer, this layer of dielectric layer can increase annode area, greatly reduces reverse leakage, and this layer is situated between
Matter layer can be with the grid of GaN HEMT (High Electron Mobility Transistor, high electron mobility transistor)
Dielectric layer is formed simultaneously, compatible with CMOS technology line；In addition, by setting field plate structure, to extend gallium nitride Ji Xiaote
The depletion region of base barrier diode, the balanced field distribution of gallium nitride based schottky barrier diode, to improve nitridation
The pressure-resistant performance of gallium base schottky barrier diode.
Detailed description of the invention
It, below will be to needed in embodiment description in order to illustrate more clearly of the technical solution of the utility model
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are merely some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of semiconductor device structure schematic diagram provided by the embodiment of the utility model；
Fig. 2 is another semiconductor device structure schematic diagram provided by the embodiment of the utility model；
Fig. 3 is another semiconductor device structure schematic diagram provided by the embodiment of the utility model；
Fig. 4 is another semiconductor device structure schematic diagram provided by the embodiment of the utility model.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, to the technical solution in the embodiments of the present invention into
Row clearly and completely describes, it is clear that described embodiment is only a part of the embodiment of the utility model, rather than complete
The embodiment in portion.Based on the embodiments of the present invention, those of ordinary skill in the art are not before making creative work
Every other embodiment obtained is put, is fallen within the protection scope of the utility model.
It should be noted that the specification and claims of the utility model and term " first " in above-mentioned attached drawing,
" second " etc. is to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that in this way
The term used is interchangeable under appropriate circumstances, so that the utility model embodiment described herein can be in addition to herein
Sequence other than those of diagram or description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that
Be to cover it is non-exclusive include, for example, containing the process, method, system, product or equipment of a series of steps or units not
Those of be necessarily limited to be clearly listed step or unit, but may include be not clearly listed or for these processes, side
Other intrinsic step or units of method, product or equipment.
As shown in Figure 1, it is a kind of structural schematic diagram of semiconductor devices 200 provided by the embodiment of the utility model, partly
Conductor device 200 is for example including gallium nitride based schottky barrier diode.
Specifically, semiconductor devices 200 includes: substrate 201, delays in the utility model first embodiment as shown in Figure 1
Rush layer 202, barrier layer 203, passivation layer 204, first anode contact hole 205, dielectric layer 206, second plate contact hole 207, sun
Pole 208, cathode contacts hole 211, cathode 212 and field plate 213.
Wherein, buffer layer 202 is arranged on substrate 201.One of buffer layer 202 far from substrate 201 is arranged in barrier layer 203
Side.Side of the barrier layer 203 far from the buffer layer 202 is arranged in passivation layer 204.First anode contact hole 205 is through passivation
Layer 204 and protrudes into barrier layer 203.Side and the first anode of the passivation layer 204 far from barrier layer 203 is arranged in dielectric layer 206
In contact hole 205.Second plate contact hole 207 is through dielectric layer 206, passivation layer 204 and protrudes into barrier layer 203.Anode 208 wraps
The first metal layer 209 and second metal layer 210 are included, wherein the first metal layer 209 is arranged in dielectric layer 206 far from passivation layer 204
Side and extend to and the first anode is located at covering in first anode contact hole 205 and second plate contact hole 207 contacts
207 bottom of dielectric layer 206 and second plate contact hole of 205 bottom of hole；Second metal layer 210 is arranged in the first metal layer 209
Upper and filling first anode contact hole 205 and second plate contact hole 207.Cathode contacts hole 211 is through dielectric layer 206 and passivation
Layer 204.Cathode 212 is arranged on dielectric layer 206 and filling cathode contacts hole 211.Field plate 213 be arranged on dielectric layer 206,
And in the region between anode 208 and cathode 212.
Wherein, the material of the substrate 201 in gallium nitride based schottky barrier diode is, for example, silicon, sapphire, silicon carbide
One of or it is well known to those skilled in the art other be suitble to growing gallium nitride materials substrate.The material example of buffer layer 202
Gallium nitride in this way.The material of barrier layer 203 is, for example, aluminium gallium nitride alloy.The material of passivation layer 204 is, for example, silicon nitride and aluminium oxide
One kind.The material of dielectric layer 206 is, for example, one of silicon nitride, silica and ethyl orthosilicate.First anode contact hole
205 and second plate contact hole 207 be, for example, strip groove.The material for the first metal layer 209 that anode 208 is included can be titanium
Metal layer or titanium nitride metal layer, the second metal layer 210 that anode 208 is included are multilayered structure, may include but unlimited
In the titanium coating, metallic aluminum, layer of titanium metal and the nitride metal titanium layer that stack gradually.Cathode 212 and field plate 213 and the second gold medal
Belonging to layer 210 is synchronous formation, and is multi-layer metal structure.In other words, anode 208 is by the first quantity metal layer for being laminated
It constitutes, cathode 212 and field plate 213 are made of the second quantity metal layer being laminated, and the first quantity is greater than second quantity.
A kind of manufacturing process for semiconductor devices 200 that the embodiments of the present invention provide can be with are as follows:
(a) using epitaxial growth technology, grown buffer layer 202 is, for example, gallium nitride on substrate 201 e.g. silicon substrate
Layer, it is, for example, aln layer that barrier layer 203 is then grown on buffer layer 202 using epitaxial growth technology.
(b) using but being not limited to chemical vapor deposition process deposit passivation layer 204 on barrier layer 203 is, for example, to nitrogenize
Silicon layer.
(c) coat photoresist in passivation layer 204, photoresist is exposed, develop obtain patterning photoresist layer, later with
Patterning photoresist layer is that mask etching passivation layer 204 and barrier layer 203 form first anode contact hole 205.
(d) dielectric layer 206 is formed on passivation layer 204 and in first anode contact hole 205, is coated on dielectric layer 206
Photoresist, photoresist is exposed, develop obtain patterning photoresist layer, later to pattern photoresist layer as mask etching medium
Layer 206, passivation layer 204 and barrier layer 203 are to form second plate contact hole 207.
(e) it is used in second plate contact hole 207 and on dielectric layer 206 but is not limited to magnetron sputtering membrane process deposition
Metal forms the first metal layer 209, and then the resist coating on the first metal layer 209 is exposed photoresist, developing obtains
Photoresist layer is patterned, removes anode region AZ shown in FIG. 1 as mask etching the first metal layer 209 to pattern photoresist layer later
Except the first metal layer, with obtain be located at anode region AZ in the first metal layer 209.
(f) resist coating on dielectric layer 206, then photoresist is exposed, develop obtain patterning photoresist layer, it
Afterwards to pattern photoresist layer as mask etching dielectric layer 206 and passivation layer 204, until the surface for exposing barrier layer 203, shape
At cathode contacts hole 211, and remove remaining patterning photoresist layer.
(g) use in dielectric layer 206, the first metal layer 209 in anode region AZ and cathode contacts hole 211 but
It is not limited to successively deposit titanium coating, metallic aluminum, layer of titanium metal and nitride metal titanium using the technique of electron beam evaporation metal
Layer, to form second metal layer 210；Then photoetching (namely resist coating, exposure, development etc.) is carried out to second metal layer 210
And etching technics, form anode 208, field plate 213 and cathode 212.
In conclusion semiconductor device structure (including gallium nitride based schottky barrier diode) provided in this embodiment,
It is provided with dielectric layer 206 in the surface of passivation layer 204 and first anode contact hole 205, increases the area of anode, greatly
Reverse leakage is reduced, which can be formed simultaneously with the gate dielectric layer of GaN HEMT, compatible with CMOS technology line；
Furthermore by the way that field plate 213 is arranged, to extend the depletion region of gallium nitride based schottky barrier diode, balanced electric field point
Cloth, reduces the electric field strength of main schottky junction, to improve the pressure resistance of gallium nitride based schottky barrier diode.
In addition, it is noted that field can also be not provided in above-mentioned gallium nitride based schottky barrier diode structure 200
Plate 213, such as semiconductor device structure schematic diagram shown in Fig. 2.
Fig. 3 is the structural schematic diagram that the utility model applies another semiconductor devices 70 that example provides, semiconductor devices 70
For example including gallium nitride based schottky barrier diode.
Specifically, as shown in figure 3, semiconductor devices 70 includes semiconductor substrate 701, passivation layer 702, first anode contact
Hole 703, dielectric layer 704, second plate contact hole 705, anode 706, cathode contacts hole 709 and cathode 710.
Wherein passivation layer 702 is arranged on semiconductor substrate 701.First anode contact hole 703 is through passivation layer 702 and stretches
Enter semiconductor substrate 701.Dielectric layer 704 is arranged in side and the first anode of the passivation layer 702 far from semiconductor substrate 701 and connects
In contact hole 703.Second plate contact hole 705 is through dielectric layer 704, passivation layer 702 and protrudes into semiconductor substrate 701.Anode 706
Including the first metal layer 707 and second metal layer 708, wherein the first metal layer 707 is arranged in dielectric layer 704 far from passivation layer
It 702 side and extends in first anode contact hole 703 and second plate contact hole 705 first anode is located at covering
705 bottom of dielectric layer 704 and second plate contact hole of 703 bottom of contact hole, second metal layer 708 are arranged in the first metal layer
On 707 and fill first anode contact hole 703 and second plate contact hole 705.704 He of dielectric layer is run through in cathode contacts hole 709
Passivation layer 702.Cathode 710 is arranged on dielectric layer 704 and filling cathode contacts hole 709.
Wherein, semiconductor substrate 701 may include silicon substrate, nitride buffer layer and aluminium gallium nitride alloy barrier layer, wherein
On the silicon substrate, the aluminum gallium nitride is arranged in the gallium nitride layer far from the silicon for the nitride buffer layer setting
The side of substrate.
Wherein the material of the passivation layer 702 in gallium nitride based schottky barrier diode is, for example, silicon nitride and aluminium oxide
It is a kind of.The material of dielectric layer 704 is, for example, one of silicon nitride, silica and ethyl orthosilicate.First anode contact hole 703
It is, for example, strip groove with second plate contact hole 705.The material for the first metal layer 707 that anode 706 is included can be titanium
Belong to layer or titanium nitride metal layer.The second metal layer 708 that anode 706 is included is multilayered structure, be can include but is not limited to
Titanium coating, metallic aluminum, layer of titanium metal and the nitride metal titanium layer stacked gradually.Cathode 710 is same with second metal layer 708
What step was formed, and be multi-layer metal structure.In other words, anode 706 is made of the first quantity metal layer being laminated, cathode
710 are made of the second quantity metal layer being laminated, and the first quantity is greater than second quantity.The semiconductor devices of the present embodiment
70 manufacturing process flow can refer to the manufacturing process flow mentioned in above-described embodiment, and details are not described herein.
In addition, it is noted that field plate also can be set in above-mentioned gallium nitride based schottky barrier diode structure；Institute
It states field plate (Fig. 3 is not drawn) and region on dielectric layer 704 and between anode 706 and cathode 710 is set.Field plate can be with
Include multi-layer metal structure identical with cathode 710.
In the present embodiment, the semiconductor devices comprising gallium nitride based schottky barrier diode, in passivation layer 702
On be provided with dielectric layer 704, greatly increase annode area, reduce reverse leakage；In addition, by setting field plate structure,
Balanced field distribution, reduces the electric field strength of main schottky junction, to improve gallium nitride based schottky barrier diode
Pressure resistance.
Fig. 4 is the structural schematic diagram of another semiconductor devices 40 provided by the embodiment of the utility model, semiconductor devices
40 for example including gallium nitride based schottky barrier diode.
Specifically, as shown in figure 4, semiconductor devices 40 includes semiconductor substrate 41, passivation layer 42, anode 43 and cathode
45。
Wherein passivation layer 42 is arranged on semiconductor substrate 41.Anode 43 includes main part 431 and connection main part 431
First extension 432 and the second extension 433.Wherein one of passivation layer 42 far from semiconductor substrate 41 is arranged in main part 431
Side.First extension 432 is through passivation layer 42 and partially protrudes into semiconductor substrate 41 and the first extension 432 far from main body
Dielectric layer 44 is provided between the end and semiconductor substrate 41 in portion 431.Second extension 433 is through passivation layer 42 and part is stretched
Enter the end of semiconductor substrate 41 and the second extension 432 far from main part 431 and semiconductor substrate 41 forms schottky junctions
Touching.Cathode 45 forms Schottky contacts through the end face 451 and semiconductor substrate 41 of passivation layer 42 and cathode 45.
Wherein, semiconductor substrate 41 for example may include: substrate, nitride buffer layer and aluminium gallium nitride alloy barrier layer, wherein
Gallium nitride layer is arranged on a semiconductor substrate, and side of the gallium nitride layer far from semiconductor substrate is arranged in aluminum gallium nitride.
The material of above-mentioned substrate can be one of silicon, sapphire and silicon carbide or well known to those skilled in the art
Other are suitble to the substrate of growing gallium nitride material.The material of passivation layer 42 can be one of silicon nitride and silica.Anode
43 can be and be made of the first quantity metal layer being laminated, and cathode 45 is made of the second quantity metal layer being laminated, and described
One quantity is greater than second quantity.Specifically, anode 43 may include titanium nitride metal layer, the titanium being cascading
The five-layer structures such as layer, metallic aluminum, layer of titanium metal and nitride metal titanium layer, the first metal layer and for example, in previous embodiment
The composite structure of two metal layers；Cathode 45 may include the titanium coating being cascading, metallic aluminum, layer of titanium metal and gold
Belong to the four-layer structures such as titanium nitride layer.The material of dielectric layer 44 can be one of silicon nitride, silica and ethyl orthosilicate.Half
The manufacturing process flow of conductor device 40 can refer to the manufacturing process flow mentioned in above-described embodiment, and details are not described herein.
In addition, it is noted that field plate also can be set in above-mentioned gallium nitride based schottky barrier diode structure；Institute
It states field plate (Fig. 4 is not drawn) and side of the passivation layer 42 far from semiconductor substrate 41 is set and between anode 43 and cathode 45
Region.Field plate is made of the metal layer being laminated, and can be identical with the metal layer for the stacking that cathode 45 is included.
In conclusion semiconductor device structure (including gallium nitride based schottky barrier diode) provided in this embodiment,
It is provided with dielectric layer 44 between the end and semiconductor substrate 41 of the first extension 432 of anode 43, greatly increases sun
Pole-face product, reduces reverse leakage；In addition, realize and channel is exhausted in the lower section of field plate by setting field plate, thus
Extend the depletion region of gallium nitride based schottky barrier diode, balanced field distribution reduces the electric field of main schottky junction
Intensity, to improve the pressure resistance of gallium nitride based schottky barrier diode.
Finally, it should be noted that above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；
Although the utility model is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that:
It is still possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is carried out etc.
With replacement；And these are modified or replaceed, various embodiments of the utility model technology that it does not separate the essence of the corresponding technical solution
The spirit and scope of scheme.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Substrate；
Buffer layer, setting is over the substrate；
Side of the buffer layer far from the substrate is arranged in barrier layer；
Side of the barrier layer far from the buffer layer is arranged in passivation layer；
First anode contact hole through the passivation layer and protrudes into the barrier layer but not through the barrier layer；
Dielectric layer is arranged in side and the first anode contact hole of the passivation layer far from the barrier layer；
Second plate contact hole through the dielectric layer, the passivation layer and protrudes into the barrier layer but not through the potential barrier
Layer；
Anode, including the first metal layer and second metal layer, wherein the first metal layer is arranged in the dielectric layer far from blunt
Change the side of layer and extend in the first anode contact hole and the second plate contact hole and is located at described the with covering
The dielectric layer in one positive contact hole bottom and second plate contact hole bottom, the second metal layer are arranged described
On the first metal layer and fill the first anode contact hole and the second plate contact hole；
The dielectric layer and the passivation layer are run through in cathode contacts hole；
Cathode is arranged on the dielectric layer and fills the cathode contacts hole；
Field plate is arranged in the region on the dielectric layer and between the anode and the cathode.
2. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Passivation layer is arranged on the semiconductor substrate；
First anode contact hole through the passivation layer and protrudes into the semiconductor substrate but not through the semiconductor substrate；
Dielectric layer is arranged in side and the first anode contact hole of the passivation layer far from the semiconductor substrate；
Second plate contact hole through the dielectric layer, the passivation layer and protrudes into the semiconductor substrate but not through described
Semiconductor substrate；
Anode, including the first metal layer and second metal layer, wherein the first metal layer is arranged in the dielectric layer far from blunt
Change the side of layer and extend in the first anode contact hole and the second plate contact hole and is located at described the with covering
The dielectric layer in one positive contact hole bottom and second plate contact hole bottom, the second metal layer are arranged described
On the first metal layer and fill the first anode contact hole and the second plate contact hole；
The dielectric layer and the passivation layer are run through in cathode contacts hole；
Cathode is arranged on the dielectric layer and fills the cathode contacts hole.
3. semiconductor devices according to claim 2, which is characterized in that the semiconductor substrate includes: substrate；Gallium nitride
Buffer layer, setting is over the substrate；And aluminium gallium nitride alloy barrier layer, it is arranged in the nitride buffer layer far from the substrate
Side.
4. semiconductor devices according to claim 2, which is characterized in that the semiconductor devices further includes field plate, described
The region on the dielectric layer and between the anode and the cathode is arranged in field plate.
5. semiconductor devices according to claim 4, which is characterized in that the second metal layer, the cathode and described
Field plate is respectively multi-layer metal structure.
6. semiconductor devices according to claim 4, which is characterized in that the semiconductor devices includes Schottky barrier two
Pole pipe, and the Schottky barrier diode has the anode, the field plate and the cathode.
7. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Passivation layer, setting is on a semiconductor substrate；
Anode, the first extension and the second extension including main part and the connection main part, wherein the main part is set
It sets in side of the passivation layer far from the semiconductor substrate, first extension is through the passivation layer and partially protrudes into
The semiconductor substrate but end not through the semiconductor substrate and first extension far from the main part and
It is provided with dielectric layer between the semiconductor substrate, second extension described is partly led through the passivation layer and partially protruding into
Structure base board but end not through the semiconductor substrate and second extension far from the main part is partly led with described
Structure base board forms Schottky contacts；
Cathode forms Schottky contacts through the end face of the passivation layer and the cathode and the semiconductor substrate.
8. semiconductor devices according to claim 7, which is characterized in that the semiconductor substrate includes: substrate；Gallium nitride
Buffer layer, setting is over the substrate；And aluminium gallium nitride alloy barrier layer, it is arranged in the nitride buffer layer far from the substrate
Side.
9. semiconductor devices according to claim 7, which is characterized in that the semiconductor devices further includes field plate, described
Side of the passivation layer far from the semiconductor substrate and the area between the anode and the cathode is arranged in field plate
Domain.
10. semiconductor devices according to claim 9, which is characterized in that the anode is by the first quantity metal for being laminated
Layer is constituted, and the cathode and the field plate be made of the second quantity metal layer being laminated, and first quantity is greater than described the
Two quantity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821576533.4U CN209282209U (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821576533.4U CN209282209U (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209282209U true CN209282209U (en) | 2019-08-20 |
Family
ID=67603701
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| CN201821576533.4U Active CN209282209U (en) | 2018-09-26 | 2018-09-26 | Semiconductor devices |
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| Country | Link |
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2018
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Effective date of registration: 20210205 Address after: 518000 s1704, building 17, merchants Garden City, Liuhe community, Pingshan street, Pingshan District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN JINGXIANG TECHNOLOGY Co.,Ltd. Patentee after: Suzhou Chenhua Semiconductor Technology Co.,Ltd. Address before: 518052 Room 201, building a, No.1 Qianhai 1st Road, Shenzhen Qianhai Shenzhen Hong Kong cooperation zone, Shenzhen City, Guangdong Province Patentee before: SHENZHEN JINGXIANG TECHNOLOGY Co.,Ltd. |