CN209266397U - The IDF lead frame of improved semiconductor product - Google Patents
The IDF lead frame of improved semiconductor product Download PDFInfo
- Publication number
- CN209266397U CN209266397U CN201920090577.4U CN201920090577U CN209266397U CN 209266397 U CN209266397 U CN 209266397U CN 201920090577 U CN201920090577 U CN 201920090577U CN 209266397 U CN209266397 U CN 209266397U
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- Prior art keywords
- pin
- chip
- area
- lead frame
- idf
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses the IDF lead frame of improved semiconductor product, including N column chipset, N >=1 is connected by the first dowel between adjacent two column chipset；Each column chipset includes two chip units, and each chip unit includes pin area and Chip Area, and is staggered between the pin in the pin area of two chip units of each column chipset, passes through the connection of corresponding second dowel between adjacent pin；The hidden pin of predetermined width is set between the adjacent pin of each chip unit, and the first end of hidden pin is fixed on the second dowel, and the second end of hidden pin extends to the Chip Area of chip unit and retains preset first gap with the edge of Chip Area.The utility model can greatly reduce machine maintenance cost by the improvement to traditional IDF lead frame, and the risk for solving during traditional IDF lead-frame packages that machine maintenance is at high cost, easily causes flanging etc..
Description
Technical field
The utility model relates to the lead frame of semiconductor product more particularly to a kind of IDF of improved semiconductor product
(full name are as follows: Inter-Digitated leadframe, lead interlock separate type lead frame) lead frame.
Background technique
The IDF lead frame that the prior art provides passes through the staggered of the Chip Area and pin for rationally designing chip, mentions
The high production efficiency of pin discrete device product.However, since there are bigger gap, existing skills between staggered pin
The pin discrete device product of art when being packaged technique needs that boss is arranged on mold, so that boss insertion frame connects
Blank space between muscle and Chip Area between the pin in region, to prevent from being filled into the blank space when resin is filled.But
Due to the size difference of its pin of the lead frame of different size, the of different sizes of the blank space between pin, boss can be made
It is also required to correspondingly be designed as different size of size, every kind of lead frame needs correspondence to design a kind of mold in this way.It that is to say
The embedded compatible of mold is poor, needs to design boss on different mold or mold for different prong sizes, while
Its pressure is also bigger when demoulding, it is easy to there are the risks such as flanging, the reliability and stability of molding become a big technical problem,
Increase the failure rate of pin discrete device product.
Utility model content
For overcome the deficiencies in the prior art, the purpose of this utility model is to provide the IDF of improved semiconductor product
The problems such as lead frame, the design for being able to solve traditional lead frame mold in molding is complicated, poor compatibility.
The purpose of this utility model adopts the following technical scheme that realization:
The IDF lead frame of improved semiconductor product, including N column chipset, N >=1 lead between adjacent two column chipset
Cross the connection of the first dowel；Each column chipset includes two chip units, and each chip unit includes pin area and Chip Area, and
And be staggered between the pin in the pin area of two chip units of each column chipset, between adjacent pin by corresponding the
The connection of two dowels；The hidden pin of setting predetermined width between the adjacent pin of each chip unit, the first of hidden pin
End is fixed on the second dowel, and the second end of hidden pin extends to the Chip Area of chip unit and protects with the edge of Chip Area
Stay preset first gap.
Further, the Chip Area is used for adhering chip；The pin area includes multiple pins, and each pin passes through
Lead is connect with chip.
Further, pin area includes fixing pin and terminal pins, and terminal pins are equipped on pin wire welding area, chip
Equipped with chip wire welding area；Wherein, fixing pin is fixedly connected with Chip Area, terminal pins pass through corresponding pin wire welding area and chip
Wire welding area is connected by lead.
Further, the cross section of the pin wire welding area of terminal pins is greater than the pin cross section of the terminal pins.
Further, there are the second gaps between hidden pin and adjacent pin, wherein the size in the second gap is
[0.1mm, 1.0mm].
Further, the size in the first gap is [0.05mm, 0.45mm].
Further, the shape of the hidden pin is strip, cylinder, circle, ellipse, triangle and does not advise
Then any one of shape.
Further, each chip unit further includes fixed area, and the Chip Area is set between fixed area and pin area.
Further, the fixed area is equipped with location hole.
Compared with prior art, the utility model has the beneficial effects that:
The utility model by being improved to traditional IDF lead frame, i.e., chip unit on the lead frames
Hidden pin is added between adjacent pin, the boss on mold to replace existing lead frame is embedded into each chip unit
Blank space between adjacent pin can be filled into the adjacent pin of each chip unit not only to avoid molding material when molding
Between the second dowel and patch area edge between gap, and also reduce embedded mould design required precision,
Applicability is extensive, and then reduces the damage of mold and reduce machine maintenance cost；Meanwhile mold is also reduced in swaged lead frame
The risk of flanging etc. is easy to produce when frame.
Detailed description of the invention
Fig. 1 is IDF lead frame structure schematic diagram provided by the utility model；
Fig. 2 is the scale diagrams of hidden pin in chip unit in Fig. 1；
Fig. 3 is the packaging technology process schematic diagram of traditional IDF lead frame；
Fig. 4 is the packaging technology process schematic diagram of IDF lead frame provided by the utility model；
Fig. 5 is device structure schematic diagram of traditional IDF lead frame in molding；
Fig. 6 is device structure schematic diagram of the IDF lead frame provided by the utility model in molding；
Fig. 7 is the rib cutting flow diagram of traditional IDF lead frame；
Fig. 8 is the rib cutting flow diagram of IDF lead frame provided by the utility model.
In figure: 1, fixed area；2, Chip Area；3, pin wire welding area；4, hidden pin；51, terminal pins；52, fixing pipe
Foot；6, boss；71, the first dowel；72, the second dowel；81, the first upper mold；82, the first lower mold；83, the second upper mold
Tool；84, the second lower mold；91, injecting glue push rod；92, resin；93, glue injection channel.
Specific embodiment
In the following, being described further in conjunction with attached drawing and specific embodiment to the utility model, it should be noted that
Under the premise of not colliding, it can be formed in any combination between various embodiments described below or between each technical characteristic new
Embodiment.
Embodiment one:
The utility model is improved on the basis of traditional IDF lead frame, that is to say: improved semiconductor produces
The IDF lead frame of product, including N column chipset, N >=1 are connected by the first dowel between adjacent two column chipset；Each column
Chipset includes two chip units, and each chip unit includes pin area and Chip Area, and two cores of each column chipset
It is staggered between the pin in the pin area of blade unit, passes through the connection of corresponding second dowel between adjacent pin.
The hidden pin of predetermined width is set between the adjacent pin of each chip unit, and the first end of hidden pin is fixed
On the second dowel, the second end of hidden pin extends to the Chip Area of chip unit and retains with the edge of Chip Area default
Gap.
Wherein, hidden pin is the specific mount structure that the utility model embodiment technical solution provides, the hidden pin
Pin in setting between chip unit is arranged together, and its main function is when carrying out molding technique, replaces existing
There is mold convexity in IDF lead frame, resin is prevented to be filled into the second dowel between the adjacent pin of chip unit
Gap between Chip Area.The hidden pin will be during cutting off the second dowel together in subsequent rib cutting technique
Excision, not will increase extra technique.By the way that hidden pin is arranged, the molding mold in molding technique does not need to be arranged convex
Platform, as long as the size of chip unit is identical, the difference of chip unit prong sizes will not influence the use of molding mold, improve
The compatibility of molding mold.Meanwhile it solving the problems, such as to demould flanging in molding technique.
Wherein, the width of hidden pin can be arranged according to the reasonable wide of chip unit pin, such as the pipe of chip unit
Foot width dimensions are bigger, then the distance between chip unit pin will be smaller, and the width dimensions of hidden pin accordingly subtract
It is small.Meanwhile retaining preset distance between the edge of hidden pin and the pin of chip unit, the preset distance is according to molding
Technique needs to be arranged, and is discharged to be conducive to the gas at pin during molding from the preset gap.Similarly, hidden
It covers pin second end and patch area edge retains pre-determined distance, the setting of the pre-determined distance is also to be conducive to paste during molding
The gas of section is discharged from the gap.
The IDF lead frame of improved semiconductor product provided by the utility model, as shown in Figure 1, a kind of preferred reality
It applies in mode, is provided with two rows of chip units altogether.
Wherein, the Chip Area 2 of each chip unit is used for adhering chip；Pin area is according to the rule of pin discrete device product
Lattice and need to be arranged multiple pins, each pin passes through lead and connect with chip.In addition, each chip further includes fixed area 1,
The fixed area 1 is fixedly connected with Chip Area 2.
Preferably, the pin in the pin area in the present embodiment includes 3, is divided into fixing pin 52 and terminal pins 51,
Middle fixing pin 52 is as shown in Figure 1, be the interim pins of each chip unit, other pins are terminal pins 51.Fixing pipe
Foot 52 is fixedly connected with Chip Area 2, and then when chip is pasted onto Chip Area 2, is electrically connected with chip.In addition, on fixed area 1
It is additionally provided with location hole, anchor leg frame when for encapsulating.
Terminal pins 51 are equipped with pin wire welding area 3, meanwhile, chip is equipped with chip wire welding area.In bonding wire craft, lead to
Welding lead between chip wire welding area and the pin wire welding area 3 of corresponding terminal pins 51 to each chip unit is crossed, so that core
Piece and pin and external circuit are electrically connected.
Further, the utility model is also by being greater than corresponding lead for the width of the pin wire welding area 3 of terminal pins 51
The width of pin 51, it is possible to increase the bonding area between pin wire welding area 3 and lead, it is easier to weld.
Further, the present embodiment in order to illustrate the distance between hidden pin 4, the pin adjacent with left and right of hidden pin 4,
The size of the distance between hidden pin 4 and Chip Area 2 etc., as shown in Fig. 2, the length of such as hidden pin 4 is set as 1.30mm,
Width is set as 0.85mm.Hidden pin 4 is set as at a distance from adjacent pin as 0.34mm with left and right.Hidden pin 4 and Chip Area 2
The distance at edge is set as 0.20mm.The size of above-mentioned all parts is understood according to the actual situation, such as according to the ruler of lead frame
Very little and pin size, which is made, to be adaptively changed.Preferably, for according to actual knowhow, hidden pin 4
The distance between pin adjacent with left and right can be set as [0.1mm, 1.0mm].And the distance between hidden pin 4 and fin edges
It can be set as [0.05mm, 0.45mm].
Preferably, the shape that the utility model is not directed to hidden pin 4 is limited, such as strip, cylinder, triangle
Shape, ellipse, circle or irregular shape (for example the both ends of hidden pin are chamfering) etc..
Embodiment two:
Based on the IDF lead frame of improved semiconductor product provided by the utility model, the utility model also proposes one
The corresponding packaging method of kind, which includes patch step, bonding wire step, molding step, plating step and rib cutting step.
As shown in Figures 3 and 4, wherein Fig. 3 indicates that the packaging method flow diagram of traditional IDF lead frame, Fig. 4 are to indicate this reality
With the packaging method flow diagram of the IDF lead frame of novel offer.It is found that changing due to lead frame from Fig. 3 and Fig. 4
Into the molding step, rib cutting step in packaging method are significantly different, and specific packaging method is as follows:
Patch step: chip is pasted on to the Chip Area of lead frame.Due to not only only one core on lead frame
Blade unit, therefore in patch, it is the Chip Area for each chip unit being pasted on multiple chips respectively in lead frame.
Bonding wire step: chip is passed through respective tube by the bonding wire between pin wire welding area of the chip wire welding area with corresponding pin
Foot is connect with external circuit.It that is to say, by the pipe of the chip wire welding area of the Chip Area of each chip unit and each terminal pins
Bonding wire between foot wire welding area.
Molding step: molding is carried out to lead frame.Lead frame is packaged using molding material, forms pin weldering
The molding body that line area, bonding wire and Chip Area are wrapped up by molding material.By molding, prevent chip, bonding wire etc. by external object
Reason and/or chemical attack etc..Such as by carrying out molding to lead frame with epoxy resin.
As shown in Figure 5 and Figure 6, based on the IDF lead frame of improved semiconductor provided by the utility model, due to each
It is provided with hidden pin between the adjacent pin of chip unit, to replace the work of mold convex platform in existing IDF lead frame
With, come prevent molding material to be filled between the adjacent pin of chip unit the second dowel and patch between gap.Than
As shown in figure 5, traditional molding block schematic illustration: in molding by by lead frame setting in the first upper mold 81 and the
Once among mold 82, by the way that under the action of injecting glue push rod 91, resin 92 is imported the first upper mold by glue injection channel 93
81, the first lower mold 82 and lead frame are formed by cavity, carry out molding to lead frame；Under first on mold 82
There are boss 6, are embedded between the adjacent pin of each chip unit, such as between terminal pins 51 and fixing pin 52,
It is spilt between the second dowel of the adjacent pin and Chip Area come resin when preventing molding.
And as shown in fig. 6, the molding block schematic illustration of lead frame provided by the utility model: in molding by that will draw
Wire frame is arranged under the second upper mold 83 and second among mold 84, by under the action of injecting glue push rod 91, by resin 92
The lower mold 84 of the second upper mold 83, second is imported by glue injection channel 93 and lead frame is formed by cavity, to lead
Frame carries out molding；Hidden pin 4 is provided between the adjacent pin of each chip of lead frame to replace traditional mould
Boss on tool, for example be arranged between terminal pins 51 and fixing pin 52, it is adjacent that this is spilt into come resin when preventing molding
Between second dowel of pin and Chip Area.
Therefore, for for the IDF lead frame of improved semiconductor product provided by the utility model, in molding,
There is no need to which corresponding boss is arranged to be embedded between the adjacent pin of each chip unit on mold, due to not needing in mold
The corresponding boss of upper setting is embedded between corresponding adjacent pin, only needs to can be realized using suitable clamping pressure in molding
Molding, meanwhile, the contact area between lead frame and mold is also reduced, so that demoulding is easier.
In addition, due to existing centainly between hidden pin and adjacent pin, between hidden pin and patch area edge
Gap can carry out good exhaust by these gaps in molding.
Plating step: lead frame is carried out tin plating.In plating, in addition to by the part of molding material package, lead frame
Other exposed metals of frame carry out tin plating, and the solderability of lead frame can be enhanced in this way, be easy to be installed in printing
On circuit board, while pin and the anticorrosive property at other positions can be improved.
Rib cutting step: removal procedure is carried out to the dowel on lead frame, and then by the chip unit on lead frame
Separation.As Fig. 7, Fig. 8 are respectively shown in traditional IDF lead frame, IDF lead frame provided by the utility model in rib cutting process
Schematic diagram.It is adjacent due to each chip unit in the IDF lead frame of improved semiconductor provided by the utility model
There are hidden pins between pin, therefore as shown in figure 8, while cutting off the second dowel on lead frame, it is also necessary to
Hidden pin between adjacent pin is cut off together.It that is to say: first between the adjacent pin of excision one single chip unit
Second dowel, while the hidden pin between adjacent pin is cut off together, other companies on lead frame are then cut off again
The first dowel between muscle, such as adjacent two column chipset is connect, and then completes the separation of chip unit.
Preferably due in lead frame provided by the utility model between hidden pin and adjacent pin there are gap,
There are gaps between hidden pin and patch area edge, and a small amount of molding material is had in molding and is overflowed, and connect in excision second
When connecing muscle, boss, excessive glue can also be cut off.In addition, have excessive glue etc. on the chip unit after separation in order to prevent, the packaging method
Deburring step can also be increased after molding step, for example unhairing is carried out to the lead frame after molding by giant
Thorn processing, for example extra excessive glue removed etc..
Above embodiment is only preferred embodiments of the present invention, cannot be protected with this to limit the utility model
Range, the variation of any unsubstantiality that those skilled in the art is done on the basis of the utility model and replacement belong to
In the utility model range claimed.
Claims (9)
1. the IDF lead frame of improved semiconductor product, which is characterized in that including N column chipset, N >=1, adjacent two column core
It is connected between piece group by the first dowel；Each column chipset includes two chip units, and each chip unit includes pin area
And Chip Area, and be staggered, between adjacent pin between the pin in the pin area of two chip units of each column chipset
It is connected by corresponding second dowel；The hidden pin of predetermined width is set between the adjacent pin of each chip unit, it is hidden
The first end for covering pin is fixed on the second dowel, the second end of hidden pin extend to the Chip Area of chip unit and with patch
The edge of section retains preset first gap.
2. the IDF lead frame of improved semiconductor product according to claim 1, which is characterized in that use the Chip Area
In adhering chip；The pin area includes multiple pins, and each pin passes through lead and connect with chip.
3. the IDF lead frame of improved semiconductor product according to claim 2, which is characterized in that pin area includes solid
Determine pin and terminal pins, terminal pins are equipped with pin wire welding area, chip is equipped with chip wire welding area；Wherein, fixing pin
It is fixedly connected with Chip Area, terminal pins are connect with chip wire welding area by lead by corresponding pin wire welding area.
4. the IDF lead frame of improved semiconductor product according to claim 3, which is characterized in that the pipe of terminal pins
The cross section of foot wire welding area is greater than the pin cross section of the terminal pins.
5. the IDF lead frame of improved semiconductor product according to claim 1, which is characterized in that hidden pin and phase
There are the second gaps between adjacent pin, wherein the size in the second gap is [0.1mm, 1.0mm].
6. the IDF lead frame of improved semiconductor product according to claim 1, which is characterized in that the first gap it is big
Small is [0.05mm, 0.45mm].
7. the IDF lead frame of improved semiconductor product according to claim 1, which is characterized in that the hidden pin
Shape be strip, cylinder, circle, ellipse, triangle and irregular shape any one.
8. the IDF lead frame of improved semiconductor product according to claim 1, which is characterized in that each chip unit
It further include fixed area, the Chip Area is set between fixed area and pin area.
9. the IDF lead frame of improved semiconductor product according to claim 8, which is characterized in that on the fixed area
Equipped with location hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920090577.4U CN209266397U (en) | 2019-01-18 | 2019-01-18 | The IDF lead frame of improved semiconductor product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920090577.4U CN209266397U (en) | 2019-01-18 | 2019-01-18 | The IDF lead frame of improved semiconductor product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209266397U true CN209266397U (en) | 2019-08-16 |
Family
ID=67584744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920090577.4U Active CN209266397U (en) | 2019-01-18 | 2019-01-18 | The IDF lead frame of improved semiconductor product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209266397U (en) |
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2019
- 2019-01-18 CN CN201920090577.4U patent/CN209266397U/en active Active
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