CN209216923U - Fan-out-type wafer level packaging structure - Google Patents

Fan-out-type wafer level packaging structure Download PDF

Info

Publication number
CN209216923U
CN209216923U CN201822031402.4U CN201822031402U CN209216923U CN 209216923 U CN209216923 U CN 209216923U CN 201822031402 U CN201822031402 U CN 201822031402U CN 209216923 U CN209216923 U CN 209216923U
Authority
CN
China
Prior art keywords
layer
bare die
pin
thickness
fan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201822031402.4U
Other languages
Chinese (zh)
Inventor
范增焰
吕开敏
全昌镐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN201822031402.4U priority Critical patent/CN209216923U/en
Application granted granted Critical
Publication of CN209216923U publication Critical patent/CN209216923U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

There is provided a kind of fan-out-type wafer level packaging structure, comprising: bare die, pre-hardening thickness reroute layer, multiple spherical pins and cured layer.Bare die has pin；Pre-hardening thickness covers and coats bare die, and the pin side of bare die exposes pre-hardening thickness surface；It reroutes layer and is formed in the side that the pin of the bare die exposes, rerouting layer includes passivation layer and metal layer；Multiple spherical shape pins are formed on the rewiring layer, and spherical pin is electrically connected by metal layer with the pin of bare die；Cured layer is formed in pre-hardening thickness far from the side for rerouting layer, and cured layer covers the pre-hardening thickness；Cured layer has different thermal expansion coefficients, cured layer and bare die thermal expansion coefficient having the same from pre-hardening thickness.The encapsulating structure of the utility model on pre-hardening thickness by adding one layer of cured layer, and the warpage of wafer, reduces subsequent technique difficulty during reducing in fan-out-type wafer-level packaging technique, while also reducing the warpage of the encapsulating structure after cutting.

Description

Fan-out-type wafer level packaging structure
Technical field
The utility model relates to semiconductor chip packaging fields, in particular to a kind of fan-out-type wafer-level packaging knot Structure.
Background technique
In the development of dynamic random access memory (DRAM, Dynamic Random Access Memory) preparation process In the process, DRAM is sealed with window spherical shape matrix arrangement (WBGA, Windows-Ball Grid Array) mode in the related technology Assembling structure 100 (as shown in Figure 1A) is packaged, including bare die 101, plastic packaging layer 102 and pin 103.It is naked for opening 110 The design of bond pad locations on piece 101 has strict demand, and needs to be mutually matched with the manufacturing capacity of plant substrate.In addition, adopting It is needed with the DRAM encapsulating structure of WBGA mode through board transport signal, the thickness and the gold in substrate of DRAM encapsulating structure Belonging to wiring line has strict demand.
Fan-out-type wafer level packaging structure (as shown in Figure 1B) in the related technology, including bare die 101', plastic packaging layer 102' And spherical pin 103'.Due to, the thermal expansion coefficient difference of plastic packaging layer and bare die is larger, causes after forming plastic packaging layer, Structure is integrally also easy to produce warpage, increases the difficulty to be formed and reroute layer and spherical pin technique.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
In view of the above problem, the utility model provides a kind of fan-out-type wafer level packaging structure, and then to a certain degree The warpage issues of the upper bottleneck for solving substrate design and fan-out-type wafer level packaging structure.
The utility model provides a kind of fan-out-type wafer level packaging structure, comprising: bare die, reroutes layer, is more at pre-hardening thickness A spherical shape pin and cured layer.Bare die has pin；Pre-hardening thickness covers and coats bare die, and the pin side of bare die is sudden and violent Expose pre-hardening thickness surface；It reroutes layer and is formed in the side that the pin of bare die exposes, rerouting layer includes passivation layer and gold Belong to layer；Multiple spherical shape pins, which are formed in, to reroute on layer, and spherical pin is electrically connected by metal layer with the pin of bare die；Cured layer Pre-hardening thickness is formed in far from the side for rerouting layer, covers pre-hardening thickness；Wherein cured layer has different from pre-hardening thickness Thermal expansion coefficient, and cured layer and bare die thermal expansion coefficient having the same.
In some embodiments of the utility model, pre-hardening thickness is epoxy-plastic packaging material, and cured layer is silicon wafer.
In some embodiments of the utility model, the thickness of pre-hardening thickness is 200~250 μm.
In some embodiments of the utility model, the thickness of cured layer is 200~400 μm.
In some embodiments of the utility model, bare die is dynamic random access memory.
The beneficial effects of the utility model are, replace the processing procedures such as substrate design, the patch in conventional package, can be improved Encapsulating structure transmission performance, and encapsulating structure size is reduced, evade the bottleneck of substrate design in traditional WBGA packaged type. Also, the encapsulating structure of the utility model applies one layer of cured layer by pre-hardening thickness more, reduces in fan-out-type wafer In grade packaging technology, especially formed reroute layer and during soldered ball pin wafer warpage, reduce subsequent technique Difficulty, while the warpage of the encapsulating structure after cutting is also reduced, be conducive to subsequent packaging technology again.
Detailed description of the invention
Figure 1A is the schematic diagram of the DRAM encapsulating structure of the WBGA mode of the prior art.
Figure 1B is the schematic diagram of fan-out-type wafer level packaging structure conventional in the prior art.
Fig. 1 C is that there is a situation where warpage schematic diagrames for fan-out-type wafer level packaging structure conventional in the prior art.
Fig. 2A-Fig. 2 I is shape of the fan-out-type wafer level packaging structure of the utility model in each step of manufacturing process State schematic diagram.
Fig. 3 is fan-out-type wafer scale made of the manufacturing process using the fan-out-type wafer level packaging structure of the utility model Encapsulating structure.
Fig. 4 is the process signal of one embodiment of the manufacturing process of the fan-out-type wafer level packaging structure of the utility model Figure.
Specific embodiment
It is to illustrate related " fan-out-type wafer-level packaging knot disclosed in the utility model by specific specific example below The advantages of embodiment of structure ", those skilled in the art can understand the utility model by content disclosed in this specification and effect Fruit.The utility model can be implemented or be applied by other different specific embodiments, the various details in this specification It can carry out various modifications and change under the design for not departing from the utility model based on different viewpoints and application.Implementation below Mode will be explained in further detail the relevant technologies content of the utility model, but disclosure of that is not practical to limit Novel protection scope.
The utility model provides one kind and is fanned out to formula fan-out-type wafer level packaging structure, referring to Fig. 3.As shown in Figure 3, it is fanned out to Type wafer level packaging structure 300 includes: bare die 301, and pre-hardening thickness 302 reroutes layer 305, spherical pin 303 and cured layer 304.Rerouting layer 305 includes passivation layer and metal layer.Pre-hardening thickness 302 is generally epoxy-plastic packaging material, and pre-hardening thickness 302 covers And bare die 301 is coated, and the pin side of bare die 301 exposes the surface of pre-hardening thickness 302.Layer 305 is rerouted to be formed in The side that the pin of bare die 301 exposes on pre-hardening thickness 302 is connected with the pin of bare die 301.Multiple spherical shape 303 shapes of pin At on rewiring layer 305.Cured layer 304 is formed in side of the pre-hardening thickness far from rewiring layer, and precuring is completely covered Layer 302.Cured layer 304 has different thermal expansion coefficients from pre-hardening thickness 302, and cured layer 304 and bare die 301 are having the same Thermal expansion coefficient.
The fan-out-type wafer level packaging structure is with traditional WBGA encapsulating structure main distinction encapsulated, at EMC layers Cured layer different from EMC thermal expansion coefficient and identical with bare die thermal expansion coefficient is applied on (pre-hardening thickness in the disclosure). EMC layers of leading precuring carry out secondary curing after cured layer to be fit again.Due to bilayer solidification, packaging technology and biography Fan-out-type wafer-level packaging technique of uniting is also different.The arrangement of bare die 201/301 first is to be applied with adhesive by being bonded in one It is realized on 207 surface of support wafer layer of layer 208.EMC is pasted by adhesive phase 208 to support 207 table of wafer layer later Face, covers and coats previously bonding multiple single bare dies 201/301, when carrying out one section under the conditions of the temperature, pressure of setting Between, complete precuring.EMC after precuring is in the form of a solid colloid.Cured layer 204 is pasted to pre- after the completion of precuring 202 surface of cured layer, is completely covered pre-hardening thickness 202, and a period of time is carried out under the conditions of the temperature, pressure of setting, completes solid Change.And after hardening, removal support wafer layer and adhesive phase, then be laid with and reroute layer and plant ball, polishing, cutting Equal subsequent steps.
In some preferred embodiments, select silicon wafer as cured layer 304.Those skilled in the art can also be according to reality Border needs, and selects other materials as cured layer.The thickness of cured layer 304 is preferably 200~400 μm.Pre-hardening thickness 302 Thickness is preferably 200~250 μm.Those skilled in the art can select corresponding thickness according to actual needs, to meet encapsulation mark It is quasi-.
In some embodiments, above-mentioned fan-out-type wafer level packaging structure is the encapsulation knot of dynamic random access memory Structure, that is, bare die 301 is dynamic random access memory.
The beneficial effect of such fan-out-type wafer level packaging structure is, replaces substrate design, the patch in conventional package Equal processing procedures can be improved encapsulating structure transmission performance, and reduce encapsulating structure size, evade in traditional WBGA packaged type The bottleneck of substrate design.Also, the encapsulating structure of the utility model applies one layer of cured layer by pre-hardening thickness more, reduces In the fan-out-type wafer-level packaging technique, especially formed reroute layer and soldered ball pin during wafer warpage, Subsequent technique difficulty is reduced, while also reducing the warpage of the encapsulating structure after cutting, is conducive to subsequent packaging technology again.
A kind of manufacturing process of above-mentioned fan-out-type wafer level packaging structure is also disclosed in the utility model.A- Fig. 2 I referring to fig. 2 And Fig. 4.Fig. 2A-Fig. 2 I is shape of the fan-out-type wafer level packaging structure of the utility model in each step of manufacturing process State schematic diagram.Manufacturing process carries out on an element 200 to be processed.Specific step is as follows:
Step S101. provides support wafer layer, forms adhesive phase in support wafer layer.
As shown in Figure 2 A, a support wafer layer 207 is provided, bonding is applied on a side surface of support wafer layer 207 Agent, to form adhesive phase 208.Support 207 surface of wafer layer will be completely covered in adhesive phase 208.Then alignment mark is carried out, By bare die specification, it is spaced identical preset distance and multiple alignment marks is set.Support wafer layer 207 can choose as transparent glass Or silicon wafer, supporting in wafer layer 207 has notch label, and adhesive phase 208 can be silica gel, and those skilled in the art can root Suitable material is selected according to actual needs.
Multiple bare dies are bonded to adhesive layer surface by step 102..
As shown in Figure 2 B, multiple single bare dies 201 of preparatory well cutting are bonded to 208 surface of adhesive phase, according to Each bare die 201 is bonded to designated position and forms scheduled arrangement by previous alignment mark.Bare die has pin, and pin is in face of viscous Mixture layer surface.Spacing distance of the spacing distance between 80~120 μm, such as bare die 201 between bare die 201 is 90 μm, 100 μm Or 110 μm.The disclosure is not particularly limited this.
Step S103. forms pre-hardening thickness far from the side of support wafer layer in adhesive phase and bare die.
As shown in Figure 2 C, epoxy-plastic packaging material (EMC) layer is bonded to support wafer layer surfaces by adhesive phase, forms one Pre-hardening thickness 202.Pre-hardening thickness 202 covers previously bonding multiple single bare dies 201.Specifically, pre-cure step S103 It carries out, first pastes EMC layers to support 207 surface of wafer layer by adhesive phase 208, covering is simultaneously in a vacuumizing room The previously bonding multiple single bare dies 201 of cladding.EMC layers are covered under the conditions of 100~120 DEG C, complete in 1min.It protects later Under conditions of holding 100~120 DEG C, 0.5~1.5h of precuring completes the precuring of epoxy-plastic packaging material.One in the disclosure is real It applying in mode, EMC layers paste completion at 110 DEG C, then at 110 DEG C, precuring 1h.Epoxy-plastic packaging material after precuring is in one The form of solid colloid.Pre-hardening thickness thickness can be 200~250 μm, for example, pre-hardening thickness thickness can be 210 μm, 220 μ M, 230 μm or 240 μm.Those skilled in the art can select suitable thickness according to actual needs, and the disclosure is without limitation. Can be by bottom-up observation, i.e., from support wafer layer 207 to from 202 direction of pre-hardening thickness in procuring process, bare die 201 There is no bubble presence between the EMC of bare die 201 with forming pre-hardening thickness and coating, i.e., it is believed that pre-cure step is completed.
Step S104. forms cured layer far from the side of support wafer layer in pre-hardening thickness.
As shown in Figure 2 D, cured layer 204, cured layer are formed far from the one side of support wafer layer 207 in pre-hardening thickness 202 204 are completely covered pre-hardening thickness 202, are then solidified.In some preferred embodiments, select silicon wafer as cured layer 202.Those skilled in the art can also select other materials as cured layer according to actual needs.Curing schedule S104 It is carried out in above-mentioned vacuumizing room, cured layer 204 is pasted to 202 surface of pre-hardening thickness, pre-hardening thickness 202 is completely covered, Under the conditions of 150~200 DEG C, about 1~3h is maintained, that is, completes solidification.For example, solidifying 2h under the conditions of 180 DEG C.Cured layer thickness It can be 750~850 μm, such as cured layer thickness can be 800 μm.Those skilled in the art can select to close according to actual needs Suitable thickness.The volatile matter not volatilized completely due to also there being part in the EMC in pre-cure step, cured layer such as silicon wafer Bonding can be formed when in piece attachment.Molding is fully cured after volatilizing completely in object to be evaporated.It is formed on the surface of pre-hardening thickness solid Change layer and reduce the warpage of full wafer wafer in this way because cured layer is identical with the thermal expansion coefficient of bare die, reduces and be subsequently formed weight The technology difficulty of wiring layer and spherical pin.
Step S105. removal support wafer layer and adhesive phase.It is as shown in Figure 2 E, removal support wafer layer 207 and Adhesive phase 208, so that the pin 2011 for arranging well laid bare die 201 in pre-hardening thickness 202 is exposed.Later, to exposing The bare die 201 come is cleaned, it is ensured that 2011 surface of pin of bare die 201 does not have adhesive phase residual.
Step S106. is formed in a side surface of the pin for exposing bare die and is rerouted layer.
As shown in Figure 2 F, the first passivation layer is deposited in the side surface that pre-hardening thickness 202 exposes bare die pin 2011, Then groove is formed by photoetching, development and engraving method, groove exposes bare die pin 2011, and gold is then deposited in groove Belong to, form metal layer, finally deposits the second passivation layer in layer on surface of metal and the first passivation layer surface, ultimately form rewiring layer 205.Rerouting layer includes the first passivation layer, the second passivation layer and metal layer.Deposit the side of the first passivation layer and the second passivation layer Method can be chemical vapor deposition or atomic layer deposition.The material of passivation layer can be polyimides (polyimide).Deposition gold The method for belonging to layer can be physical vapour deposition (PVD) or plating.The material of metal layer can be one of copper, aluminium, tungsten etc. or above-mentioned The alloy material of material.The disclosure is without limitation.
In an embodiment of the disclosure, the thickness of the first passivation layer and the second passivation layer is at 5~10 μm, for example, can Think 6 μm, 7 μm, 8 μm or 9 μm.The thickness of first passivation layer and the second passivation layer can be identical or different.The thickness of metal layer Between 3~5 μm, for example, can be 4 μm.The disclosure is without limitation.
Step S107. is in the spherical pin of formation on rewiring layer.
As shown in Figure 2 G, tin ball bonding is connected to and reroutes 205 surface of layer, is connected with the bare die pin 2011 exposed, Form spherical pin 203.In an embodiment of the disclosure, plant ball mode can from use plant ball device, template, brush soldering paste or It is selected according to actual needs in the method mounted by hand.
S108. polishing cured layer is to predetermined thickness.
As illustrated in figure 2h, using the method for mechanical polishing, cured layer is polished far from the one side of spherical pin, Cured layer 204 is set to be polishing to predetermined thickness, to meet encapsulation specification.The thickness of cured layer after polishing 200~400 μm it Between, for example, the thickness of cured layer can be 250 μm, 300 μm or 350 μm, those skilled in the art can select according to actual needs Select suitable thickness.The disclosure is without limitation.
S109. it cuts, forms fan-out-type wafer level packaging structure.
As shown in figure 2i, the element to be processed 200 for milled of fighting each other is measured, is marked, and is cut later according to label It cuts, such as arrow locations in Fig. 2 I.The mode of element 200 to be processed application laser or diamond cut is cut into as shown in Figure 3 The fan-out-type wafer level packaging structure 300 comprising single bare die.Those skilled in the art can also select it according to actual needs His cutting mode.Fan-out-type wafer level packaging structure 300 include single bare die 301, pre-hardening thickness 302, bare die pin 303, Cured layer 304 reroutes layer 305.
In some embodiments, which is used to manufacture the encapsulating structure of dynamic random access memory, that is, bare die 201/301 is dynamic random access memory.
In above-described process, in order to carry out subsequent step, and guarantee the electrical property of fan-out-type wafer level packaging structure, It needs to clean the die surfaces after removal adhesive phase and support layers of dies after removing support step S105.Usually going It after supporting step S105, is passivated before Route step S106, carries out cleaning step.It is using cleaning agent that adhesive phase and support is brilliant Lamella is in the removing residues on pre-hardening thickness surface, and the part for exposing bare die keeps cleaning, to guarantee electrical property.For example, Cleaning method can be selected as water for washing, detergent.
The above are the manufacturing process of the fan-out-type wafer level packaging structure of the utility model, which utilizes fan-out-type wafer Grade encapsulation technology, replaces the processing procedures such as substrate design, the patch in conventional package, can be improved fan-out-type wafer level packaging structure biography Defeated performance, and fan-out-type wafer level packaging structure size is reduced, evade the bottle of substrate design in traditional WBGA packaged type Neck.Also, the method for the utility model applies one layer of cured layer by pre-hardening thickness more, reduces and is being fanned out to formula wafer scale In packaging technology, especially formed reroute layer and during soldered ball pin wafer warpage, reduce subsequent technique hardly possible Degree, while the warpage of the fan-out-type wafer level packaging structure after cutting is also reduced, be conducive to subsequent packaging technology again.
The above are some embodiments of fan-out-type wafer level packaging structure provided by the utility model, pass through embodiment Explanation, it is believed that those skilled in the art can understand the technical solution of the utility model and its operation principles.However the above is only The preferred embodiment of the utility model, not limits the utility model.Those skilled in the art can be according to actual needs Technical solution provided to the utility model is appropriately modified, and makes an amendment and equivalent transformation is all without departing from the utility model institute Claimed range.The utility model interest field claimed, when being subject to appended claims.

Claims (5)

1. a kind of fan-out-type wafer level packaging structure characterized by comprising
Bare die, the bare die have pin；
Pre-hardening thickness, the pre-hardening thickness covers and coats the bare die, and the pin side of the bare die exposes The pre-hardening thickness surface；
Layer is rerouted, the rewiring layer is formed in the side that the pin of the bare die exposes, and the rewiring layer includes blunt Change layer and metal layer；
Multiple spherical shape pins, are formed on the rewiring layer, and the spherical shape pin passes through the metal layer and the bare die The pin electrical connection；And
Cured layer, the cured layer are formed in pre-hardening thickness far from the side for rerouting layer, and the cured layer covers institute State pre-hardening thickness；
The cured layer has different thermal expansion coefficients from the pre-hardening thickness, and the cured layer has phase with the bare die Same thermal expansion coefficient.
2. fan-out-type wafer level packaging structure according to claim 1, which is characterized in that the pre-hardening thickness is epoxy modeling Envelope material, the cured layer is silicon wafer.
3. fan-out-type wafer level packaging structure according to claim 1, which is characterized in that the thickness of the pre-hardening thickness is 200~250 μm.
4. fan-out-type wafer level packaging structure according to claim 1, which is characterized in that the thickness of the cured layer is 200~400 μm.
5. fan-out-type wafer level packaging structure according to claim 1, which is characterized in that the bare die is that dynamic random is deposited Store reservoir.
CN201822031402.4U 2018-12-05 2018-12-05 Fan-out-type wafer level packaging structure Active CN209216923U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201822031402.4U CN209216923U (en) 2018-12-05 2018-12-05 Fan-out-type wafer level packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201822031402.4U CN209216923U (en) 2018-12-05 2018-12-05 Fan-out-type wafer level packaging structure

Publications (1)

Publication Number Publication Date
CN209216923U true CN209216923U (en) 2019-08-06

Family

ID=67463030

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201822031402.4U Active CN209216923U (en) 2018-12-05 2018-12-05 Fan-out-type wafer level packaging structure

Country Status (1)

Country Link
CN (1) CN209216923U (en)

Similar Documents

Publication Publication Date Title
CN105047652B (en) The encapsulating structure and production method of semiconductor devices
CN206657808U (en) Electronic installation
EP3422398A1 (en) Silicon substrate embedded, fan-out, 3d package structure
CN105206592B (en) The structure and production method of fan-out package
CN107017238A (en) Electronic installation
CN107123605A (en) Semiconductor package part and its technique of doing over again
CN101211874A (en) Structure of super thin chip scale package and method of the same
CN105226036B (en) The packaging method and encapsulating structure of image sensing chip
CN103811394B (en) Carrier wafer and manufacture method thereof and method for packing
CN101232008A (en) Multi-chips package and method of forming the same
CN105621345B (en) The encapsulating structure and packaging method that MEMS chip integrates
CN105244341A (en) Semiconductor device FOWLP packaging structure and manufacturing method thereof
CN108122784A (en) The method for encapsulating singulation
CN106653628B (en) A kind of semiconductor memory and preparation method thereof
CN105655320B (en) Low-cost chip back silicon through hole interconnection structure and preparation method thereof
CN101252092B (en) Multi-chip packaging structure and making method thereof
TWI233188B (en) Quad flat no-lead package structure and manufacturing method thereof
CN107078068B (en) The packaging method and packaging body of wafer stage chip
CN101562138B (en) Method for producing semiconductor packaging part
CN107068578A (en) The preparation method and sensor-packaging structure of sensor-packaging structure
CN209216923U (en) Fan-out-type wafer level packaging structure
CN109545805A (en) A kind of semiconductor chip packaging method
CN107086177B (en) Semiconductor wafer level packaging method and cutter for semiconductor wafer level packaging method
CN112908947A (en) Plastic package structure and manufacturing method thereof
CN107093579A (en) Semiconductor wafer level packaging methods, device and encapsulation cutter

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant